1 /* 2 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * DOC: This file contains definitions of Data Path configuration. 22 */ 23 24 #ifndef _CFG_DP_H_ 25 #define _CFG_DP_H_ 26 27 #include "cfg_define.h" 28 #include "wlan_init_cfg.h" 29 30 #define WLAN_CFG_MAX_CLIENTS 64 31 #define WLAN_CFG_MAX_CLIENTS_MIN 8 32 #define WLAN_CFG_MAX_CLIENTS_MAX 64 33 34 /* Change this to a lower value to enforce scattered idle list mode */ 35 #define WLAN_CFG_MAX_ALLOC_SIZE 0x200000 36 #define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000 37 #define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000 38 39 #if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \ 40 defined(QCA_LL_PDEV_TX_FLOW_CONTROL) 41 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10 42 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15 43 #else 44 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 45 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 46 #endif 47 48 #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0 49 #define WLAN_CFG_PER_PDEV_TX_RING_MAX 1 50 51 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 52 #define WLAN_CFG_PER_PDEV_RX_RING 0 53 #define WLAN_CFG_PER_PDEV_LMAC_RING 0 54 #define WLAN_LRO_ENABLE 0 55 #ifdef QCA_WIFI_QCA6750 56 #define WLAN_CFG_MAC_PER_TARGET 1 57 #else 58 #define WLAN_CFG_MAC_PER_TARGET 2 59 #endif 60 #ifdef IPA_OFFLOAD 61 /* Size of TCL TX Ring */ 62 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 63 #define WLAN_CFG_TX_RING_SIZE 2048 64 #else 65 #define WLAN_CFG_TX_RING_SIZE 1024 66 #endif 67 68 #define WLAN_CFG_IPA_TX_RING_SIZE_MIN 1024 69 #define WLAN_CFG_IPA_TX_RING_SIZE 1024 70 #define WLAN_CFG_IPA_TX_RING_SIZE_MAX 8096 71 72 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN 1024 73 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE 1024 74 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX 8096 75 76 #ifdef IPA_WDI3_TX_TWO_PIPES 77 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN 1024 78 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE 1024 79 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX 8096 80 81 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN 1024 82 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE 1024 83 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX 8096 84 #endif 85 86 #define WLAN_CFG_PER_PDEV_TX_RING 0 87 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048 88 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000 89 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024 90 #else 91 #define WLAN_CFG_TX_RING_SIZE 512 92 #define WLAN_CFG_PER_PDEV_TX_RING 1 93 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 94 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 95 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 96 #endif 97 98 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 99 #define WLAN_CFG_TX_COMP_RING_SIZE 4096 100 101 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 102 #define WLAN_CFG_NUM_TX_DESC 4096 103 #define WLAN_CFG_NUM_TX_EXT_DESC 4096 104 #else 105 #define WLAN_CFG_TX_COMP_RING_SIZE 1024 106 107 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 108 #define WLAN_CFG_NUM_TX_DESC 1024 109 #define WLAN_CFG_NUM_TX_EXT_DESC 1024 110 #endif 111 112 /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 113 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1 114 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 115 116 /* Interrupt Mitigation - Timer threshold in us */ 117 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8 118 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8 119 120 #ifdef WLAN_DP_PER_RING_TYPE_CONFIG 121 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX \ 122 WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 123 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX \ 124 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 125 #else 126 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1 127 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8 128 #endif 129 #endif 130 131 #ifdef NBUF_MEMORY_DEBUG 132 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0xFFFF 133 #else 134 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0x1FFFF 135 #endif 136 137 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD \ 138 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 139 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN 0 140 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX 0x200000 141 142 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD \ 143 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 144 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN 100 145 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX 0x200000 146 147 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256 148 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 512 149 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 0 150 151 #define WLAN_CFG_PER_PDEV_RX_RING_MIN 0 152 #define WLAN_CFG_PER_PDEV_RX_RING_MAX 0 153 154 #define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0 155 #define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1 156 157 #define WLAN_CFG_TX_RING_SIZE_MIN 512 158 #define WLAN_CFG_TX_RING_SIZE_MAX 0x80000 159 160 #define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512 161 #define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000 162 163 #define WLAN_CFG_NUM_TX_DESC_MIN 16 164 #define WLAN_CFG_NUM_TX_DESC_MAX 32768 165 166 #define WLAN_CFG_NUM_TX_EXT_DESC_MIN 16 167 #define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000 168 169 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1 170 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256 171 172 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 0 173 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128 174 175 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1 176 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128 177 178 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1 179 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128 180 181 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1 182 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1 183 184 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8 185 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 1000 186 187 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8 188 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500 189 190 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8 191 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000 192 193 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8 194 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 512 195 196 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8 197 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500 198 199 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000 200 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000 201 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000 202 203 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 204 205 /* Per vdev pools */ 206 #define WLAN_CFG_NUM_TX_DESC_POOL 3 207 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 208 209 #else /* QCA_LL_TX_FLOW_CONTROL_V2 */ 210 211 #ifdef TX_PER_PDEV_DESC_POOL 212 #define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT 213 #define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT 214 215 #else /* TX_PER_PDEV_DESC_POOL */ 216 217 #define WLAN_CFG_NUM_TX_DESC_POOL 3 218 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 219 220 #endif /* TX_PER_PDEV_DESC_POOL */ 221 #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */ 222 223 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1 224 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4 225 226 #define WLAN_CFG_HTT_PKT_TYPE 2 227 #define WLAN_CFG_HTT_PKT_TYPE_MIN 2 228 #define WLAN_CFG_HTT_PKT_TYPE_MAX 2 229 230 #define WLAN_CFG_MAX_PEER_ID 64 231 #define WLAN_CFG_MAX_PEER_ID_MIN 64 232 #define WLAN_CFG_MAX_PEER_ID_MAX 64 233 234 #define WLAN_CFG_RX_DEFRAG_TIMEOUT 100 235 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100 236 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100 237 238 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 239 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 1 240 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX MAX_TCL_DATA_RINGS 241 242 #if defined(CONFIG_BERYLLIUM) 243 #define WLAN_CFG_NUM_REO_DEST_RING 8 244 #else 245 #define WLAN_CFG_NUM_REO_DEST_RING 4 246 #endif 247 #define WLAN_CFG_NUM_REO_DEST_RING_MIN 4 248 #define WLAN_CFG_NUM_REO_DEST_RING_MAX MAX_REO_DEST_RINGS 249 250 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS 2 251 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN 1 252 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX 3 253 254 #define WLAN_CFG_NSS_NUM_REO_DEST_RING 2 255 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN 1 256 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX 3 257 258 #define WLAN_CFG_WBM_RELEASE_RING_SIZE 1024 259 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64 260 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 1024 261 262 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE 512 263 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN 32 264 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX 512 265 266 #define WLAN_CFG_TCL_STATUS_RING_SIZE 32 267 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32 268 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32 269 270 #if defined(QCA_WIFI_QCA6290) 271 #define WLAN_CFG_REO_DST_RING_SIZE 1024 272 #else 273 #define WLAN_CFG_REO_DST_RING_SIZE 2048 274 #endif 275 276 #define WLAN_CFG_REO_DST_RING_SIZE_MIN 8 277 #define WLAN_CFG_REO_DST_RING_SIZE_MAX 8192 278 279 #define WLAN_CFG_REO_REINJECT_RING_SIZE 128 280 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32 281 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 128 282 283 #define WLAN_CFG_RX_RELEASE_RING_SIZE 1024 284 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8 285 #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 286 defined(QCA_WIFI_QCA6750) || defined(QCA_WIFI_WCN7850) 287 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024 288 #else 289 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 8192 290 #endif 291 292 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE 256 293 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128 294 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 512 295 296 #define WLAN_CFG_REO_CMD_RING_SIZE 128 297 #define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64 298 #define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128 299 300 #define WLAN_CFG_REO_STATUS_RING_SIZE 256 301 #define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128 302 #define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048 303 304 #define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024 305 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024 306 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 1024 307 308 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096 309 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16 310 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 4096 311 312 #define WLAN_CFG_TX_DESC_LIMIT_0 0 313 #define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096 314 #define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768 315 316 #define WLAN_CFG_TX_DESC_LIMIT_1 0 317 #define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096 318 #define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768 319 320 #define WLAN_CFG_TX_DESC_LIMIT_2 0 321 #define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096 322 #define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768 323 324 #define WLAN_CFG_TX_DEVICE_LIMIT 65536 325 #define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384 326 #define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536 327 328 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024 329 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128 330 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024 331 332 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096 333 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16 334 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192 335 336 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE 4096 337 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN 16 338 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX 8192 339 340 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048 341 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48 342 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192 343 344 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE 2048 345 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN 48 346 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX 4096 347 348 #define WLAN_CFG_TX_MONITOR_BUF_SIZE 2048 349 #define WLAN_CFG_TX_MONITOR_BUF_SIZE_MIN 48 350 #define WLAN_CFG_TX_MONITOR_BUF_SIZE_MAX 8192 351 352 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024 353 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16 354 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192 355 356 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096 357 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096 358 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384 359 360 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024 361 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024 362 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192 363 364 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE 32 365 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN 0 366 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX 256 367 368 /** 369 * Allocate as many RX descriptors as buffers in the SW2RXDMA 370 * ring. This value may need to be tuned later. 371 */ 372 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 373 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 374 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 375 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 1 376 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 377 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 378 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 4096 379 380 /** 381 * For low memory AP cases using 1 will reduce the rx descriptors memory req 382 */ 383 #elif defined(QCA_LOWMEM_CONFIG) || defined(QCA_512M_CONFIG) 384 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 385 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 386 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 387 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 388 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 389 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 12288 390 391 /** 392 * AP use cases need to allocate more RX Descriptors than the number of 393 * entries avaialable in the SW2RXDMA buffer replenish ring. This is to account 394 * for frames sitting in REO queues, HW-HW DMA rings etc. Hence using a 395 * multiplication factor of 3, to allocate three times as many RX descriptors 396 * as RX buffers. 397 */ 398 #else 399 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 3 400 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 401 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 402 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 12288 403 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 4096 404 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 12288 405 #endif 406 407 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE 16384 408 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN 1 409 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX 16384 410 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT 128 411 412 #define WLAN_CFG_PKTLOG_BUFFER_SIZE 10 413 #define WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE 1 414 #define WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE 10 415 416 #ifdef QCA_WIFI_WCN7850 417 #define WLAN_CFG_NUM_REO_RINGS_MAP 0x7 418 #else 419 #define WLAN_CFG_NUM_REO_RINGS_MAP 0xF 420 #endif 421 #define WLAN_CFG_NUM_REO_RINGS_MAP_MIN 0x1 422 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xF 423 424 #define WLAN_CFG_RADIO_0_DEFAULT_REO 0x1 425 #define WLAN_CFG_RADIO_1_DEFAULT_REO 0x2 426 #define WLAN_CFG_RADIO_2_DEFAULT_REO 0x3 427 428 #define WLAN_CFG_RADIO_DEFAULT_REO_MIN 0x1 429 #define WLAN_CFG_RADIO_DEFAULT_REO_MAX 0x4 430 431 #define WLAN_CFG_REO2PPE_RING_SIZE 1024 432 #define WLAN_CFG_REO2PPE_RING_SIZE_MIN 64 433 #define WLAN_CFG_REO2PPE_RING_SIZE_MAX 1024 434 435 #define WLAN_CFG_PPE2TCL_RING_SIZE 1024 436 #define WLAN_CFG_PPE2TCL_RING_SIZE_MIN 64 437 #define WLAN_CFG_PPE2TCL_RING_SIZE_MAX 1024 438 439 #define WLAN_CFG_PPE_RELEASE_RING_SIZE 1024 440 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MIN 64 441 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MAX 1024 442 443 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 444 #define WLAN_CFG_MLO_RX_RING_MAP 0xF 445 #define WLAN_CFG_MLO_RX_RING_MAP_MIN 0x0 446 #define WLAN_CFG_MLO_RX_RING_MAP_MAX 0xFF 447 #endif 448 449 /* DP INI Declerations */ 450 #define CFG_DP_HTT_PACKET_TYPE \ 451 CFG_INI_UINT("dp_htt_packet_type", \ 452 WLAN_CFG_HTT_PKT_TYPE_MIN, \ 453 WLAN_CFG_HTT_PKT_TYPE_MAX, \ 454 WLAN_CFG_HTT_PKT_TYPE, \ 455 CFG_VALUE_OR_DEFAULT, "DP HTT packet type") 456 457 #define CFG_DP_INT_BATCH_THRESHOLD_OTHER \ 458 CFG_INI_UINT("dp_int_batch_threshold_other", \ 459 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \ 460 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \ 461 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \ 462 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other") 463 464 #define CFG_DP_INT_BATCH_THRESHOLD_RX \ 465 CFG_INI_UINT("dp_int_batch_threshold_rx", \ 466 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \ 467 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \ 468 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \ 469 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx") 470 471 #define CFG_DP_INT_BATCH_THRESHOLD_TX \ 472 CFG_INI_UINT("dp_int_batch_threshold_tx", \ 473 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \ 474 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \ 475 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \ 476 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx") 477 478 #define CFG_DP_INT_TIMER_THRESHOLD_OTHER \ 479 CFG_INI_UINT("dp_int_timer_threshold_other", \ 480 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \ 481 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \ 482 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \ 483 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other") 484 485 #define CFG_DP_INT_TIMER_THRESHOLD_RX \ 486 CFG_INI_UINT("dp_int_timer_threshold_rx", \ 487 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \ 488 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \ 489 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \ 490 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx") 491 492 #define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \ 493 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \ 494 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \ 495 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \ 496 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \ 497 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring") 498 499 #define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \ 500 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \ 501 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \ 502 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \ 503 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \ 504 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring") 505 506 #define CFG_DP_INT_TIMER_THRESHOLD_TX \ 507 CFG_INI_UINT("dp_int_timer_threshold_tx", \ 508 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \ 509 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \ 510 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \ 511 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx") 512 513 #define CFG_DP_MAX_ALLOC_SIZE \ 514 CFG_INI_UINT("dp_max_alloc_size", \ 515 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \ 516 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \ 517 WLAN_CFG_MAX_ALLOC_SIZE, \ 518 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size") 519 520 #define CFG_DP_MAX_CLIENTS \ 521 CFG_INI_UINT("dp_max_clients", \ 522 WLAN_CFG_MAX_CLIENTS_MIN, \ 523 WLAN_CFG_MAX_CLIENTS_MAX, \ 524 WLAN_CFG_MAX_CLIENTS, \ 525 CFG_VALUE_OR_DEFAULT, "DP Max Clients") 526 527 #define CFG_DP_MAX_PEER_ID \ 528 CFG_INI_UINT("dp_max_peer_id", \ 529 WLAN_CFG_MAX_PEER_ID_MIN, \ 530 WLAN_CFG_MAX_PEER_ID_MAX, \ 531 WLAN_CFG_MAX_PEER_ID, \ 532 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID") 533 534 #define CFG_DP_REO_DEST_RINGS \ 535 CFG_INI_UINT("dp_reo_dest_rings", \ 536 WLAN_CFG_NUM_REO_DEST_RING_MIN, \ 537 WLAN_CFG_NUM_REO_DEST_RING_MAX, \ 538 WLAN_CFG_NUM_REO_DEST_RING, \ 539 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings") 540 541 #define CFG_DP_TCL_DATA_RINGS \ 542 CFG_INI_UINT("dp_tcl_data_rings", \ 543 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \ 544 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \ 545 WLAN_CFG_NUM_TCL_DATA_RINGS, \ 546 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings") 547 548 #define CFG_DP_NSS_REO_DEST_RINGS \ 549 CFG_INI_UINT("dp_nss_reo_dest_rings", \ 550 WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN, \ 551 WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX, \ 552 WLAN_CFG_NSS_NUM_REO_DEST_RING, \ 553 CFG_VALUE_OR_DEFAULT, "DP NSS REO Destination Rings") 554 555 #define CFG_DP_NSS_TCL_DATA_RINGS \ 556 CFG_INI_UINT("dp_nss_tcl_data_rings", \ 557 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN, \ 558 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX, \ 559 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS, \ 560 CFG_VALUE_OR_DEFAULT, "DP NSS TCL Data Rings") 561 562 #define CFG_DP_TX_DESC \ 563 CFG_INI_UINT("dp_tx_desc", \ 564 WLAN_CFG_NUM_TX_DESC_MIN, \ 565 WLAN_CFG_NUM_TX_DESC_MAX, \ 566 WLAN_CFG_NUM_TX_DESC, \ 567 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors") 568 569 #define CFG_DP_TX_EXT_DESC \ 570 CFG_INI_UINT("dp_tx_ext_desc", \ 571 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \ 572 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \ 573 WLAN_CFG_NUM_TX_EXT_DESC, \ 574 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors") 575 576 #define CFG_DP_TX_EXT_DESC_POOLS \ 577 CFG_INI_UINT("dp_tx_ext_desc_pool", \ 578 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \ 579 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \ 580 WLAN_CFG_NUM_TXEXT_DESC_POOL, \ 581 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool") 582 583 #define CFG_DP_PDEV_RX_RING \ 584 CFG_INI_UINT("dp_pdev_rx_ring", \ 585 WLAN_CFG_PER_PDEV_RX_RING_MIN, \ 586 WLAN_CFG_PER_PDEV_RX_RING_MAX, \ 587 WLAN_CFG_PER_PDEV_RX_RING, \ 588 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring") 589 590 #define CFG_DP_PDEV_TX_RING \ 591 CFG_INI_UINT("dp_pdev_tx_ring", \ 592 WLAN_CFG_PER_PDEV_TX_RING_MIN, \ 593 WLAN_CFG_PER_PDEV_TX_RING_MAX, \ 594 WLAN_CFG_PER_PDEV_TX_RING, \ 595 CFG_VALUE_OR_DEFAULT, \ 596 "DP PDEV Tx Ring") 597 598 #define CFG_DP_RX_DEFRAG_TIMEOUT \ 599 CFG_INI_UINT("dp_rx_defrag_timeout", \ 600 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \ 601 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \ 602 WLAN_CFG_RX_DEFRAG_TIMEOUT, \ 603 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout") 604 605 #define CFG_DP_TX_COMPL_RING_SIZE \ 606 CFG_INI_UINT("dp_tx_compl_ring_size", \ 607 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \ 608 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \ 609 WLAN_CFG_TX_COMP_RING_SIZE, \ 610 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size") 611 612 #define CFG_DP_TX_RING_SIZE \ 613 CFG_INI_UINT("dp_tx_ring_size", \ 614 WLAN_CFG_TX_RING_SIZE_MIN,\ 615 WLAN_CFG_TX_RING_SIZE_MAX,\ 616 WLAN_CFG_TX_RING_SIZE,\ 617 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size") 618 619 #define CFG_DP_NSS_COMP_RING_SIZE \ 620 CFG_INI_UINT("dp_nss_comp_ring_size", \ 621 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \ 622 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \ 623 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \ 624 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size") 625 626 #define CFG_DP_PDEV_LMAC_RING \ 627 CFG_INI_UINT("dp_pdev_lmac_ring", \ 628 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \ 629 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \ 630 WLAN_CFG_PER_PDEV_LMAC_RING, \ 631 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring") 632 /* 633 * <ini> 634 * dp_rx_pending_hl_threshold - High threshold of frame number to start 635 * frame dropping scheme 636 * @Min: 0 637 * @Max: 524288 638 * @Default: 393216 639 * 640 * This ini entry is used to set a high limit threshold to start frame 641 * dropping scheme 642 * 643 * Usage: External 644 * 645 * </ini> 646 */ 647 #define CFG_DP_RX_PENDING_HL_THRESHOLD \ 648 CFG_INI_UINT("dp_rx_pending_hl_threshold", \ 649 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN, \ 650 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX, \ 651 WLAN_CFG_RX_PENDING_HL_THRESHOLD, \ 652 CFG_VALUE_OR_DEFAULT, "DP rx pending hl threshold") 653 654 /* 655 * <ini> 656 * dp_rx_pending_lo_threshold - Low threshold of frame number to stop 657 * frame dropping scheme 658 * @Min: 100 659 * @Max: 524288 660 * @Default: 393216 661 * 662 * This ini entry is used to set a low limit threshold to stop frame 663 * dropping scheme 664 * 665 * Usage: External 666 * 667 * </ini> 668 */ 669 #define CFG_DP_RX_PENDING_LO_THRESHOLD \ 670 CFG_INI_UINT("dp_rx_pending_lo_threshold", \ 671 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN, \ 672 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX, \ 673 WLAN_CFG_RX_PENDING_LO_THRESHOLD, \ 674 CFG_VALUE_OR_DEFAULT, "DP rx pending lo threshold") 675 676 #define CFG_DP_BASE_HW_MAC_ID \ 677 CFG_INI_UINT("dp_base_hw_macid", \ 678 0, 1, 1, \ 679 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID") 680 681 #define CFG_DP_RX_HASH \ 682 CFG_INI_BOOL("dp_rx_hash", true, \ 683 "DP Rx Hash") 684 685 #define CFG_DP_TSO \ 686 CFG_INI_BOOL("TSOEnable", false, \ 687 "DP TSO Enabled") 688 689 #define CFG_DP_LRO \ 690 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \ 691 "DP LRO Enable") 692 693 /* 694 * <ini> 695 * CFG_DP_SG - Enable the SG feature standalonely 696 * @Min: 0 697 * @Max: 1 698 * @Default: 1 699 * 700 * This ini entry is used to enable/disable SG feature standalonely. 701 * Also does Rome support SG on TX, lithium does not. 702 * For example the lithium does not support SG on UDP frames. 703 * Which is able to handle SG only for TSO frames(in case TSO is enabled). 704 * 705 * Usage: External 706 * 707 * </ini> 708 */ 709 #define CFG_DP_SG \ 710 CFG_INI_BOOL("dp_sg_support", false, \ 711 "DP SG Enable") 712 713 #define WLAN_CFG_GRO_ENABLE_MIN 0 714 #define WLAN_CFG_GRO_ENABLE_MAX 3 715 #define WLAN_CFG_GRO_ENABLE_DEFAULT 0 716 #define DP_GRO_ENABLE_BIT_SET BIT(0) 717 #define DP_FORCE_USE_GRO_BIT_SET BIT(1) 718 /* 719 * <ini> 720 * CFG_DP_GRO - Enable the GRO feature standalonely 721 * @Min: 0 722 * @Max: 3 723 * @Default: 0 724 * 725 * This ini entry is used to enable/disable GRO feature standalonely. 726 * Value 0: Disable GRO feature 727 * Value 1: Enable Dynamic GRO feature, TC rule can control GRO 728 * behavior of STA mode 729 * Value 3: Enable GRO feature forcibly 730 * 731 * Usage: External 732 * 733 * </ini> 734 */ 735 #define CFG_DP_GRO \ 736 CFG_INI_UINT("GROEnable", \ 737 WLAN_CFG_GRO_ENABLE_MIN, \ 738 WLAN_CFG_GRO_ENABLE_MAX, \ 739 WLAN_CFG_GRO_ENABLE_DEFAULT, \ 740 CFG_VALUE_OR_DEFAULT, "DP GRO Enable") 741 742 #define CFG_DP_OL_TX_CSUM \ 743 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \ 744 "DP tx csum Enable") 745 746 #define CFG_DP_OL_RX_CSUM \ 747 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \ 748 "DP rx csum Enable") 749 750 #define CFG_DP_RAWMODE \ 751 CFG_INI_BOOL("dp_rawmode_support", false, \ 752 "DP rawmode Enable") 753 754 #define CFG_DP_PEER_FLOW_CTRL \ 755 CFG_INI_BOOL("dp_peer_flow_control_support", false, \ 756 "DP peer flow ctrl Enable") 757 758 #define CFG_DP_NAPI \ 759 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \ 760 "DP Napi Enabled") 761 /* 762 * <ini> 763 * gEnableP2pIpTcpUdpChecksumOffload - Enable checksum offload for P2P mode 764 * @Min: 0 765 * @Max: 1 766 * @Default: 1 767 * 768 * This ini entry is used to enable/disable TX checksum(UDP/TCP) for P2P modes. 769 * This includes P2P device mode, P2P client mode and P2P GO mode. 770 * The feature is enabled by default. To disable TX checksum for P2P, add the 771 * following entry in ini file: 772 * gEnableP2pIpTcpUdpChecksumOffload=0 773 * 774 * Usage: External 775 * 776 * </ini> 777 */ 778 #define CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD \ 779 CFG_INI_BOOL("gEnableP2pIpTcpUdpChecksumOffload", true, \ 780 "DP TCP UDP Checksum Offload for P2P mode (device/cli/go)") 781 782 /* 783 * <ini> 784 * gEnableNanIpTcpUdpChecksumOffload - Enable checksum offload for NAN mode 785 * @Min: 0 786 * @Max: 1 787 * @Default: 1 788 * 789 * Usage: External 790 * 791 * </ini> 792 */ 793 #define CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD \ 794 CFG_INI_BOOL("gEnableNanIpTcpUdpChecksumOffload", true, \ 795 "DP TCP UDP Checksum Offload for NAN mode") 796 797 /* 798 * <ini> 799 * gEnableIpTcpUdpChecksumOffload - Enable checksum offload 800 * @Min: 0 801 * @Max: 1 802 * @Default: 1 803 * 804 * Usage: External 805 * 806 * </ini> 807 */ 808 #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \ 809 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \ 810 "DP TCP UDP Checksum Offload") 811 812 #define CFG_DP_DEFRAG_TIMEOUT_CHECK \ 813 CFG_INI_BOOL("dp_defrag_timeout_check", true, \ 814 "DP Defrag Timeout Check") 815 816 #define CFG_DP_WBM_RELEASE_RING \ 817 CFG_INI_UINT("dp_wbm_release_ring", \ 818 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \ 819 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \ 820 WLAN_CFG_WBM_RELEASE_RING_SIZE, \ 821 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring") 822 823 #define CFG_DP_TCL_CMD_CREDIT_RING \ 824 CFG_INI_UINT("dp_tcl_cmd_credit_ring", \ 825 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN, \ 826 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX, \ 827 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE, \ 828 CFG_VALUE_OR_DEFAULT, "DP TCL Cmd_Credit ring") 829 830 #define CFG_DP_TCL_STATUS_RING \ 831 CFG_INI_UINT("dp_tcl_status_ring",\ 832 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \ 833 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \ 834 WLAN_CFG_TCL_STATUS_RING_SIZE, \ 835 CFG_VALUE_OR_DEFAULT, "DP TCL status ring") 836 837 #define CFG_DP_REO_REINJECT_RING \ 838 CFG_INI_UINT("dp_reo_reinject_ring", \ 839 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \ 840 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \ 841 WLAN_CFG_REO_REINJECT_RING_SIZE, \ 842 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring") 843 844 #define CFG_DP_RX_RELEASE_RING \ 845 CFG_INI_UINT("dp_rx_release_ring", \ 846 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \ 847 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \ 848 WLAN_CFG_RX_RELEASE_RING_SIZE, \ 849 CFG_VALUE_OR_DEFAULT, "DP Rx release ring") 850 851 #define CFG_DP_RX_DESTINATION_RING \ 852 CFG_INI_UINT("dp_reo_dst_ring", \ 853 WLAN_CFG_REO_DST_RING_SIZE_MIN, \ 854 WLAN_CFG_REO_DST_RING_SIZE_MAX, \ 855 WLAN_CFG_REO_DST_RING_SIZE, \ 856 CFG_VALUE_OR_DEFAULT, "DP REO destination ring") 857 858 #define CFG_DP_REO_EXCEPTION_RING \ 859 CFG_INI_UINT("dp_reo_exception_ring", \ 860 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \ 861 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \ 862 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \ 863 CFG_VALUE_OR_DEFAULT, "DP REO exception ring") 864 865 #define CFG_DP_REO_CMD_RING \ 866 CFG_INI_UINT("dp_reo_cmd_ring", \ 867 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \ 868 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \ 869 WLAN_CFG_REO_CMD_RING_SIZE, \ 870 CFG_VALUE_OR_DEFAULT, "DP REO command ring") 871 872 #define CFG_DP_REO_STATUS_RING \ 873 CFG_INI_UINT("dp_reo_status_ring", \ 874 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \ 875 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \ 876 WLAN_CFG_REO_STATUS_RING_SIZE, \ 877 CFG_VALUE_OR_DEFAULT, "DP REO status ring") 878 879 #define CFG_DP_RXDMA_BUF_RING \ 880 CFG_INI_UINT("dp_rxdma_buf_ring", \ 881 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \ 882 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \ 883 WLAN_CFG_RXDMA_BUF_RING_SIZE, \ 884 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring") 885 886 #define CFG_DP_RXDMA_REFILL_RING \ 887 CFG_INI_UINT("dp_rxdma_refill_ring", \ 888 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \ 889 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \ 890 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \ 891 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring") 892 893 #define CFG_DP_TX_DESC_LIMIT_0 \ 894 CFG_INI_UINT("dp_tx_desc_limit_0", \ 895 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \ 896 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \ 897 WLAN_CFG_TX_DESC_LIMIT_0, \ 898 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0") 899 900 #define CFG_DP_TX_DESC_LIMIT_1 \ 901 CFG_INI_UINT("dp_tx_desc_limit_1", \ 902 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \ 903 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \ 904 WLAN_CFG_TX_DESC_LIMIT_1, \ 905 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1") 906 907 #define CFG_DP_TX_DESC_LIMIT_2 \ 908 CFG_INI_UINT("dp_tx_desc_limit_2", \ 909 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \ 910 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \ 911 WLAN_CFG_TX_DESC_LIMIT_2, \ 912 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2") 913 914 #define CFG_DP_TX_DEVICE_LIMIT \ 915 CFG_INI_UINT("dp_tx_device_limit", \ 916 WLAN_CFG_TX_DEVICE_LIMIT_MIN, \ 917 WLAN_CFG_TX_DEVICE_LIMIT_MAX, \ 918 WLAN_CFG_TX_DEVICE_LIMIT, \ 919 CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit") 920 921 #define CFG_DP_TX_SW_INTERNODE_QUEUE \ 922 CFG_INI_UINT("dp_tx_sw_internode_queue", \ 923 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \ 924 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \ 925 WLAN_CFG_TX_SW_INTERNODE_QUEUE, \ 926 CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue") 927 928 #define CFG_DP_RXDMA_MONITOR_BUF_RING \ 929 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \ 930 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \ 931 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \ 932 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \ 933 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring") 934 935 #define CFG_DP_TX_MONITOR_BUF_RING \ 936 CFG_INI_UINT("dp_tx_monitor_buf_ring", \ 937 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN, \ 938 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX, \ 939 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE, \ 940 CFG_VALUE_OR_DEFAULT, "DP TX monitor buffer ring") 941 942 #define CFG_DP_RXDMA_MONITOR_DST_RING \ 943 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \ 944 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \ 945 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \ 946 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \ 947 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 948 949 #define CFG_DP_TX_MONITOR_DST_RING \ 950 CFG_INI_UINT("dp_tx_monitor_dst_ring", \ 951 WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN, \ 952 WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX, \ 953 WLAN_CFG_TX_MONITOR_DST_RING_SIZE, \ 954 CFG_VALUE_OR_DEFAULT, "DP TX monitor destination ring") 955 956 #define CFG_DP_RXDMA_MONITOR_STATUS_RING \ 957 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \ 958 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \ 959 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \ 960 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \ 961 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring") 962 963 #define CFG_DP_RXDMA_MONITOR_DESC_RING \ 964 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \ 965 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \ 966 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \ 967 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \ 968 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 969 970 #define CFG_DP_RXDMA_ERR_DST_RING \ 971 CFG_INI_UINT("dp_rxdma_err_dst_ring", \ 972 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \ 973 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \ 974 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \ 975 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring") 976 977 #define CFG_DP_PER_PKT_LOGGING \ 978 CFG_INI_UINT("enable_verbose_debug", \ 979 0, 0xffff, 0, \ 980 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging") 981 982 #define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \ 983 CFG_INI_UINT("TxFlowStartQueueOffset", \ 984 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \ 985 CFG_VALUE_OR_DEFAULT, "Start queue offset") 986 987 #define CFG_DP_TX_FLOW_STOP_QUEUE_TH \ 988 CFG_INI_UINT("TxFlowStopQueueThreshold", \ 989 0, 50, 15, \ 990 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold") 991 992 #define CFG_DP_IPA_UC_TX_BUF_SIZE \ 993 CFG_INI_UINT("IpaUcTxBufSize", \ 994 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \ 995 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size") 996 997 #define CFG_DP_IPA_UC_TX_PARTITION_BASE \ 998 CFG_INI_UINT("IpaUcTxPartitionBase", \ 999 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \ 1000 CFG_VALUE_OR_DEFAULT, "IPA tx partition base") 1001 1002 #define CFG_DP_IPA_UC_RX_IND_RING_COUNT \ 1003 CFG_INI_UINT("IpaUcRxIndRingCount", \ 1004 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \ 1005 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count") 1006 1007 #define CFG_DP_AP_STA_SECURITY_SEPERATION \ 1008 CFG_INI_BOOL("gDisableIntraBssFwd", \ 1009 false, "Disable intrs BSS Rx packets") 1010 1011 #define CFG_DP_ENABLE_DATA_STALL_DETECTION \ 1012 CFG_INI_BOOL("gEnableDataStallDetection", \ 1013 true, "Enable/Disable Data stall detection") 1014 1015 #define CFG_DP_RX_SW_DESC_WEIGHT \ 1016 CFG_INI_UINT("dp_rx_sw_desc_weight", \ 1017 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN, \ 1018 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX, \ 1019 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE, \ 1020 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC weight") 1021 1022 #define CFG_DP_RX_SW_DESC_NUM \ 1023 CFG_INI_UINT("dp_rx_sw_desc_num", \ 1024 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN, \ 1025 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX, \ 1026 WLAN_CFG_RX_SW_DESC_NUM_SIZE, \ 1027 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC num") 1028 1029 #define CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE \ 1030 CFG_INI_UINT("dp_rx_flow_search_table_size", \ 1031 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN, \ 1032 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX, \ 1033 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT, \ 1034 CFG_VALUE_OR_DEFAULT, \ 1035 "DP Rx Flow Search Table Size in number of entries") 1036 1037 #define CFG_DP_RX_FLOW_TAG_ENABLE \ 1038 CFG_INI_BOOL("dp_rx_flow_tag_enable", false, \ 1039 "Enable/Disable DP Rx Flow Tag") 1040 1041 #define CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV \ 1042 CFG_INI_BOOL("dp_rx_per_pdev_flow_search", false, \ 1043 "DP Rx Flow Search Table Is Per PDev") 1044 1045 #define CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE \ 1046 CFG_INI_BOOL("dp_rx_monitor_protocol_flow_tag_enable", true, \ 1047 "Enable/Disable Rx Protocol & Flow tags in Monitor mode") 1048 1049 #define CFG_DP_TX_PER_PKT_VDEV_ID_CHECK \ 1050 CFG_INI_BOOL("dp_tx_allow_per_pkt_vdev_id_check", false, \ 1051 "Enable/Disable tx Per Pkt vdev id check") 1052 1053 /* 1054 * <ini> 1055 * dp_rx_fisa_enable - Control Rx datapath FISA 1056 * @Min: 0 1057 * @Max: 1 1058 * @Default: 1 1059 * 1060 * This ini is used to enable DP Rx FISA feature 1061 * 1062 * Related: dp_rx_flow_search_table_size 1063 * 1064 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1065 * 1066 * Usage: Internal 1067 * 1068 * </ini> 1069 */ 1070 #define CFG_DP_RX_FISA_ENABLE \ 1071 CFG_INI_BOOL("dp_rx_fisa_enable", true, \ 1072 "Enable/Disable DP Rx FISA") 1073 1074 #define CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD \ 1075 CFG_INI_UINT("mon_drop_thresh", \ 1076 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN, \ 1077 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX, \ 1078 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE, \ 1079 CFG_VALUE_OR_DEFAULT, "RXDMA monitor rx drop theshold") 1080 1081 #define CFG_DP_PKTLOG_BUFFER_SIZE \ 1082 CFG_INI_UINT("PktlogBufSize", \ 1083 WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE, \ 1084 WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE, \ 1085 WLAN_CFG_PKTLOG_BUFFER_SIZE, \ 1086 CFG_VALUE_OR_DEFAULT, "Packet Log buffer size") 1087 1088 #define CFG_DP_FULL_MON_MODE \ 1089 CFG_INI_BOOL("full_mon_mode", \ 1090 false, "Full Monitor mode support") 1091 1092 #define CFG_DP_REO_RINGS_MAP \ 1093 CFG_INI_UINT("dp_reo_rings_map", \ 1094 WLAN_CFG_NUM_REO_RINGS_MAP_MIN, \ 1095 WLAN_CFG_NUM_REO_RINGS_MAP_MAX, \ 1096 WLAN_CFG_NUM_REO_RINGS_MAP, \ 1097 CFG_VALUE_OR_DEFAULT, "REO Destination Rings Mapping") 1098 1099 #define CFG_DP_RX_RADIO_0_DEFAULT_REO \ 1100 CFG_INI_UINT("dp_rx_radio0_default_reo", \ 1101 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1102 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1103 WLAN_CFG_RADIO_0_DEFAULT_REO, \ 1104 CFG_VALUE_OR_DEFAULT, "Radio0 to REO destination default mapping") 1105 1106 #define CFG_DP_RX_RADIO_1_DEFAULT_REO \ 1107 CFG_INI_UINT("dp_rx_radio1_default_reo", \ 1108 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1109 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1110 WLAN_CFG_RADIO_1_DEFAULT_REO, \ 1111 CFG_VALUE_OR_DEFAULT, "Radio1 to REO destination default mapping") 1112 1113 #define CFG_DP_RX_RADIO_2_DEFAULT_REO \ 1114 CFG_INI_UINT("dp_rx_radio2_default_reo", \ 1115 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1116 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1117 WLAN_CFG_RADIO_2_DEFAULT_REO, \ 1118 CFG_VALUE_OR_DEFAULT, "Radio2 to REO destination default mapping") 1119 1120 #define CFG_DP_PEER_EXT_STATS \ 1121 CFG_INI_BOOL("peer_ext_stats", \ 1122 false, "Peer extended stats") 1123 /* 1124 * <ini> 1125 * legacy_mode_csum_disable - Disable csum offload for legacy 802.11abg modes 1126 * @Min: 0 1127 * @Max: 1 1128 * @Default: Default value indicating if checksum should be disabled for 1129 * legacy WLAN modes 1130 * 1131 * This ini is used to disable HW checksum offload capability for legacy 1132 * connections 1133 * 1134 * Related: gEnableIpTcpUdpChecksumOffload should be enabled 1135 * 1136 * Usage: Internal 1137 * 1138 * </ini> 1139 */ 1140 #ifndef DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1141 #define DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1 1142 #endif 1143 1144 #define CFG_DP_LEGACY_MODE_CSUM_DISABLE \ 1145 CFG_INI_BOOL("legacy_mode_csum_disable", \ 1146 DP_LEGACY_MODE_CSM_DEFAULT_DISABLE, \ 1147 "Enable/Disable legacy mode checksum") 1148 1149 #define CFG_DP_RX_BUFF_POOL_ENABLE \ 1150 CFG_INI_BOOL("dp_rx_buff_prealloc_pool", false, \ 1151 "Enable/Disable DP RX emergency buffer pool support") 1152 1153 #define CFG_DP_RX_REFILL_BUFF_POOL_ENABLE \ 1154 CFG_INI_BOOL("dp_rx_refill_buff_pool", false, \ 1155 "Enable/Disable DP RX refill buffer pool support") 1156 1157 #define CFG_DP_POLL_MODE_ENABLE \ 1158 CFG_INI_BOOL("dp_poll_mode_enable", false, \ 1159 "Enable/Disable Polling mode for data path") 1160 1161 #define CFG_DP_RX_FST_IN_CMEM \ 1162 CFG_INI_BOOL("dp_rx_fst_in_cmem", false, \ 1163 "Enable/Disable flow search table in CMEM") 1164 /* 1165 * <ini> 1166 * gEnableSWLM - Control DP Software latency manager 1167 * @Min: 0 1168 * @Max: 1 1169 * @Default: 0 1170 * 1171 * This ini is used to enable DP Software latency Manager 1172 * 1173 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1174 * 1175 * Usage: Internal 1176 * 1177 * </ini> 1178 */ 1179 #define CFG_DP_SWLM_ENABLE \ 1180 CFG_INI_BOOL("gEnableSWLM", false, \ 1181 "Enable/Disable DP SWLM") 1182 /* 1183 * <ini> 1184 * wow_check_rx_pending_enable - control to check RX frames pending in Wow 1185 * @Min: 0 1186 * @Max: 1 1187 * @Default: 0 1188 * 1189 * This ini is used to control DP Software to perform RX pending check 1190 * before entering WoW mode 1191 * 1192 * Usage: Internal 1193 * 1194 * </ini> 1195 */ 1196 #define CFG_DP_WOW_CHECK_RX_PENDING \ 1197 CFG_INI_BOOL("wow_check_rx_pending_enable", \ 1198 false, \ 1199 "enable rx frame pending check in WoW mode") 1200 #define CFG_DP_DELAY_MON_REPLENISH \ 1201 CFG_INI_BOOL("delay_mon_replenish", \ 1202 true, "Delay Monitor Replenish") 1203 1204 #ifdef QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT 1205 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN 500 1206 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX 2000 1207 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER 500 1208 1209 #define CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG \ 1210 CFG_INI_BOOL("vdev_stats_hw_offload_config", \ 1211 false, "Offload vdev stats to HW") 1212 #define CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER \ 1213 CFG_INI_UINT("vdev_stats_hw_offload_timer", \ 1214 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN, \ 1215 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX, \ 1216 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER, \ 1217 CFG_VALUE_OR_DEFAULT, \ 1218 "vdev stats hw offload timer duration") 1219 #define CFG_DP_VDEV_STATS_HW_OFFLOAD \ 1220 CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG) \ 1221 CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER) 1222 #else 1223 #define CFG_DP_VDEV_STATS_HW_OFFLOAD 1224 #endif 1225 1226 /* 1227 * <ini> 1228 * ghw_cc_enable - enable HW cookie conversion by register 1229 * @Min: 0 1230 * @Max: 1 1231 * @Default: 1 1232 * 1233 * This ini is used to control HW based 20 bits cookie to 64 bits 1234 * Desc virtual address conversion 1235 * 1236 * Usage: Internal 1237 * 1238 * </ini> 1239 */ 1240 #define CFG_DP_HW_CC_ENABLE \ 1241 CFG_INI_BOOL("ghw_cc_enable", \ 1242 true, "Enable/Disable HW cookie conversion") 1243 1244 #ifdef IPA_OFFLOAD 1245 /* 1246 * <ini> 1247 * dp_ipa_tx_ring_size - Set tcl ring size for IPA 1248 * @Min: 1024 1249 * @Max: 8096 1250 * @Default: 1024 1251 * 1252 * This ini sets the tcl ring size for IPA 1253 * 1254 * Related: N/A 1255 * 1256 * Supported Feature: IPA 1257 * 1258 * Usage: Internal 1259 * 1260 * </ini> 1261 */ 1262 #define CFG_DP_IPA_TX_RING_SIZE \ 1263 CFG_INI_UINT("dp_ipa_tx_ring_size", \ 1264 WLAN_CFG_IPA_TX_RING_SIZE_MIN, \ 1265 WLAN_CFG_IPA_TX_RING_SIZE_MAX, \ 1266 WLAN_CFG_IPA_TX_RING_SIZE, \ 1267 CFG_VALUE_OR_DEFAULT, "IPA TCL ring size") 1268 1269 /* 1270 * <ini> 1271 * dp_ipa_tx_comp_ring_size - Set tx comp ring size for IPA 1272 * @Min: 1024 1273 * @Max: 8096 1274 * @Default: 1024 1275 * 1276 * This ini sets the tx comp ring size for IPA 1277 * 1278 * Related: N/A 1279 * 1280 * Supported Feature: IPA 1281 * 1282 * Usage: Internal 1283 * 1284 * </ini> 1285 */ 1286 #define CFG_DP_IPA_TX_COMP_RING_SIZE \ 1287 CFG_INI_UINT("dp_ipa_tx_comp_ring_size", \ 1288 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN, \ 1289 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX, \ 1290 WLAN_CFG_IPA_TX_COMP_RING_SIZE, \ 1291 CFG_VALUE_OR_DEFAULT, "IPA tx comp ring size") 1292 1293 #ifdef IPA_WDI3_TX_TWO_PIPES 1294 /* 1295 * <ini> 1296 * dp_ipa_tx_alt_ring_size - Set alt tcl ring size for IPA 1297 * @Min: 1024 1298 * @Max: 8096 1299 * @Default: 1024 1300 * 1301 * This ini sets the alt tcl ring size for IPA 1302 * 1303 * Related: N/A 1304 * 1305 * Supported Feature: IPA 1306 * 1307 * Usage: Internal 1308 * 1309 * </ini> 1310 */ 1311 #define CFG_DP_IPA_TX_ALT_RING_SIZE \ 1312 CFG_INI_UINT("dp_ipa_tx_alt_ring_size", \ 1313 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN, \ 1314 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX, \ 1315 WLAN_CFG_IPA_TX_ALT_RING_SIZE, \ 1316 CFG_VALUE_OR_DEFAULT, \ 1317 "DP IPA TX Alternative Ring Size") 1318 1319 /* 1320 * <ini> 1321 * dp_ipa_tx_alt_comp_ring_size - Set tx alt comp ring size for IPA 1322 * @Min: 1024 1323 * @Max: 8096 1324 * @Default: 1024 1325 * 1326 * This ini sets the tx alt comp ring size for IPA 1327 * 1328 * Related: N/A 1329 * 1330 * Supported Feature: IPA 1331 * 1332 * Usage: Internal 1333 * 1334 * </ini> 1335 */ 1336 #define CFG_DP_IPA_TX_ALT_COMP_RING_SIZE \ 1337 CFG_INI_UINT("dp_ipa_tx_alt_comp_ring_size", \ 1338 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN, \ 1339 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX, \ 1340 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE, \ 1341 CFG_VALUE_OR_DEFAULT, \ 1342 "DP IPA TX Alternative Completion Ring Size") 1343 1344 #define CFG_DP_IPA_TX_ALT_RING_CFG \ 1345 CFG(CFG_DP_IPA_TX_ALT_RING_SIZE) \ 1346 CFG(CFG_DP_IPA_TX_ALT_COMP_RING_SIZE) 1347 1348 #else 1349 #define CFG_DP_IPA_TX_ALT_RING_CFG 1350 #endif 1351 1352 #define CFG_DP_IPA_TX_RING_CFG \ 1353 CFG(CFG_DP_IPA_TX_RING_SIZE) \ 1354 CFG(CFG_DP_IPA_TX_COMP_RING_SIZE) 1355 #else 1356 #define CFG_DP_IPA_TX_RING_CFG 1357 #define CFG_DP_IPA_TX_ALT_RING_CFG 1358 #endif 1359 1360 #ifdef WLAN_SUPPORT_PPEDS 1361 #define CFG_DP_PPE_ENABLE \ 1362 CFG_INI_BOOL("ppe_enable", false, \ 1363 "DP ppe enable flag") 1364 1365 #define CFG_DP_REO2PPE_RING \ 1366 CFG_INI_UINT("dp_reo2ppe_ring", \ 1367 WLAN_CFG_REO2PPE_RING_SIZE_MIN, \ 1368 WLAN_CFG_REO2PPE_RING_SIZE_MAX, \ 1369 WLAN_CFG_REO2PPE_RING_SIZE, \ 1370 CFG_VALUE_OR_DEFAULT, "DP REO2PPE ring") 1371 1372 #define CFG_DP_PPE2TCL_RING \ 1373 CFG_INI_UINT("dp_ppe2tcl_ring", \ 1374 WLAN_CFG_PPE2TCL_RING_SIZE_MIN, \ 1375 WLAN_CFG_PPE2TCL_RING_SIZE_MAX, \ 1376 WLAN_CFG_PPE2TCL_RING_SIZE, \ 1377 CFG_VALUE_OR_DEFAULT, "DP PPE2TCL rings") 1378 1379 #define CFG_DP_PPE_RELEASE_RING \ 1380 CFG_INI_UINT("dp_ppe_release_ring", \ 1381 WLAN_CFG_PPE_RELEASE_RING_SIZE_MIN, \ 1382 WLAN_CFG_PPE_RELEASE_RING_SIZE_MAX, \ 1383 WLAN_CFG_PPE_RELEASE_RING_SIZE, \ 1384 CFG_VALUE_OR_DEFAULT, "DP PPE Release Ring") 1385 1386 #define CFG_DP_PPE_CONFIG \ 1387 CFG(CFG_DP_PPE_ENABLE) \ 1388 CFG(CFG_DP_REO2PPE_RING) \ 1389 CFG(CFG_DP_PPE2TCL_RING) \ 1390 CFG(CFG_DP_PPE_RELEASE_RING) 1391 #else 1392 #define CFG_DP_PPE_CONFIG 1393 #endif 1394 1395 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 1396 /* 1397 * <ini> 1398 * dp_chip0_rx_ring_map - Set Rx ring map for CHIP 0 1399 * @Min: 0x0 1400 * @Max: 0xFF 1401 * @Default: 0xF 1402 * 1403 * This ini sets Rx ring map for CHIP 0 1404 * 1405 * Usage: Internal 1406 * 1407 * </ini> 1408 */ 1409 #define CFG_DP_MLO_CHIP0_RX_RING_MAP \ 1410 CFG_INI_UINT("dp_chip0_rx_ring_map", \ 1411 WLAN_CFG_MLO_RX_RING_MAP_MIN, \ 1412 WLAN_CFG_MLO_RX_RING_MAP_MAX, \ 1413 WLAN_CFG_MLO_RX_RING_MAP, \ 1414 CFG_VALUE_OR_DEFAULT, "DP Rx ring map chip0") 1415 1416 /* 1417 * <ini> 1418 * dp_chip1_rx_ring_map - Set Rx ring map for CHIP 1 1419 * @Min: 0x0 1420 * @Max: 0xFF 1421 * @Default: 0xF 1422 * 1423 * This ini sets Rx ring map for CHIP 1 1424 * 1425 * Usage: Internal 1426 * 1427 * </ini> 1428 */ 1429 #define CFG_DP_MLO_CHIP1_RX_RING_MAP \ 1430 CFG_INI_UINT("dp_chip1_rx_ring_map", \ 1431 WLAN_CFG_MLO_RX_RING_MAP_MIN, \ 1432 WLAN_CFG_MLO_RX_RING_MAP_MAX, \ 1433 WLAN_CFG_MLO_RX_RING_MAP, \ 1434 CFG_VALUE_OR_DEFAULT, "DP Rx ring map chip1") 1435 1436 /* 1437 * <ini> 1438 * dp_chip2_rx_ring_map - Set Rx ring map for CHIP 2 1439 * @Min: 0x0 1440 * @Max: 0xFF 1441 * @Default: 0xF 1442 * 1443 * This ini sets Rx ring map for CHIP 2 1444 * 1445 * Usage: Internal 1446 * 1447 * </ini> 1448 */ 1449 #define CFG_DP_MLO_CHIP2_RX_RING_MAP \ 1450 CFG_INI_UINT("dp_chip2_rx_ring_map", \ 1451 WLAN_CFG_MLO_RX_RING_MAP_MIN, \ 1452 WLAN_CFG_MLO_RX_RING_MAP_MAX, \ 1453 WLAN_CFG_MLO_RX_RING_MAP, \ 1454 CFG_VALUE_OR_DEFAULT, "DP Rx ring map chip2") 1455 1456 #define CFG_DP_MLO_CONFIG \ 1457 CFG(CFG_DP_MLO_CHIP0_RX_RING_MAP) \ 1458 CFG(CFG_DP_MLO_CHIP1_RX_RING_MAP) \ 1459 CFG(CFG_DP_MLO_CHIP2_RX_RING_MAP) 1460 #else 1461 #define CFG_DP_MLO_CONFIG 1462 #endif 1463 1464 #define CFG_DP \ 1465 CFG(CFG_DP_HTT_PACKET_TYPE) \ 1466 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \ 1467 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \ 1468 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \ 1469 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \ 1470 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \ 1471 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \ 1472 CFG(CFG_DP_MAX_ALLOC_SIZE) \ 1473 CFG(CFG_DP_MAX_CLIENTS) \ 1474 CFG(CFG_DP_MAX_PEER_ID) \ 1475 CFG(CFG_DP_REO_DEST_RINGS) \ 1476 CFG(CFG_DP_TCL_DATA_RINGS) \ 1477 CFG(CFG_DP_NSS_REO_DEST_RINGS) \ 1478 CFG(CFG_DP_NSS_TCL_DATA_RINGS) \ 1479 CFG(CFG_DP_TX_DESC) \ 1480 CFG(CFG_DP_TX_EXT_DESC) \ 1481 CFG(CFG_DP_TX_EXT_DESC_POOLS) \ 1482 CFG(CFG_DP_PDEV_RX_RING) \ 1483 CFG(CFG_DP_PDEV_TX_RING) \ 1484 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \ 1485 CFG(CFG_DP_TX_COMPL_RING_SIZE) \ 1486 CFG(CFG_DP_TX_RING_SIZE) \ 1487 CFG(CFG_DP_NSS_COMP_RING_SIZE) \ 1488 CFG(CFG_DP_PDEV_LMAC_RING) \ 1489 CFG(CFG_DP_BASE_HW_MAC_ID) \ 1490 CFG(CFG_DP_RX_HASH) \ 1491 CFG(CFG_DP_TSO) \ 1492 CFG(CFG_DP_LRO) \ 1493 CFG(CFG_DP_SG) \ 1494 CFG(CFG_DP_GRO) \ 1495 CFG(CFG_DP_OL_TX_CSUM) \ 1496 CFG(CFG_DP_OL_RX_CSUM) \ 1497 CFG(CFG_DP_RAWMODE) \ 1498 CFG(CFG_DP_PEER_FLOW_CTRL) \ 1499 CFG(CFG_DP_NAPI) \ 1500 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \ 1501 CFG(CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD) \ 1502 CFG(CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD) \ 1503 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \ 1504 CFG(CFG_DP_WBM_RELEASE_RING) \ 1505 CFG(CFG_DP_TCL_CMD_CREDIT_RING) \ 1506 CFG(CFG_DP_TCL_STATUS_RING) \ 1507 CFG(CFG_DP_REO_REINJECT_RING) \ 1508 CFG(CFG_DP_RX_RELEASE_RING) \ 1509 CFG(CFG_DP_REO_EXCEPTION_RING) \ 1510 CFG(CFG_DP_RX_DESTINATION_RING) \ 1511 CFG(CFG_DP_REO_CMD_RING) \ 1512 CFG(CFG_DP_REO_STATUS_RING) \ 1513 CFG(CFG_DP_RXDMA_BUF_RING) \ 1514 CFG(CFG_DP_RXDMA_REFILL_RING) \ 1515 CFG(CFG_DP_TX_DESC_LIMIT_0) \ 1516 CFG(CFG_DP_TX_DESC_LIMIT_1) \ 1517 CFG(CFG_DP_TX_DESC_LIMIT_2) \ 1518 CFG(CFG_DP_TX_DEVICE_LIMIT) \ 1519 CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \ 1520 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \ 1521 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \ 1522 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \ 1523 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \ 1524 CFG(CFG_DP_RXDMA_ERR_DST_RING) \ 1525 CFG(CFG_DP_PER_PKT_LOGGING) \ 1526 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \ 1527 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \ 1528 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \ 1529 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \ 1530 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \ 1531 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \ 1532 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) \ 1533 CFG(CFG_DP_RX_SW_DESC_WEIGHT) \ 1534 CFG(CFG_DP_RX_SW_DESC_NUM) \ 1535 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE) \ 1536 CFG(CFG_DP_RX_FLOW_TAG_ENABLE) \ 1537 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV) \ 1538 CFG(CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE) \ 1539 CFG(CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD) \ 1540 CFG(CFG_DP_PKTLOG_BUFFER_SIZE) \ 1541 CFG(CFG_DP_RX_FISA_ENABLE) \ 1542 CFG(CFG_DP_FULL_MON_MODE) \ 1543 CFG(CFG_DP_REO_RINGS_MAP) \ 1544 CFG(CFG_DP_PEER_EXT_STATS) \ 1545 CFG(CFG_DP_RX_BUFF_POOL_ENABLE) \ 1546 CFG(CFG_DP_RX_REFILL_BUFF_POOL_ENABLE) \ 1547 CFG(CFG_DP_RX_PENDING_HL_THRESHOLD) \ 1548 CFG(CFG_DP_RX_PENDING_LO_THRESHOLD) \ 1549 CFG(CFG_DP_LEGACY_MODE_CSUM_DISABLE) \ 1550 CFG(CFG_DP_POLL_MODE_ENABLE) \ 1551 CFG(CFG_DP_SWLM_ENABLE) \ 1552 CFG(CFG_DP_TX_PER_PKT_VDEV_ID_CHECK) \ 1553 CFG(CFG_DP_RX_FST_IN_CMEM) \ 1554 CFG(CFG_DP_RX_RADIO_0_DEFAULT_REO) \ 1555 CFG(CFG_DP_RX_RADIO_1_DEFAULT_REO) \ 1556 CFG(CFG_DP_RX_RADIO_2_DEFAULT_REO) \ 1557 CFG(CFG_DP_WOW_CHECK_RX_PENDING) \ 1558 CFG(CFG_DP_HW_CC_ENABLE) \ 1559 CFG(CFG_DP_DELAY_MON_REPLENISH) \ 1560 CFG(CFG_DP_TX_MONITOR_BUF_RING) \ 1561 CFG(CFG_DP_TX_MONITOR_DST_RING) \ 1562 CFG_DP_IPA_TX_RING_CFG \ 1563 CFG_DP_PPE_CONFIG \ 1564 CFG_DP_IPA_TX_ALT_RING_CFG \ 1565 CFG_DP_MLO_CONFIG \ 1566 CFG_DP_VDEV_STATS_HW_OFFLOAD 1567 #endif /* _CFG_DP_H_ */ 1568