1 /* 2 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /** 20 * DOC: This file contains definitions of Data Path configuration. 21 */ 22 23 #ifndef _CFG_DP_H_ 24 #define _CFG_DP_H_ 25 26 #include "cfg_define.h" 27 28 #define WLAN_CFG_MAX_CLIENTS 64 29 #define WLAN_CFG_MAX_CLIENTS_MIN 8 30 #define WLAN_CFG_MAX_CLIENTS_MAX 64 31 32 /* Change this to a lower value to enforce scattered idle list mode */ 33 #define WLAN_CFG_MAX_ALLOC_SIZE 0x200000 34 #define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000 35 #define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000 36 37 #if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \ 38 defined(QCA_LL_PDEV_TX_FLOW_CONTROL) 39 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10 40 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15 41 #else 42 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 43 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 44 #endif 45 46 #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0 47 #define WLAN_CFG_PER_PDEV_TX_RING_MAX 1 48 49 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 50 #define WLAN_CFG_PER_PDEV_RX_RING 0 51 #define WLAN_CFG_PER_PDEV_LMAC_RING 0 52 #define WLAN_LRO_ENABLE 0 53 #ifdef QCA_WIFI_QCA6750 54 #define WLAN_CFG_MAC_PER_TARGET 1 55 #else 56 #define WLAN_CFG_MAC_PER_TARGET 2 57 #endif 58 #ifdef IPA_OFFLOAD 59 /* Size of TCL TX Ring */ 60 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 61 #define WLAN_CFG_TX_RING_SIZE 2048 62 #else 63 #define WLAN_CFG_TX_RING_SIZE 1024 64 #endif 65 66 #define WLAN_CFG_IPA_TX_RING_SIZE 1024 67 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE 1024 68 69 #define WLAN_CFG_PER_PDEV_TX_RING 0 70 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048 71 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000 72 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024 73 #else 74 #define WLAN_CFG_TX_RING_SIZE 512 75 #define WLAN_CFG_PER_PDEV_TX_RING 1 76 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 77 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 78 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 79 #endif 80 81 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 82 #define WLAN_CFG_TX_COMP_RING_SIZE 4096 83 84 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 85 #define WLAN_CFG_NUM_TX_DESC 4096 86 #define WLAN_CFG_NUM_TX_EXT_DESC 4096 87 #else 88 #define WLAN_CFG_TX_COMP_RING_SIZE 1024 89 90 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 91 #define WLAN_CFG_NUM_TX_DESC 1024 92 #define WLAN_CFG_NUM_TX_EXT_DESC 1024 93 #endif 94 95 /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 96 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1 97 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 98 99 /* Interrupt Mitigation - Timer threshold in us */ 100 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8 101 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8 102 103 #ifdef WLAN_DP_PER_RING_TYPE_CONFIG 104 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX \ 105 WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 106 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX \ 107 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 108 #else 109 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1 110 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8 111 #endif 112 #endif 113 114 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD 0x60000 115 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN 0 116 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX 0x80000 117 118 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD 0x60000 119 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN 100 120 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX 0x80000 121 122 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256 123 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 512 124 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 0 125 126 #define WLAN_CFG_PER_PDEV_RX_RING_MIN 0 127 #define WLAN_CFG_PER_PDEV_RX_RING_MAX 0 128 129 #define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0 130 #define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1 131 132 #define WLAN_CFG_TX_RING_SIZE_MIN 512 133 #define WLAN_CFG_TX_RING_SIZE_MAX 0x80000 134 135 #define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512 136 #define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000 137 138 #define WLAN_CFG_NUM_TX_DESC_MIN 16 139 #define WLAN_CFG_NUM_TX_DESC_MAX 32768 140 141 #define WLAN_CFG_NUM_TX_EXT_DESC_MIN 16 142 #define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000 143 144 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1 145 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256 146 147 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 0 148 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128 149 150 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1 151 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128 152 153 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1 154 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128 155 156 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1 157 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1 158 159 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8 160 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 1000 161 162 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8 163 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500 164 165 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8 166 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000 167 168 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8 169 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 512 170 171 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8 172 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500 173 174 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000 175 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000 176 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000 177 178 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 179 180 /* Per vdev pools */ 181 #define WLAN_CFG_NUM_TX_DESC_POOL 3 182 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 183 184 #else /* QCA_LL_TX_FLOW_CONTROL_V2 */ 185 186 #ifdef TX_PER_PDEV_DESC_POOL 187 #define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT 188 #define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT 189 190 #else /* TX_PER_PDEV_DESC_POOL */ 191 192 #define WLAN_CFG_NUM_TX_DESC_POOL 3 193 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 194 195 #endif /* TX_PER_PDEV_DESC_POOL */ 196 #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */ 197 198 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1 199 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4 200 201 #define WLAN_CFG_HTT_PKT_TYPE 2 202 #define WLAN_CFG_HTT_PKT_TYPE_MIN 2 203 #define WLAN_CFG_HTT_PKT_TYPE_MAX 2 204 205 #define WLAN_CFG_MAX_PEER_ID 64 206 #define WLAN_CFG_MAX_PEER_ID_MIN 64 207 #define WLAN_CFG_MAX_PEER_ID_MAX 64 208 209 #define WLAN_CFG_RX_DEFRAG_TIMEOUT 100 210 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100 211 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100 212 213 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 214 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3 215 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3 216 217 #define WLAN_CFG_NUM_REO_DEST_RING 4 218 #define WLAN_CFG_NUM_REO_DEST_RING_MIN 4 219 #define WLAN_CFG_NUM_REO_DEST_RING_MAX 4 220 221 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS 2 222 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN 1 223 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX 3 224 225 #define WLAN_CFG_NSS_NUM_REO_DEST_RING 2 226 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN 1 227 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX 3 228 229 #define WLAN_CFG_WBM_RELEASE_RING_SIZE 1024 230 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64 231 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 1024 232 233 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE 32 234 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN 32 235 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX 32 236 237 #define WLAN_CFG_TCL_STATUS_RING_SIZE 32 238 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32 239 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32 240 241 #if defined(QCA_WIFI_QCA6290) 242 #define WLAN_CFG_REO_DST_RING_SIZE 1024 243 #else 244 #define WLAN_CFG_REO_DST_RING_SIZE 2048 245 #endif 246 247 #define WLAN_CFG_REO_DST_RING_SIZE_MIN 1024 248 #define WLAN_CFG_REO_DST_RING_SIZE_MAX 2048 249 250 #define WLAN_CFG_REO_REINJECT_RING_SIZE 128 251 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32 252 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 128 253 254 #define WLAN_CFG_RX_RELEASE_RING_SIZE 1024 255 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8 256 #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 257 defined(QCA_WIFI_QCA6750) 258 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024 259 #else 260 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 8192 261 #endif 262 263 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE 256 264 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128 265 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 512 266 267 #define WLAN_CFG_REO_CMD_RING_SIZE 128 268 #define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64 269 #define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128 270 271 #define WLAN_CFG_REO_STATUS_RING_SIZE 256 272 #define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128 273 #define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048 274 275 #define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024 276 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024 277 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 1024 278 279 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096 280 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16 281 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 4096 282 283 #define WLAN_CFG_TX_DESC_LIMIT_0 0 284 #define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096 285 #define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768 286 287 #define WLAN_CFG_TX_DESC_LIMIT_1 0 288 #define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096 289 #define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768 290 291 #define WLAN_CFG_TX_DESC_LIMIT_2 0 292 #define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096 293 #define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768 294 295 #define WLAN_CFG_TX_DEVICE_LIMIT 65536 296 #define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384 297 #define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536 298 299 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024 300 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128 301 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024 302 303 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096 304 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16 305 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192 306 307 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048 308 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48 309 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192 310 311 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024 312 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16 313 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192 314 315 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096 316 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096 317 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384 318 319 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024 320 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024 321 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192 322 323 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE 32 324 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN 0 325 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX 256 326 327 /** 328 * Allocate as many RX descriptors as buffers in the SW2RXDMA 329 * ring. This value may need to be tuned later. 330 */ 331 #if defined(QCA_HOST2FW_RXBUF_RING) 332 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 333 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 334 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 1 335 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 336 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 4096 337 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 4096 338 339 /** 340 * For low memory AP cases using 1 will reduce the rx descriptors memory req 341 */ 342 #elif defined(QCA_LOWMEM_CONFIG) || defined(QCA_512M_CONFIG) 343 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 344 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 345 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 346 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 347 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 348 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 12288 349 350 /** 351 * AP use cases need to allocate more RX Descriptors than the number of 352 * entries avaialable in the SW2RXDMA buffer replenish ring. This is to account 353 * for frames sitting in REO queues, HW-HW DMA rings etc. Hence using a 354 * multiplication factor of 3, to allocate three times as many RX descriptors 355 * as RX buffers. 356 */ 357 #else 358 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 3 359 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 360 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 361 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 12288 362 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 4096 363 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 12288 364 #endif //QCA_HOST2FW_RXBUF_RING 365 366 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE 16384 367 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN 1 368 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX 16384 369 370 #define WLAN_CFG_PKTLOG_BUFFER_SIZE 10 371 #define WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE 1 372 #define WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE 10 373 374 #define WLAN_CFG_NUM_REO_RINGS_MAP 0xF 375 #define WLAN_CFG_NUM_REO_RINGS_MAP_MIN 0x1 376 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xF 377 378 #define WLAN_CFG_RADIO_0_DEFAULT_REO 0x1 379 #define WLAN_CFG_RADIO_1_DEFAULT_REO 0x2 380 #define WLAN_CFG_RADIO_2_DEFAULT_REO 0x3 381 382 #define WLAN_CFG_RADIO_DEFAULT_REO_MIN 0x1 383 #define WLAN_CFG_RADIO_DEFAULT_REO_MAX 0x4 384 385 /* DP INI Declerations */ 386 #define CFG_DP_HTT_PACKET_TYPE \ 387 CFG_INI_UINT("dp_htt_packet_type", \ 388 WLAN_CFG_HTT_PKT_TYPE_MIN, \ 389 WLAN_CFG_HTT_PKT_TYPE_MAX, \ 390 WLAN_CFG_HTT_PKT_TYPE, \ 391 CFG_VALUE_OR_DEFAULT, "DP HTT packet type") 392 393 #define CFG_DP_INT_BATCH_THRESHOLD_OTHER \ 394 CFG_INI_UINT("dp_int_batch_threshold_other", \ 395 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \ 396 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \ 397 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \ 398 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other") 399 400 #define CFG_DP_INT_BATCH_THRESHOLD_RX \ 401 CFG_INI_UINT("dp_int_batch_threshold_rx", \ 402 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \ 403 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \ 404 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \ 405 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx") 406 407 #define CFG_DP_INT_BATCH_THRESHOLD_TX \ 408 CFG_INI_UINT("dp_int_batch_threshold_tx", \ 409 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \ 410 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \ 411 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \ 412 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx") 413 414 #define CFG_DP_INT_TIMER_THRESHOLD_OTHER \ 415 CFG_INI_UINT("dp_int_timer_threshold_other", \ 416 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \ 417 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \ 418 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \ 419 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other") 420 421 #define CFG_DP_INT_TIMER_THRESHOLD_RX \ 422 CFG_INI_UINT("dp_int_timer_threshold_rx", \ 423 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \ 424 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \ 425 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \ 426 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx") 427 428 #define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \ 429 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \ 430 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \ 431 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \ 432 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \ 433 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring") 434 435 #define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \ 436 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \ 437 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \ 438 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \ 439 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \ 440 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring") 441 442 #define CFG_DP_INT_TIMER_THRESHOLD_TX \ 443 CFG_INI_UINT("dp_int_timer_threshold_tx", \ 444 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \ 445 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \ 446 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \ 447 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx") 448 449 #define CFG_DP_MAX_ALLOC_SIZE \ 450 CFG_INI_UINT("dp_max_alloc_size", \ 451 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \ 452 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \ 453 WLAN_CFG_MAX_ALLOC_SIZE, \ 454 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size") 455 456 #define CFG_DP_MAX_CLIENTS \ 457 CFG_INI_UINT("dp_max_clients", \ 458 WLAN_CFG_MAX_CLIENTS_MIN, \ 459 WLAN_CFG_MAX_CLIENTS_MAX, \ 460 WLAN_CFG_MAX_CLIENTS, \ 461 CFG_VALUE_OR_DEFAULT, "DP Max Clients") 462 463 #define CFG_DP_MAX_PEER_ID \ 464 CFG_INI_UINT("dp_max_peer_id", \ 465 WLAN_CFG_MAX_PEER_ID_MIN, \ 466 WLAN_CFG_MAX_PEER_ID_MAX, \ 467 WLAN_CFG_MAX_PEER_ID, \ 468 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID") 469 470 #define CFG_DP_REO_DEST_RINGS \ 471 CFG_INI_UINT("dp_reo_dest_rings", \ 472 WLAN_CFG_NUM_REO_DEST_RING_MIN, \ 473 WLAN_CFG_NUM_REO_DEST_RING_MAX, \ 474 WLAN_CFG_NUM_REO_DEST_RING, \ 475 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings") 476 477 #define CFG_DP_TCL_DATA_RINGS \ 478 CFG_INI_UINT("dp_tcl_data_rings", \ 479 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \ 480 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \ 481 WLAN_CFG_NUM_TCL_DATA_RINGS, \ 482 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings") 483 484 #define CFG_DP_NSS_REO_DEST_RINGS \ 485 CFG_INI_UINT("dp_nss_reo_dest_rings", \ 486 WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN, \ 487 WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX, \ 488 WLAN_CFG_NSS_NUM_REO_DEST_RING, \ 489 CFG_VALUE_OR_DEFAULT, "DP NSS REO Destination Rings") 490 491 #define CFG_DP_NSS_TCL_DATA_RINGS \ 492 CFG_INI_UINT("dp_nss_tcl_data_rings", \ 493 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN, \ 494 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX, \ 495 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS, \ 496 CFG_VALUE_OR_DEFAULT, "DP NSS TCL Data Rings") 497 498 #define CFG_DP_TX_DESC \ 499 CFG_INI_UINT("dp_tx_desc", \ 500 WLAN_CFG_NUM_TX_DESC_MIN, \ 501 WLAN_CFG_NUM_TX_DESC_MAX, \ 502 WLAN_CFG_NUM_TX_DESC, \ 503 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors") 504 505 #define CFG_DP_TX_EXT_DESC \ 506 CFG_INI_UINT("dp_tx_ext_desc", \ 507 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \ 508 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \ 509 WLAN_CFG_NUM_TX_EXT_DESC, \ 510 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors") 511 512 #define CFG_DP_TX_EXT_DESC_POOLS \ 513 CFG_INI_UINT("dp_tx_ext_desc_pool", \ 514 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \ 515 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \ 516 WLAN_CFG_NUM_TXEXT_DESC_POOL, \ 517 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool") 518 519 #define CFG_DP_PDEV_RX_RING \ 520 CFG_INI_UINT("dp_pdev_rx_ring", \ 521 WLAN_CFG_PER_PDEV_RX_RING_MIN, \ 522 WLAN_CFG_PER_PDEV_RX_RING_MAX, \ 523 WLAN_CFG_PER_PDEV_RX_RING, \ 524 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring") 525 526 #define CFG_DP_PDEV_TX_RING \ 527 CFG_INI_UINT("dp_pdev_tx_ring", \ 528 WLAN_CFG_PER_PDEV_TX_RING_MIN, \ 529 WLAN_CFG_PER_PDEV_TX_RING_MAX, \ 530 WLAN_CFG_PER_PDEV_TX_RING, \ 531 CFG_VALUE_OR_DEFAULT, \ 532 "DP PDEV Tx Ring") 533 534 #define CFG_DP_RX_DEFRAG_TIMEOUT \ 535 CFG_INI_UINT("dp_rx_defrag_timeout", \ 536 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \ 537 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \ 538 WLAN_CFG_RX_DEFRAG_TIMEOUT, \ 539 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout") 540 541 #define CFG_DP_TX_COMPL_RING_SIZE \ 542 CFG_INI_UINT("dp_tx_compl_ring_size", \ 543 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \ 544 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \ 545 WLAN_CFG_TX_COMP_RING_SIZE, \ 546 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size") 547 548 #define CFG_DP_TX_RING_SIZE \ 549 CFG_INI_UINT("dp_tx_ring_size", \ 550 WLAN_CFG_TX_RING_SIZE_MIN,\ 551 WLAN_CFG_TX_RING_SIZE_MAX,\ 552 WLAN_CFG_TX_RING_SIZE,\ 553 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size") 554 555 #define CFG_DP_NSS_COMP_RING_SIZE \ 556 CFG_INI_UINT("dp_nss_comp_ring_size", \ 557 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \ 558 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \ 559 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \ 560 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size") 561 562 #define CFG_DP_PDEV_LMAC_RING \ 563 CFG_INI_UINT("dp_pdev_lmac_ring", \ 564 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \ 565 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \ 566 WLAN_CFG_PER_PDEV_LMAC_RING, \ 567 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring") 568 /* 569 * <ini> 570 * dp_rx_pending_hl_threshold - High threshold of frame number to start 571 * frame dropping scheme 572 * @Min: 0 573 * @Max: 524288 574 * @Default: 393216 575 * 576 * This ini entry is used to set a high limit threshold to start frame 577 * dropping scheme 578 * 579 * Usage: External 580 * 581 * </ini> 582 */ 583 #define CFG_DP_RX_PENDING_HL_THRESHOLD \ 584 CFG_INI_UINT("dp_rx_pending_hl_threshold", \ 585 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN, \ 586 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX, \ 587 WLAN_CFG_RX_PENDING_HL_THRESHOLD, \ 588 CFG_VALUE_OR_DEFAULT, "DP rx pending hl threshold") 589 590 /* 591 * <ini> 592 * dp_rx_pending_lo_threshold - Low threshold of frame number to stop 593 * frame dropping scheme 594 * @Min: 100 595 * @Max: 524288 596 * @Default: 393216 597 * 598 * This ini entry is used to set a low limit threshold to stop frame 599 * dropping scheme 600 * 601 * Usage: External 602 * 603 * </ini> 604 */ 605 #define CFG_DP_RX_PENDING_LO_THRESHOLD \ 606 CFG_INI_UINT("dp_rx_pending_lo_threshold", \ 607 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN, \ 608 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX, \ 609 WLAN_CFG_RX_PENDING_LO_THRESHOLD, \ 610 CFG_VALUE_OR_DEFAULT, "DP rx pending lo threshold") 611 612 #define CFG_DP_BASE_HW_MAC_ID \ 613 CFG_INI_UINT("dp_base_hw_macid", \ 614 0, 1, 1, \ 615 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID") 616 617 #define CFG_DP_RX_HASH \ 618 CFG_INI_BOOL("dp_rx_hash", true, \ 619 "DP Rx Hash") 620 621 #define CFG_DP_TSO \ 622 CFG_INI_BOOL("TSOEnable", false, \ 623 "DP TSO Enabled") 624 625 #define CFG_DP_LRO \ 626 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \ 627 "DP LRO Enable") 628 629 /* 630 * <ini> 631 * CFG_DP_SG - Enable the SG feature standalonely 632 * @Min: 0 633 * @Max: 1 634 * @Default: 1 635 * 636 * This ini entry is used to enable/disable SG feature standalonely. 637 * Also does Rome support SG on TX, lithium does not. 638 * For example the lithium does not support SG on UDP frames. 639 * Which is able to handle SG only for TSO frames(in case TSO is enabled). 640 * 641 * Usage: External 642 * 643 * </ini> 644 */ 645 #define CFG_DP_SG \ 646 CFG_INI_BOOL("dp_sg_support", false, \ 647 "DP SG Enable") 648 649 #define CFG_DP_GRO \ 650 CFG_INI_BOOL("GROEnable", false, \ 651 "DP GRO Enable") 652 653 #define CFG_DP_OL_TX_CSUM \ 654 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \ 655 "DP tx csum Enable") 656 657 #define CFG_DP_OL_RX_CSUM \ 658 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \ 659 "DP rx csum Enable") 660 661 #define CFG_DP_RAWMODE \ 662 CFG_INI_BOOL("dp_rawmode_support", false, \ 663 "DP rawmode Enable") 664 665 #define CFG_DP_PEER_FLOW_CTRL \ 666 CFG_INI_BOOL("dp_peer_flow_control_support", false, \ 667 "DP peer flow ctrl Enable") 668 669 #define CFG_DP_NAPI \ 670 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \ 671 "DP Napi Enabled") 672 /* 673 * <ini> 674 * gEnableP2pIpTcpUdpChecksumOffload - Enable checksum offload for P2P mode 675 * @Min: 0 676 * @Max: 1 677 * @Default: 1 678 * 679 * This ini entry is used to enable/disable TX checksum(UDP/TCP) for P2P modes. 680 * This includes P2P device mode, P2P client mode and P2P GO mode. 681 * The feature is enabled by default. To disable TX checksum for P2P, add the 682 * following entry in ini file: 683 * gEnableP2pIpTcpUdpChecksumOffload=0 684 * 685 * Usage: External 686 * 687 * </ini> 688 */ 689 #define CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD \ 690 CFG_INI_BOOL("gEnableP2pIpTcpUdpChecksumOffload", true, \ 691 "DP TCP UDP Checksum Offload for P2P mode (device/cli/go)") 692 693 /* 694 * <ini> 695 * gEnableNanIpTcpUdpChecksumOffload - Enable checksum offload for NAN mode 696 * @Min: 0 697 * @Max: 1 698 * @Default: 1 699 * 700 * Usage: External 701 * 702 * </ini> 703 */ 704 #define CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD \ 705 CFG_INI_BOOL("gEnableNanIpTcpUdpChecksumOffload", true, \ 706 "DP TCP UDP Checksum Offload for NAN mode") 707 708 /* 709 * <ini> 710 * gEnableIpTcpUdpChecksumOffload - Enable checksum offload 711 * @Min: 0 712 * @Max: 1 713 * @Default: 1 714 * 715 * Usage: External 716 * 717 * </ini> 718 */ 719 #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \ 720 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \ 721 "DP TCP UDP Checksum Offload") 722 723 #define CFG_DP_DEFRAG_TIMEOUT_CHECK \ 724 CFG_INI_BOOL("dp_defrag_timeout_check", true, \ 725 "DP Defrag Timeout Check") 726 727 #define CFG_DP_WBM_RELEASE_RING \ 728 CFG_INI_UINT("dp_wbm_release_ring", \ 729 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \ 730 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \ 731 WLAN_CFG_WBM_RELEASE_RING_SIZE, \ 732 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring") 733 734 #define CFG_DP_TCL_CMD_CREDIT_RING \ 735 CFG_INI_UINT("dp_tcl_cmd_credit_ring", \ 736 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN, \ 737 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX, \ 738 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE, \ 739 CFG_VALUE_OR_DEFAULT, "DP TCL Cmd_Credit ring") 740 741 #define CFG_DP_TCL_STATUS_RING \ 742 CFG_INI_UINT("dp_tcl_status_ring",\ 743 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \ 744 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \ 745 WLAN_CFG_TCL_STATUS_RING_SIZE, \ 746 CFG_VALUE_OR_DEFAULT, "DP TCL status ring") 747 748 #define CFG_DP_REO_REINJECT_RING \ 749 CFG_INI_UINT("dp_reo_reinject_ring", \ 750 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \ 751 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \ 752 WLAN_CFG_REO_REINJECT_RING_SIZE, \ 753 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring") 754 755 #define CFG_DP_RX_RELEASE_RING \ 756 CFG_INI_UINT("dp_rx_release_ring", \ 757 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \ 758 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \ 759 WLAN_CFG_RX_RELEASE_RING_SIZE, \ 760 CFG_VALUE_OR_DEFAULT, "DP Rx release ring") 761 762 #define CFG_DP_REO_EXCEPTION_RING \ 763 CFG_INI_UINT("dp_reo_exception_ring", \ 764 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \ 765 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \ 766 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \ 767 CFG_VALUE_OR_DEFAULT, "DP REO exception ring") 768 769 #define CFG_DP_REO_CMD_RING \ 770 CFG_INI_UINT("dp_reo_cmd_ring", \ 771 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \ 772 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \ 773 WLAN_CFG_REO_CMD_RING_SIZE, \ 774 CFG_VALUE_OR_DEFAULT, "DP REO command ring") 775 776 #define CFG_DP_REO_STATUS_RING \ 777 CFG_INI_UINT("dp_reo_status_ring", \ 778 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \ 779 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \ 780 WLAN_CFG_REO_STATUS_RING_SIZE, \ 781 CFG_VALUE_OR_DEFAULT, "DP REO status ring") 782 783 #define CFG_DP_RXDMA_BUF_RING \ 784 CFG_INI_UINT("dp_rxdma_buf_ring", \ 785 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \ 786 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \ 787 WLAN_CFG_RXDMA_BUF_RING_SIZE, \ 788 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring") 789 790 #define CFG_DP_RXDMA_REFILL_RING \ 791 CFG_INI_UINT("dp_rxdma_refill_ring", \ 792 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \ 793 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \ 794 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \ 795 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring") 796 797 #define CFG_DP_TX_DESC_LIMIT_0 \ 798 CFG_INI_UINT("dp_tx_desc_limit_0", \ 799 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \ 800 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \ 801 WLAN_CFG_TX_DESC_LIMIT_0, \ 802 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0") 803 804 #define CFG_DP_TX_DESC_LIMIT_1 \ 805 CFG_INI_UINT("dp_tx_desc_limit_1", \ 806 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \ 807 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \ 808 WLAN_CFG_TX_DESC_LIMIT_1, \ 809 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1") 810 811 #define CFG_DP_TX_DESC_LIMIT_2 \ 812 CFG_INI_UINT("dp_tx_desc_limit_2", \ 813 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \ 814 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \ 815 WLAN_CFG_TX_DESC_LIMIT_2, \ 816 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2") 817 818 #define CFG_DP_TX_DEVICE_LIMIT \ 819 CFG_INI_UINT("dp_tx_device_limit", \ 820 WLAN_CFG_TX_DEVICE_LIMIT_MIN, \ 821 WLAN_CFG_TX_DEVICE_LIMIT_MAX, \ 822 WLAN_CFG_TX_DEVICE_LIMIT, \ 823 CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit") 824 825 #define CFG_DP_TX_SW_INTERNODE_QUEUE \ 826 CFG_INI_UINT("dp_tx_sw_internode_queue", \ 827 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \ 828 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \ 829 WLAN_CFG_TX_SW_INTERNODE_QUEUE, \ 830 CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue") 831 832 #define CFG_DP_RXDMA_MONITOR_BUF_RING \ 833 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \ 834 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \ 835 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \ 836 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \ 837 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring") 838 839 #define CFG_DP_RXDMA_MONITOR_DST_RING \ 840 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \ 841 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \ 842 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \ 843 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \ 844 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 845 846 #define CFG_DP_RXDMA_MONITOR_STATUS_RING \ 847 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \ 848 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \ 849 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \ 850 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \ 851 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring") 852 853 #define CFG_DP_RXDMA_MONITOR_DESC_RING \ 854 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \ 855 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \ 856 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \ 857 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \ 858 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 859 860 #define CFG_DP_RXDMA_ERR_DST_RING \ 861 CFG_INI_UINT("dp_rxdma_err_dst_ring", \ 862 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \ 863 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \ 864 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \ 865 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring") 866 867 #define CFG_DP_PER_PKT_LOGGING \ 868 CFG_INI_UINT("enable_verbose_debug", \ 869 0, 0xffff, 0, \ 870 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging") 871 872 #define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \ 873 CFG_INI_UINT("TxFlowStartQueueOffset", \ 874 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \ 875 CFG_VALUE_OR_DEFAULT, "Start queue offset") 876 877 #define CFG_DP_TX_FLOW_STOP_QUEUE_TH \ 878 CFG_INI_UINT("TxFlowStopQueueThreshold", \ 879 0, 50, 15, \ 880 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold") 881 882 #define CFG_DP_IPA_UC_TX_BUF_SIZE \ 883 CFG_INI_UINT("IpaUcTxBufSize", \ 884 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \ 885 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size") 886 887 #define CFG_DP_IPA_UC_TX_PARTITION_BASE \ 888 CFG_INI_UINT("IpaUcTxPartitionBase", \ 889 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \ 890 CFG_VALUE_OR_DEFAULT, "IPA tx partition base") 891 892 #define CFG_DP_IPA_UC_RX_IND_RING_COUNT \ 893 CFG_INI_UINT("IpaUcRxIndRingCount", \ 894 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \ 895 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count") 896 897 #define CFG_DP_REORDER_OFFLOAD_SUPPORT \ 898 CFG_INI_UINT("gReorderOffloadSupported", \ 899 0, 1, 1, \ 900 CFG_VALUE_OR_DEFAULT, "Packet reordering offload to firmware") 901 902 #define CFG_DP_AP_STA_SECURITY_SEPERATION \ 903 CFG_INI_BOOL("gDisableIntraBssFwd", \ 904 false, "Disable intrs BSS Rx packets") 905 906 #define CFG_DP_ENABLE_DATA_STALL_DETECTION \ 907 CFG_INI_BOOL("gEnableDataStallDetection", \ 908 true, "Enable/Disable Data stall detection") 909 910 #define CFG_DP_RX_SW_DESC_WEIGHT \ 911 CFG_INI_UINT("dp_rx_sw_desc_weight", \ 912 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN, \ 913 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX, \ 914 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE, \ 915 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC weight") 916 917 #define CFG_DP_RX_SW_DESC_NUM \ 918 CFG_INI_UINT("dp_rx_sw_desc_num", \ 919 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN, \ 920 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX, \ 921 WLAN_CFG_RX_SW_DESC_NUM_SIZE, \ 922 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC num") 923 924 #define CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE \ 925 CFG_INI_UINT("dp_rx_flow_search_table_size", \ 926 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN, \ 927 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX, \ 928 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE, \ 929 CFG_VALUE_OR_DEFAULT, \ 930 "DP Rx Flow Search Table Size in number of entries") 931 932 #define CFG_DP_RX_FLOW_TAG_ENABLE \ 933 CFG_INI_BOOL("dp_rx_flow_tag_enable", false, \ 934 "Enable/Disable DP Rx Flow Tag") 935 936 #define CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV \ 937 CFG_INI_BOOL("dp_rx_per_pdev_flow_search", false, \ 938 "DP Rx Flow Search Table Is Per PDev") 939 940 #define CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE \ 941 CFG_INI_BOOL("dp_rx_monitor_protocol_flow_tag_enable", true, \ 942 "Enable/Disable Rx Protocol & Flow tags in Monitor mode") 943 944 #define CFG_DP_TX_PER_PKT_VDEV_ID_CHECK \ 945 CFG_INI_BOOL("dp_tx_allow_per_pkt_vdev_id_check", false, \ 946 "Enable/Disable tx Per Pkt vdev id check") 947 948 /* 949 * <ini> 950 * dp_rx_fisa_enable - Control Rx datapath FISA 951 * @Min: 0 952 * @Max: 1 953 * @Default: 0 954 * 955 * This ini is used to enable DP Rx FISA feature 956 * 957 * Related: dp_rx_flow_search_table_size 958 * 959 * Supported Feature: STA,P2P and SAP IPA disabled terminating 960 * 961 * Usage: Internal/External 962 * 963 * </ini> 964 */ 965 #define CFG_DP_RX_FISA_ENABLE \ 966 CFG_INI_BOOL("dp_rx_fisa_enable", false, \ 967 "Enable/Disable DP Rx FISA") 968 969 #define CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD \ 970 CFG_INI_UINT("mon_drop_thresh", \ 971 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN, \ 972 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX, \ 973 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE, \ 974 CFG_VALUE_OR_DEFAULT, "RXDMA monitor rx drop theshold") 975 976 #define CFG_DP_PKTLOG_BUFFER_SIZE \ 977 CFG_INI_UINT("PktlogBufSize", \ 978 WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE, \ 979 WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE, \ 980 WLAN_CFG_PKTLOG_BUFFER_SIZE, \ 981 CFG_VALUE_OR_DEFAULT, "Packet Log buffer size") 982 983 #define CFG_DP_FULL_MON_MODE \ 984 CFG_INI_BOOL("full_mon_mode", \ 985 false, "Full Monitor mode support") 986 987 #define CFG_DP_REO_RINGS_MAP \ 988 CFG_INI_UINT("dp_reo_rings_map", \ 989 WLAN_CFG_NUM_REO_RINGS_MAP_MIN, \ 990 WLAN_CFG_NUM_REO_RINGS_MAP_MAX, \ 991 WLAN_CFG_NUM_REO_RINGS_MAP, \ 992 CFG_VALUE_OR_DEFAULT, "REO Destination Rings Mapping") 993 994 #define CFG_DP_RX_RADIO_0_DEFAULT_REO \ 995 CFG_INI_UINT("dp_rx_radio0_default_reo", \ 996 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 997 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 998 WLAN_CFG_RADIO_0_DEFAULT_REO, \ 999 CFG_VALUE_OR_DEFAULT, "Radio0 to REO destination default mapping") 1000 1001 #define CFG_DP_RX_RADIO_1_DEFAULT_REO \ 1002 CFG_INI_UINT("dp_rx_radio1_default_reo", \ 1003 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1004 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1005 WLAN_CFG_RADIO_1_DEFAULT_REO, \ 1006 CFG_VALUE_OR_DEFAULT, "Radio1 to REO destination default mapping") 1007 1008 #define CFG_DP_RX_RADIO_2_DEFAULT_REO \ 1009 CFG_INI_UINT("dp_rx_radio2_default_reo", \ 1010 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1011 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1012 WLAN_CFG_RADIO_2_DEFAULT_REO, \ 1013 CFG_VALUE_OR_DEFAULT, "Radio2 to REO destination default mapping") 1014 1015 #define CFG_DP_PEER_EXT_STATS \ 1016 CFG_INI_BOOL("peer_ext_stats", \ 1017 false, "Peer extended stats") 1018 /* 1019 * <ini> 1020 * legacy_mode_csum_disable - Disable csum offload for legacy 802.11abg modes 1021 * @Min: 0 1022 * @Max: 1 1023 * @Default: 0 1024 * 1025 * This ini is used to disable HW checksum offload capability for legacy 1026 * connections 1027 * 1028 * Related: gEnableIpTcpUdpChecksumOffload should be enabled 1029 * 1030 * Usage: Internal 1031 * 1032 * </ini> 1033 */ 1034 1035 #define CFG_DP_LEGACY_MODE_CSUM_DISABLE \ 1036 CFG_INI_BOOL("legacy_mode_csum_disable", false, \ 1037 "Enable/Disable legacy mode checksum") 1038 1039 #define CFG_DP_RX_BUFF_POOL_ENABLE \ 1040 CFG_INI_BOOL("dp_rx_buff_prealloc_pool", false, \ 1041 "Enable/Disable DP RX emergency buffer pool support") 1042 1043 #define CFG_DP_POLL_MODE_ENABLE \ 1044 CFG_INI_BOOL("dp_poll_mode_enable", false, \ 1045 "Enable/Disable Polling mode for data path") 1046 1047 #define CFG_DP_RX_FST_IN_CMEM \ 1048 CFG_INI_BOOL("dp_rx_fst_in_cmem", false, \ 1049 "Enable/Disable flow search table in CMEM") 1050 /* 1051 * <ini> 1052 * gEnableSWLM - Control DP Software latency manager 1053 * @Min: 0 1054 * @Max: 1 1055 * @Default: 0 1056 * 1057 * This ini is used to enable DP Software latency Manager 1058 * 1059 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1060 * 1061 * Usage: Internal 1062 * 1063 * </ini> 1064 */ 1065 #define CFG_DP_SWLM_ENABLE \ 1066 CFG_INI_BOOL("gEnableSWLM", false, \ 1067 "Enable/Disable DP SWLM") 1068 /* 1069 * <ini> 1070 * wow_check_rx_pending_enable - control to check RX frames pending in Wow 1071 * @Min: 0 1072 * @Max: 1 1073 * @Default: 0 1074 * 1075 * This ini is used to control DP Software to perform RX pending check 1076 * before entering WoW mode 1077 * 1078 * Usage: Internal 1079 * 1080 * </ini> 1081 */ 1082 #define CFG_DP_WOW_CHECK_RX_PENDING \ 1083 CFG_INI_BOOL("wow_check_rx_pending_enable", \ 1084 false, \ 1085 "enable rx frame pending check in WoW mode") 1086 1087 /* 1088 * <ini> 1089 * gForceRX64BA - enable force 64 blockack mode for RX 1090 * @Min: 0 1091 * @Max: 1 1092 * @Default: 0 1093 * 1094 * This ini is used to control DP Software to use 64 blockack 1095 * for RX direction forcibly 1096 * 1097 * Usage: Internal 1098 * 1099 * </ini> 1100 */ 1101 #define CFG_FORCE_RX_64_BA \ 1102 CFG_INI_BOOL("gForceRX64BA", \ 1103 false, "Enable/Disable force 64 blockack in RX side") 1104 1105 #define CFG_DP \ 1106 CFG(CFG_DP_HTT_PACKET_TYPE) \ 1107 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \ 1108 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \ 1109 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \ 1110 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \ 1111 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \ 1112 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \ 1113 CFG(CFG_DP_MAX_ALLOC_SIZE) \ 1114 CFG(CFG_DP_MAX_CLIENTS) \ 1115 CFG(CFG_DP_MAX_PEER_ID) \ 1116 CFG(CFG_DP_REO_DEST_RINGS) \ 1117 CFG(CFG_DP_TCL_DATA_RINGS) \ 1118 CFG(CFG_DP_NSS_REO_DEST_RINGS) \ 1119 CFG(CFG_DP_NSS_TCL_DATA_RINGS) \ 1120 CFG(CFG_DP_TX_DESC) \ 1121 CFG(CFG_DP_TX_EXT_DESC) \ 1122 CFG(CFG_DP_TX_EXT_DESC_POOLS) \ 1123 CFG(CFG_DP_PDEV_RX_RING) \ 1124 CFG(CFG_DP_PDEV_TX_RING) \ 1125 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \ 1126 CFG(CFG_DP_TX_COMPL_RING_SIZE) \ 1127 CFG(CFG_DP_TX_RING_SIZE) \ 1128 CFG(CFG_DP_NSS_COMP_RING_SIZE) \ 1129 CFG(CFG_DP_PDEV_LMAC_RING) \ 1130 CFG(CFG_DP_BASE_HW_MAC_ID) \ 1131 CFG(CFG_DP_RX_HASH) \ 1132 CFG(CFG_DP_TSO) \ 1133 CFG(CFG_DP_LRO) \ 1134 CFG(CFG_DP_SG) \ 1135 CFG(CFG_DP_GRO) \ 1136 CFG(CFG_DP_OL_TX_CSUM) \ 1137 CFG(CFG_DP_OL_RX_CSUM) \ 1138 CFG(CFG_DP_RAWMODE) \ 1139 CFG(CFG_DP_PEER_FLOW_CTRL) \ 1140 CFG(CFG_DP_NAPI) \ 1141 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \ 1142 CFG(CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD) \ 1143 CFG(CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD) \ 1144 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \ 1145 CFG(CFG_DP_WBM_RELEASE_RING) \ 1146 CFG(CFG_DP_TCL_CMD_CREDIT_RING) \ 1147 CFG(CFG_DP_TCL_STATUS_RING) \ 1148 CFG(CFG_DP_REO_REINJECT_RING) \ 1149 CFG(CFG_DP_RX_RELEASE_RING) \ 1150 CFG(CFG_DP_REO_EXCEPTION_RING) \ 1151 CFG(CFG_DP_REO_CMD_RING) \ 1152 CFG(CFG_DP_REO_STATUS_RING) \ 1153 CFG(CFG_DP_RXDMA_BUF_RING) \ 1154 CFG(CFG_DP_RXDMA_REFILL_RING) \ 1155 CFG(CFG_DP_TX_DESC_LIMIT_0) \ 1156 CFG(CFG_DP_TX_DESC_LIMIT_1) \ 1157 CFG(CFG_DP_TX_DESC_LIMIT_2) \ 1158 CFG(CFG_DP_TX_DEVICE_LIMIT) \ 1159 CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \ 1160 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \ 1161 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \ 1162 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \ 1163 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \ 1164 CFG(CFG_DP_RXDMA_ERR_DST_RING) \ 1165 CFG(CFG_DP_PER_PKT_LOGGING) \ 1166 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \ 1167 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \ 1168 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \ 1169 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \ 1170 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \ 1171 CFG(CFG_DP_REORDER_OFFLOAD_SUPPORT) \ 1172 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \ 1173 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) \ 1174 CFG(CFG_DP_RX_SW_DESC_WEIGHT) \ 1175 CFG(CFG_DP_RX_SW_DESC_NUM) \ 1176 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE) \ 1177 CFG(CFG_DP_RX_FLOW_TAG_ENABLE) \ 1178 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV) \ 1179 CFG(CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE) \ 1180 CFG(CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD) \ 1181 CFG(CFG_DP_PKTLOG_BUFFER_SIZE) \ 1182 CFG(CFG_DP_RX_FISA_ENABLE) \ 1183 CFG(CFG_DP_FULL_MON_MODE) \ 1184 CFG(CFG_DP_REO_RINGS_MAP) \ 1185 CFG(CFG_DP_PEER_EXT_STATS) \ 1186 CFG(CFG_DP_RX_BUFF_POOL_ENABLE) \ 1187 CFG(CFG_DP_RX_PENDING_HL_THRESHOLD) \ 1188 CFG(CFG_DP_RX_PENDING_LO_THRESHOLD) \ 1189 CFG(CFG_DP_LEGACY_MODE_CSUM_DISABLE) \ 1190 CFG(CFG_DP_POLL_MODE_ENABLE) \ 1191 CFG(CFG_DP_SWLM_ENABLE) \ 1192 CFG(CFG_DP_TX_PER_PKT_VDEV_ID_CHECK) \ 1193 CFG(CFG_DP_RX_FST_IN_CMEM) \ 1194 CFG(CFG_DP_RX_RADIO_0_DEFAULT_REO) \ 1195 CFG(CFG_DP_RX_RADIO_1_DEFAULT_REO) \ 1196 CFG(CFG_DP_RX_RADIO_2_DEFAULT_REO) \ 1197 CFG(CFG_DP_WOW_CHECK_RX_PENDING) \ 1198 CFG(CFG_FORCE_RX_64_BA) 1199 #endif /* _CFG_DP_H_ */ 1200