1 /* 2 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * DOC: This file contains definitions of Data Path configuration. 22 */ 23 24 #ifndef _CFG_DP_H_ 25 #define _CFG_DP_H_ 26 27 #include "cfg_define.h" 28 #include "wlan_init_cfg.h" 29 30 #define WLAN_CFG_MAX_CLIENTS 64 31 #define WLAN_CFG_MAX_CLIENTS_MIN 8 32 #define WLAN_CFG_MAX_CLIENTS_MAX 64 33 34 /* Change this to a lower value to enforce scattered idle list mode */ 35 #define WLAN_CFG_MAX_ALLOC_SIZE 0x200000 36 #define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000 37 #define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000 38 39 #if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \ 40 defined(QCA_LL_PDEV_TX_FLOW_CONTROL) 41 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10 42 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15 43 #else 44 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 45 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 46 #endif 47 48 #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0 49 #define WLAN_CFG_PER_PDEV_TX_RING_MAX 1 50 51 #ifdef IPA_OFFLOAD 52 /* Size of TCL TX Ring */ 53 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 54 #define WLAN_CFG_TX_RING_SIZE 2048 55 #else 56 #define WLAN_CFG_TX_RING_SIZE 1024 57 #endif 58 59 #define WLAN_CFG_IPA_TX_RING_SIZE_MIN 1024 60 #define WLAN_CFG_IPA_TX_RING_SIZE 1024 61 #define WLAN_CFG_IPA_TX_RING_SIZE_MAX 8096 62 63 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN 1024 64 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE 1024 65 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX 8096 66 67 #ifdef IPA_WDI3_TX_TWO_PIPES 68 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN 1024 69 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE 1024 70 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX 8096 71 72 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN 1024 73 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE 1024 74 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX 8096 75 #endif 76 77 #define WLAN_CFG_PER_PDEV_TX_RING 0 78 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048 79 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000 80 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024 81 #else 82 #define WLAN_CFG_TX_RING_SIZE 512 83 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 84 #define WLAN_CFG_PER_PDEV_TX_RING 1 85 #else 86 #define WLAN_CFG_PER_PDEV_TX_RING 0 87 #endif 88 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 89 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 90 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 91 #endif /* IPA_OFFLOAD */ 92 93 #define WLAN_CFG_TIME_CONTROL_BP 3000 94 95 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 96 #define WLAN_CFG_PER_PDEV_RX_RING 0 97 #define WLAN_CFG_PER_PDEV_LMAC_RING 0 98 #define WLAN_LRO_ENABLE 0 99 #ifdef QCA_WIFI_QCA6750 100 #define WLAN_CFG_MAC_PER_TARGET 1 101 #else 102 #define WLAN_CFG_MAC_PER_TARGET 2 103 #endif 104 105 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 106 #define WLAN_CFG_TX_COMP_RING_SIZE 4096 107 108 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 109 #define WLAN_CFG_NUM_TX_DESC 4096 110 #define WLAN_CFG_NUM_TX_EXT_DESC 4096 111 #else 112 #define WLAN_CFG_TX_COMP_RING_SIZE 1024 113 114 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 115 #define WLAN_CFG_NUM_TX_DESC 1024 116 #define WLAN_CFG_NUM_TX_EXT_DESC 1024 117 #endif 118 119 /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 120 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1 121 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 122 123 /* Interrupt Mitigation - Timer threshold in us */ 124 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8 125 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8 126 127 #ifdef WLAN_DP_PER_RING_TYPE_CONFIG 128 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX \ 129 WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 130 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX \ 131 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 132 #else 133 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1 134 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8 135 #endif 136 #endif /* WLAN_MAX_PDEVS */ 137 138 #ifdef NBUF_MEMORY_DEBUG 139 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0xFFFF 140 #else 141 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0x1FFFF 142 #endif 143 144 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD \ 145 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 146 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN 0 147 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX 0x200000 148 149 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD \ 150 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 151 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN 100 152 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX 0x200000 153 154 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256 155 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 512 156 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 0 157 158 #define WLAN_CFG_PER_PDEV_RX_RING_MIN 0 159 #define WLAN_CFG_PER_PDEV_RX_RING_MAX 0 160 161 #define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0 162 #define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1 163 164 #define WLAN_CFG_TX_RING_SIZE_MIN 512 165 #define WLAN_CFG_TX_RING_SIZE_MAX 0x80000 166 167 #define WLAN_CFG_TIME_CONTROL_BP_MIN 3000 168 #define WLAN_CFG_TIME_CONTROL_BP_MAX 1800000 169 170 #define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512 171 #define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000 172 173 #define WLAN_CFG_NUM_TX_DESC_MIN 16 174 #define WLAN_CFG_NUM_TX_DESC_MAX 0x10000 175 176 #define WLAN_CFG_NUM_TX_EXT_DESC_MIN 16 177 #define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000 178 179 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1 180 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256 181 182 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 0 183 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128 184 185 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1 186 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128 187 188 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1 189 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128 190 191 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1 192 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1 193 194 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8 195 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 1000 196 197 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8 198 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500 199 200 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8 201 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000 202 203 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8 204 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 512 205 206 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8 207 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500 208 209 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000 210 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000 211 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000 212 213 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 214 215 /* Per vdev pools */ 216 #define WLAN_CFG_NUM_TX_DESC_POOL 3 217 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 218 219 #else /* QCA_LL_TX_FLOW_CONTROL_V2 */ 220 221 #ifdef TX_PER_PDEV_DESC_POOL 222 #define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT 223 #define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT 224 225 #else /* TX_PER_PDEV_DESC_POOL */ 226 227 #define WLAN_CFG_NUM_TX_DESC_POOL 3 228 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 229 230 #endif /* TX_PER_PDEV_DESC_POOL */ 231 #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */ 232 233 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1 234 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4 235 236 #define WLAN_CFG_HTT_PKT_TYPE 2 237 #define WLAN_CFG_HTT_PKT_TYPE_MIN 2 238 #define WLAN_CFG_HTT_PKT_TYPE_MAX 2 239 240 #define WLAN_CFG_MAX_PEER_ID 64 241 #define WLAN_CFG_MAX_PEER_ID_MIN 64 242 #define WLAN_CFG_MAX_PEER_ID_MAX 64 243 244 #define WLAN_CFG_RX_DEFRAG_TIMEOUT 100 245 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100 246 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100 247 248 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 249 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 1 250 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX MAX_TCL_DATA_RINGS 251 252 #define WLAN_CFG_NUM_TX_COMP_RINGS WLAN_CFG_NUM_TCL_DATA_RINGS 253 #define WLAN_CFG_NUM_TX_COMP_RINGS_MIN WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 254 #define WLAN_CFG_NUM_TX_COMP_RINGS_MAX WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 255 256 #if defined(CONFIG_BERYLLIUM) 257 #define WLAN_CFG_NUM_REO_DEST_RING 8 258 #else 259 #define WLAN_CFG_NUM_REO_DEST_RING 4 260 #endif 261 #define WLAN_CFG_NUM_REO_DEST_RING_MIN 4 262 #define WLAN_CFG_NUM_REO_DEST_RING_MAX MAX_REO_DEST_RINGS 263 264 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS 2 265 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN 1 266 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX 3 267 268 #define WLAN_CFG_NSS_NUM_REO_DEST_RING 2 269 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN 1 270 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX 3 271 272 #define WLAN_CFG_WBM_RELEASE_RING_SIZE 1024 273 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64 274 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 1024 275 276 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE 512 277 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN 32 278 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX 512 279 280 #define WLAN_CFG_TCL_STATUS_RING_SIZE 32 281 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32 282 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32 283 284 #if defined(QCA_WIFI_QCA6290) 285 #define WLAN_CFG_REO_DST_RING_SIZE 1024 286 #else 287 #define WLAN_CFG_REO_DST_RING_SIZE 2048 288 #endif 289 290 #define WLAN_CFG_REO_DST_RING_SIZE_MIN 8 291 #define WLAN_CFG_REO_DST_RING_SIZE_MAX 8192 292 293 #define WLAN_CFG_REO_REINJECT_RING_SIZE 128 294 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32 295 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 128 296 297 #define WLAN_CFG_RX_RELEASE_RING_SIZE 1024 298 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8 299 #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 300 defined(QCA_WIFI_QCA6750) || defined(QCA_WIFI_KIWI) 301 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024 302 #else 303 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 32768 304 #endif 305 306 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE 256 307 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128 308 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 512 309 310 #define WLAN_CFG_REO_CMD_RING_SIZE 128 311 #define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64 312 #define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128 313 314 #define WLAN_CFG_REO_STATUS_RING_SIZE 256 315 #define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128 316 #define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048 317 318 #define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024 319 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024 320 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 4096 321 322 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096 323 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16 324 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 16384 325 326 #define WLAN_CFG_TX_DESC_LIMIT_0 0 327 #define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096 328 #define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768 329 330 #define WLAN_CFG_TX_DESC_LIMIT_1 0 331 #define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096 332 #define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768 333 334 #define WLAN_CFG_TX_DESC_LIMIT_2 0 335 #define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096 336 #define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768 337 338 #define WLAN_CFG_TX_DEVICE_LIMIT 65536 339 #define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384 340 #define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536 341 342 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024 343 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128 344 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024 345 346 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096 347 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16 348 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192 349 350 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE 4096 351 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN 16 352 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX 8192 353 354 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048 355 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48 356 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192 357 358 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE 2048 359 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN 48 360 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX 8192 361 362 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024 363 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16 364 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192 365 366 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096 367 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096 368 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384 369 370 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024 371 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024 372 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192 373 374 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE 32 375 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN 0 376 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX 256 377 378 /** 379 * Allocate as many RX descriptors as buffers in the SW2RXDMA 380 * ring. This value may need to be tuned later. 381 */ 382 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 383 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 384 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 385 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 1 386 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 387 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 388 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 389 390 /** 391 * For low memory AP cases using 1 will reduce the rx descriptors memory req 392 */ 393 #elif defined(QCA_LOWMEM_CONFIG) || defined(QCA_512M_CONFIG) 394 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 395 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 396 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 397 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 398 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 399 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 400 401 /** 402 * AP use cases need to allocate more RX Descriptors than the number of 403 * entries available in the SW2RXDMA buffer replenish ring. This is to account 404 * for frames sitting in REO queues, HW-HW DMA rings etc. Hence using a 405 * multiplication factor of 3, to allocate three times as many RX descriptors 406 * as RX buffers. 407 */ 408 #else 409 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 3 410 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 411 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 412 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 12288 413 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 4096 414 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 415 #endif 416 417 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE 16384 418 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN 1 419 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX 16384 420 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT 128 421 422 #define WLAN_CFG_PKTLOG_BUFFER_SIZE 10 423 #define WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE 1 424 #define WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE 10 425 426 #ifdef IPA_OFFLOAD 427 #define WLAN_CFG_NUM_REO_RINGS_MAP 0x7 428 #else 429 #define WLAN_CFG_NUM_REO_RINGS_MAP 0xF 430 #endif 431 #define WLAN_CFG_NUM_REO_RINGS_MAP_MIN 0x1 432 #if defined(CONFIG_BERYLLIUM) 433 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xFF 434 #else 435 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xF 436 #endif 437 438 #define WLAN_CFG_RADIO_0_DEFAULT_REO 0x1 439 #define WLAN_CFG_RADIO_1_DEFAULT_REO 0x2 440 #define WLAN_CFG_RADIO_2_DEFAULT_REO 0x3 441 442 #define WLAN_CFG_RADIO_DEFAULT_REO_MIN 0x1 443 #define WLAN_CFG_RADIO_DEFAULT_REO_MAX 0x4 444 445 #define WLAN_CFG_REO2PPE_RING_SIZE 2048 446 #define WLAN_CFG_REO2PPE_RING_SIZE_MIN 64 447 #define WLAN_CFG_REO2PPE_RING_SIZE_MAX 16384 448 449 #define WLAN_CFG_PPE2TCL_RING_SIZE 1024 450 #define WLAN_CFG_PPE2TCL_RING_SIZE_MIN 64 451 #define WLAN_CFG_PPE2TCL_RING_SIZE_MAX 1024 452 453 #define WLAN_CFG_PPE_RELEASE_RING_SIZE 1024 454 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MIN 64 455 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MAX 1024 456 457 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 458 #define WLAN_CFG_MLO_RX_RING_MAP 0x7 459 #define WLAN_CFG_MLO_RX_RING_MAP_MIN 0x0 460 #define WLAN_CFG_MLO_RX_RING_MAP_MAX 0xFF 461 #endif 462 463 #define WLAN_CFG_TX_CAPT_MAX_MEM_MIN 0 464 #define WLAN_CFG_TX_CAPT_MAX_MEM_MAX 512 465 #define WLAN_CFG_TX_CAPT_MAX_MEM_DEFAULT 0 466 467 #define CFG_DP_MPDU_RETRY_THRESHOLD_MIN 0 468 #define CFG_DP_MPDU_RETRY_THRESHOLD_MAX 255 469 #define CFG_DP_MPDU_RETRY_THRESHOLD 0 470 471 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR 0 472 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR_MIN 0 473 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR_MAX 4 474 475 #ifdef CONFIG_SAWF_STATS 476 #define WLAN_CFG_SAWF_STATS 0x0 477 #define WLAN_CFG_SAWF_STATS_MIN 0x0 478 #define WLAN_CFG_SAWF_STATS_MAX 0x7 479 #endif 480 /* 481 * <ini> 482 * "dp_tx_capt_max_mem_mb"- maximum memory used by Tx capture 483 * @Min: 0 484 * @Max: 512 MB 485 * @Default: 0 (disabled) 486 * 487 * This ini entry is used to set a max limit beyond which frames 488 * are dropped by Tx capture. User needs to set a non-zero value 489 * to enable it. 490 * 491 * Usage: External 492 * 493 * </ini> 494 */ 495 #define CFG_DP_TX_CAPT_MAX_MEM_MB \ 496 CFG_INI_UINT("dp_tx_capt_max_mem_mb", \ 497 WLAN_CFG_TX_CAPT_MAX_MEM_MIN, \ 498 WLAN_CFG_TX_CAPT_MAX_MEM_MAX, \ 499 WLAN_CFG_TX_CAPT_MAX_MEM_DEFAULT, \ 500 CFG_VALUE_OR_DEFAULT, "Max Memory (in MB) used by Tx Capture") 501 502 /* DP INI Declarations */ 503 #define CFG_DP_HTT_PACKET_TYPE \ 504 CFG_INI_UINT("dp_htt_packet_type", \ 505 WLAN_CFG_HTT_PKT_TYPE_MIN, \ 506 WLAN_CFG_HTT_PKT_TYPE_MAX, \ 507 WLAN_CFG_HTT_PKT_TYPE, \ 508 CFG_VALUE_OR_DEFAULT, "DP HTT packet type") 509 510 #define CFG_DP_INT_BATCH_THRESHOLD_OTHER \ 511 CFG_INI_UINT("dp_int_batch_threshold_other", \ 512 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \ 513 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \ 514 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \ 515 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other") 516 517 #define CFG_DP_INT_BATCH_THRESHOLD_RX \ 518 CFG_INI_UINT("dp_int_batch_threshold_rx", \ 519 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \ 520 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \ 521 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \ 522 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx") 523 524 #define CFG_DP_INT_BATCH_THRESHOLD_TX \ 525 CFG_INI_UINT("dp_int_batch_threshold_tx", \ 526 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \ 527 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \ 528 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \ 529 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx") 530 531 #define CFG_DP_INT_TIMER_THRESHOLD_OTHER \ 532 CFG_INI_UINT("dp_int_timer_threshold_other", \ 533 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \ 534 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \ 535 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \ 536 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other") 537 538 #define CFG_DP_INT_TIMER_THRESHOLD_RX \ 539 CFG_INI_UINT("dp_int_timer_threshold_rx", \ 540 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \ 541 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \ 542 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \ 543 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx") 544 545 #define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \ 546 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \ 547 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \ 548 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \ 549 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \ 550 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring") 551 552 #define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \ 553 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \ 554 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \ 555 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \ 556 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \ 557 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring") 558 559 #define CFG_DP_INT_TIMER_THRESHOLD_TX \ 560 CFG_INI_UINT("dp_int_timer_threshold_tx", \ 561 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \ 562 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \ 563 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \ 564 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx") 565 566 #define CFG_DP_MAX_ALLOC_SIZE \ 567 CFG_INI_UINT("dp_max_alloc_size", \ 568 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \ 569 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \ 570 WLAN_CFG_MAX_ALLOC_SIZE, \ 571 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size") 572 573 #define CFG_DP_MAX_CLIENTS \ 574 CFG_INI_UINT("dp_max_clients", \ 575 WLAN_CFG_MAX_CLIENTS_MIN, \ 576 WLAN_CFG_MAX_CLIENTS_MAX, \ 577 WLAN_CFG_MAX_CLIENTS, \ 578 CFG_VALUE_OR_DEFAULT, "DP Max Clients") 579 580 #define CFG_DP_MAX_PEER_ID \ 581 CFG_INI_UINT("dp_max_peer_id", \ 582 WLAN_CFG_MAX_PEER_ID_MIN, \ 583 WLAN_CFG_MAX_PEER_ID_MAX, \ 584 WLAN_CFG_MAX_PEER_ID, \ 585 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID") 586 587 #define CFG_DP_REO_DEST_RINGS \ 588 CFG_INI_UINT("dp_reo_dest_rings", \ 589 WLAN_CFG_NUM_REO_DEST_RING_MIN, \ 590 WLAN_CFG_NUM_REO_DEST_RING_MAX, \ 591 WLAN_CFG_NUM_REO_DEST_RING, \ 592 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings") 593 594 #define CFG_DP_TX_COMP_RINGS \ 595 CFG_INI_UINT("dp_tx_comp_rings", \ 596 WLAN_CFG_NUM_TX_COMP_RINGS_MIN, \ 597 WLAN_CFG_NUM_TX_COMP_RINGS_MAX, \ 598 WLAN_CFG_NUM_TX_COMP_RINGS, \ 599 CFG_VALUE_OR_DEFAULT, "DP Tx Comp Rings") 600 601 #define CFG_DP_TCL_DATA_RINGS \ 602 CFG_INI_UINT("dp_tcl_data_rings", \ 603 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \ 604 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \ 605 WLAN_CFG_NUM_TCL_DATA_RINGS, \ 606 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings") 607 608 #define CFG_DP_NSS_REO_DEST_RINGS \ 609 CFG_INI_UINT("dp_nss_reo_dest_rings", \ 610 WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN, \ 611 WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX, \ 612 WLAN_CFG_NSS_NUM_REO_DEST_RING, \ 613 CFG_VALUE_OR_DEFAULT, "DP NSS REO Destination Rings") 614 615 #define CFG_DP_NSS_TCL_DATA_RINGS \ 616 CFG_INI_UINT("dp_nss_tcl_data_rings", \ 617 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN, \ 618 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX, \ 619 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS, \ 620 CFG_VALUE_OR_DEFAULT, "DP NSS TCL Data Rings") 621 622 #define CFG_DP_TX_DESC \ 623 CFG_INI_UINT("dp_tx_desc", \ 624 WLAN_CFG_NUM_TX_DESC_MIN, \ 625 WLAN_CFG_NUM_TX_DESC_MAX, \ 626 WLAN_CFG_NUM_TX_DESC, \ 627 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors") 628 629 #define CFG_DP_TX_EXT_DESC \ 630 CFG_INI_UINT("dp_tx_ext_desc", \ 631 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \ 632 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \ 633 WLAN_CFG_NUM_TX_EXT_DESC, \ 634 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors") 635 636 #define CFG_DP_TX_EXT_DESC_POOLS \ 637 CFG_INI_UINT("dp_tx_ext_desc_pool", \ 638 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \ 639 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \ 640 WLAN_CFG_NUM_TXEXT_DESC_POOL, \ 641 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool") 642 643 #define CFG_DP_PDEV_RX_RING \ 644 CFG_INI_UINT("dp_pdev_rx_ring", \ 645 WLAN_CFG_PER_PDEV_RX_RING_MIN, \ 646 WLAN_CFG_PER_PDEV_RX_RING_MAX, \ 647 WLAN_CFG_PER_PDEV_RX_RING, \ 648 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring") 649 650 #define CFG_DP_PDEV_TX_RING \ 651 CFG_INI_UINT("dp_pdev_tx_ring", \ 652 WLAN_CFG_PER_PDEV_TX_RING_MIN, \ 653 WLAN_CFG_PER_PDEV_TX_RING_MAX, \ 654 WLAN_CFG_PER_PDEV_TX_RING, \ 655 CFG_VALUE_OR_DEFAULT, \ 656 "DP PDEV Tx Ring") 657 658 #define CFG_DP_RX_DEFRAG_TIMEOUT \ 659 CFG_INI_UINT("dp_rx_defrag_timeout", \ 660 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \ 661 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \ 662 WLAN_CFG_RX_DEFRAG_TIMEOUT, \ 663 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout") 664 665 #define CFG_DP_TX_COMPL_RING_SIZE \ 666 CFG_INI_UINT("dp_tx_compl_ring_size", \ 667 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \ 668 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \ 669 WLAN_CFG_TX_COMP_RING_SIZE, \ 670 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size") 671 672 #define CFG_DP_TX_RING_SIZE \ 673 CFG_INI_UINT("dp_tx_ring_size", \ 674 WLAN_CFG_TX_RING_SIZE_MIN,\ 675 WLAN_CFG_TX_RING_SIZE_MAX,\ 676 WLAN_CFG_TX_RING_SIZE,\ 677 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size") 678 679 #define CFG_DP_NSS_COMP_RING_SIZE \ 680 CFG_INI_UINT("dp_nss_comp_ring_size", \ 681 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \ 682 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \ 683 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \ 684 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size") 685 686 #define CFG_DP_PDEV_LMAC_RING \ 687 CFG_INI_UINT("dp_pdev_lmac_ring", \ 688 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \ 689 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \ 690 WLAN_CFG_PER_PDEV_LMAC_RING, \ 691 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring") 692 693 #define CFG_DP_TIME_CONTROL_BP \ 694 CFG_INI_UINT("dp_time_control_bp", \ 695 WLAN_CFG_TIME_CONTROL_BP_MIN,\ 696 WLAN_CFG_TIME_CONTROL_BP_MAX,\ 697 WLAN_CFG_TIME_CONTROL_BP,\ 698 CFG_VALUE_OR_DEFAULT, "DP time control back pressure") 699 700 #ifdef CONFIG_SAWF_STATS 701 #define CFG_DP_SAWF_STATS \ 702 CFG_INI_UINT("dp_sawf_stats", \ 703 WLAN_CFG_SAWF_STATS_MIN,\ 704 WLAN_CFG_SAWF_STATS_MAX,\ 705 WLAN_CFG_SAWF_STATS,\ 706 CFG_VALUE_OR_DEFAULT, "DP sawf stats config") 707 #define CFG_DP_SAWF_STATS_CONFIG CFG(CFG_DP_SAWF_STATS) 708 #else 709 #define CFG_DP_SAWF_STATS_CONFIG 710 #endif 711 712 /* 713 * <ini> 714 * dp_rx_pending_hl_threshold - High threshold of frame number to start 715 * frame dropping scheme 716 * @Min: 0 717 * @Max: 524288 718 * @Default: 393216 719 * 720 * This ini entry is used to set a high limit threshold to start frame 721 * dropping scheme 722 * 723 * Usage: External 724 * 725 * </ini> 726 */ 727 #define CFG_DP_RX_PENDING_HL_THRESHOLD \ 728 CFG_INI_UINT("dp_rx_pending_hl_threshold", \ 729 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN, \ 730 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX, \ 731 WLAN_CFG_RX_PENDING_HL_THRESHOLD, \ 732 CFG_VALUE_OR_DEFAULT, "DP rx pending hl threshold") 733 734 /* 735 * <ini> 736 * dp_rx_pending_lo_threshold - Low threshold of frame number to stop 737 * frame dropping scheme 738 * @Min: 100 739 * @Max: 524288 740 * @Default: 393216 741 * 742 * This ini entry is used to set a low limit threshold to stop frame 743 * dropping scheme 744 * 745 * Usage: External 746 * 747 * </ini> 748 */ 749 #define CFG_DP_RX_PENDING_LO_THRESHOLD \ 750 CFG_INI_UINT("dp_rx_pending_lo_threshold", \ 751 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN, \ 752 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX, \ 753 WLAN_CFG_RX_PENDING_LO_THRESHOLD, \ 754 CFG_VALUE_OR_DEFAULT, "DP rx pending lo threshold") 755 756 #define CFG_DP_BASE_HW_MAC_ID \ 757 CFG_INI_UINT("dp_base_hw_macid", \ 758 0, 1, 1, \ 759 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID") 760 761 #define CFG_DP_RX_HASH \ 762 CFG_INI_BOOL("dp_rx_hash", true, \ 763 "DP Rx Hash") 764 765 #define CFG_DP_TSO \ 766 CFG_INI_BOOL("TSOEnable", false, \ 767 "DP TSO Enabled") 768 769 #define CFG_DP_LRO \ 770 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \ 771 "DP LRO Enable") 772 773 #ifdef WLAN_USE_CONFIG_PARAMS 774 /* 775 * <ini> 776 * dp_tx_desc_use_512p - Use 512M tx descriptor size 777 * @Min: 0 778 * @Max: 1 779 * @Default: 0 780 * 781 * This ini entry is used as flag to use 512M tx descriptor size or not 782 * 783 * Usage: Internal 784 * 785 * </ini> 786 */ 787 #define CFG_DP_TX_DESC_512P \ 788 CFG_INI_BOOL("dp_tx_desc_use_512p", false, \ 789 "DP TX DESC PINE SPECIFIC") 790 791 /* 792 * <ini> 793 * dp_nss_3radio_ring - Use 3 Radio NSS comp ring size 794 * @Min: 0 795 * @Max: 1 796 * @Default: 0 797 * 798 * This ini entry is used as flag to use 3 Radio NSS com ring size or not 799 * 800 * Usage: Internal 801 * 802 * </ini> 803 */ 804 #define CFG_DP_NSS_3RADIO_RING \ 805 CFG_INI_BOOL("dp_nss_3radio_ring", false, \ 806 "DP NSS 3 RADIO RING SIZE") 807 808 /* 809 * <ini> 810 * dp_mon_ring_per_512M - Update monitor status ring as 512M profile 811 * @Min: 0 812 * @Max: 1 813 * @Default: 0 814 * 815 * This ini entry is used as flag to update monitor status ring as 512M profile 816 * 817 * Usage: Internal 818 * 819 * </ini> 820 */ 821 #define CFG_DP_MON_STATUS_512M \ 822 CFG_INI_BOOL("dp_mon_ring_per_512M", false, \ 823 "DP MON STATUS RING SIZE PER 512M PROFILE") 824 825 /* 826 * <ini> 827 * dp_mon_2chain_ring - Reduce monitor rings size as for 2 Chains case 828 * @Min: 0 829 * @Max: 1 830 * @Default: 0 831 * 832 * This ini entry is used as flag to reduce monitor rings size as those used 833 * in case of 2 Tx/RxChains 834 * 835 * Usage: Internal 836 * 837 * </ini> 838 */ 839 #define CFG_DP_MON_2CHAIN_RING \ 840 CFG_INI_BOOL("dp_mon_2chain_ring", false, \ 841 "DP MON UPDATE RINGS FOR 2CHAIN") 842 843 /* 844 * <ini> 845 * dp_mon_4chain_ring - Update monitor rings size for 4 Chains case 846 * @Min: 0 847 * @Max: 1 848 * @Default: 0 849 * 850 * This ini entry is used as flag to reduce monitor rings size as those used 851 * in case of 4 Tx/RxChains 852 * 853 * Usage: Internal 854 * 855 * </ini> 856 */ 857 #define CFG_DP_MON_4CHAIN_RING \ 858 CFG_INI_BOOL("dp_mon_4chain_ring", false, \ 859 "DP MON UPDATE RINGS FOR 4CHAIN") 860 861 /* 862 * <ini> 863 * dp_4radip_rdp_reo - Update RDP REO map based on 4 radio config 864 * @Min: 0 865 * @Max: 1 866 * @Default: 0 867 * 868 * This ini entry is used as flag to update RDP reo map based on 4 Radio config 869 * 870 * Usage: Internal 871 * 872 * </ini> 873 */ 874 #define CFG_DP_4RADIO_RDP_REO \ 875 CFG_INI_BOOL("dp_nss_4radio_rdp_reo", \ 876 false, "Update REO destination mapping for 4radio") 877 878 #define CFG_DP_INI_SECTION_PARAMS \ 879 CFG(CFG_DP_NSS_3RADIO_RING) \ 880 CFG(CFG_DP_TX_DESC_512P) \ 881 CFG(CFG_DP_MON_STATUS_512M) \ 882 CFG(CFG_DP_MON_2CHAIN_RING) \ 883 CFG(CFG_DP_MON_4CHAIN_RING) \ 884 CFG(CFG_DP_4RADIO_RDP_REO) 885 #else 886 #define CFG_DP_INI_SECTION_PARAMS 887 #endif 888 889 /* 890 * <ini> 891 * CFG_DP_SG - Enable the SG feature standalonely 892 * @Min: 0 893 * @Max: 1 894 * @Default: 1 895 * 896 * This ini entry is used to enable/disable SG feature standalonely. 897 * Also does Rome support SG on TX, lithium does not. 898 * For example the lithium does not support SG on UDP frames. 899 * Which is able to handle SG only for TSO frames(in case TSO is enabled). 900 * 901 * Usage: External 902 * 903 * </ini> 904 */ 905 #define CFG_DP_SG \ 906 CFG_INI_BOOL("dp_sg_support", false, \ 907 "DP SG Enable") 908 909 #define WLAN_CFG_GRO_ENABLE_MIN 0 910 #define WLAN_CFG_GRO_ENABLE_MAX 3 911 #define WLAN_CFG_GRO_ENABLE_DEFAULT 0 912 #define DP_GRO_ENABLE_BIT_SET BIT(0) 913 #define DP_TC_BASED_DYNAMIC_GRO BIT(1) 914 915 /* 916 * <ini> 917 * CFG_DP_GRO - Enable the GRO feature standalonely 918 * @Min: 0 919 * @Max: 3 920 * @Default: 0 921 * 922 * This ini entry is used to enable/disable GRO feature standalonely. 923 * Value 0: Disable GRO feature 924 * Value 1: Enable GRO feature always 925 * Value 3: Enable GRO dynamic feature where TC rule can control GRO 926 * behavior 927 * 928 * Usage: External 929 * 930 * </ini> 931 */ 932 #define CFG_DP_GRO \ 933 CFG_INI_UINT("GROEnable", \ 934 WLAN_CFG_GRO_ENABLE_MIN, \ 935 WLAN_CFG_GRO_ENABLE_MAX, \ 936 WLAN_CFG_GRO_ENABLE_DEFAULT, \ 937 CFG_VALUE_OR_DEFAULT, "DP GRO Enable") 938 939 #define WLAN_CFG_TC_INGRESS_PRIO_MIN 0 940 #define WLAN_CFG_TC_INGRESS_PRIO_MAX 0xFFFF 941 #define WLAN_CFG_TC_INGRESS_PRIO_DEFAULT 0 942 943 #define CFG_DP_TC_INGRESS_PRIO \ 944 CFG_INI_UINT("tc_ingress_prio", \ 945 WLAN_CFG_TC_INGRESS_PRIO_MIN, \ 946 WLAN_CFG_TC_INGRESS_PRIO_MAX, \ 947 WLAN_CFG_TC_INGRESS_PRIO_DEFAULT, \ 948 CFG_VALUE_OR_DEFAULT, "DP tc ingress prio") 949 950 #define CFG_DP_OL_TX_CSUM \ 951 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \ 952 "DP tx csum Enable") 953 954 #define CFG_DP_OL_RX_CSUM \ 955 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \ 956 "DP rx csum Enable") 957 958 #define CFG_DP_RAWMODE \ 959 CFG_INI_BOOL("dp_rawmode_support", false, \ 960 "DP rawmode Enable") 961 962 #define CFG_DP_PEER_FLOW_CTRL \ 963 CFG_INI_BOOL("dp_peer_flow_control_support", false, \ 964 "DP peer flow ctrl Enable") 965 966 #define CFG_DP_NAPI \ 967 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \ 968 "DP Napi Enabled") 969 /* 970 * <ini> 971 * gEnableP2pIpTcpUdpChecksumOffload - Enable checksum offload for P2P mode 972 * @Min: 0 973 * @Max: 1 974 * @Default: 1 975 * 976 * This ini entry is used to enable/disable TX checksum(UDP/TCP) for P2P modes. 977 * This includes P2P device mode, P2P client mode and P2P GO mode. 978 * The feature is enabled by default. To disable TX checksum for P2P, add the 979 * following entry in ini file: 980 * gEnableP2pIpTcpUdpChecksumOffload=0 981 * 982 * Usage: External 983 * 984 * </ini> 985 */ 986 #define CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD \ 987 CFG_INI_BOOL("gEnableP2pIpTcpUdpChecksumOffload", true, \ 988 "DP TCP UDP Checksum Offload for P2P mode (device/cli/go)") 989 990 /* 991 * <ini> 992 * gEnableNanIpTcpUdpChecksumOffload - Enable checksum offload for NAN mode 993 * @Min: 0 994 * @Max: 1 995 * @Default: 1 996 * 997 * Usage: External 998 * 999 * </ini> 1000 */ 1001 #define CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD \ 1002 CFG_INI_BOOL("gEnableNanIpTcpUdpChecksumOffload", true, \ 1003 "DP TCP UDP Checksum Offload for NAN mode") 1004 1005 /* 1006 * <ini> 1007 * gEnableIpTcpUdpChecksumOffload - Enable checksum offload 1008 * @Min: 0 1009 * @Max: 1 1010 * @Default: 1 1011 * 1012 * Usage: External 1013 * 1014 * </ini> 1015 */ 1016 #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \ 1017 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \ 1018 "DP TCP UDP Checksum Offload") 1019 1020 #define CFG_DP_DEFRAG_TIMEOUT_CHECK \ 1021 CFG_INI_BOOL("dp_defrag_timeout_check", true, \ 1022 "DP Defrag Timeout Check") 1023 1024 #define CFG_DP_WBM_RELEASE_RING \ 1025 CFG_INI_UINT("dp_wbm_release_ring", \ 1026 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \ 1027 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \ 1028 WLAN_CFG_WBM_RELEASE_RING_SIZE, \ 1029 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring") 1030 1031 #define CFG_DP_TCL_CMD_CREDIT_RING \ 1032 CFG_INI_UINT("dp_tcl_cmd_credit_ring", \ 1033 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN, \ 1034 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX, \ 1035 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE, \ 1036 CFG_VALUE_OR_DEFAULT, "DP TCL Cmd_Credit ring") 1037 1038 #define CFG_DP_TCL_STATUS_RING \ 1039 CFG_INI_UINT("dp_tcl_status_ring",\ 1040 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \ 1041 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \ 1042 WLAN_CFG_TCL_STATUS_RING_SIZE, \ 1043 CFG_VALUE_OR_DEFAULT, "DP TCL status ring") 1044 1045 #define CFG_DP_REO_REINJECT_RING \ 1046 CFG_INI_UINT("dp_reo_reinject_ring", \ 1047 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \ 1048 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \ 1049 WLAN_CFG_REO_REINJECT_RING_SIZE, \ 1050 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring") 1051 1052 #define CFG_DP_RX_RELEASE_RING \ 1053 CFG_INI_UINT("dp_rx_release_ring", \ 1054 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \ 1055 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \ 1056 WLAN_CFG_RX_RELEASE_RING_SIZE, \ 1057 CFG_VALUE_OR_DEFAULT, "DP Rx release ring") 1058 1059 #define CFG_DP_RX_DESTINATION_RING \ 1060 CFG_INI_UINT("dp_reo_dst_ring", \ 1061 WLAN_CFG_REO_DST_RING_SIZE_MIN, \ 1062 WLAN_CFG_REO_DST_RING_SIZE_MAX, \ 1063 WLAN_CFG_REO_DST_RING_SIZE, \ 1064 CFG_VALUE_OR_DEFAULT, "DP REO destination ring") 1065 1066 #define CFG_DP_REO_EXCEPTION_RING \ 1067 CFG_INI_UINT("dp_reo_exception_ring", \ 1068 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \ 1069 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \ 1070 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \ 1071 CFG_VALUE_OR_DEFAULT, "DP REO exception ring") 1072 1073 #define CFG_DP_REO_CMD_RING \ 1074 CFG_INI_UINT("dp_reo_cmd_ring", \ 1075 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \ 1076 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \ 1077 WLAN_CFG_REO_CMD_RING_SIZE, \ 1078 CFG_VALUE_OR_DEFAULT, "DP REO command ring") 1079 1080 #define CFG_DP_REO_STATUS_RING \ 1081 CFG_INI_UINT("dp_reo_status_ring", \ 1082 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \ 1083 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \ 1084 WLAN_CFG_REO_STATUS_RING_SIZE, \ 1085 CFG_VALUE_OR_DEFAULT, "DP REO status ring") 1086 1087 #define CFG_DP_RXDMA_BUF_RING \ 1088 CFG_INI_UINT("dp_rxdma_buf_ring", \ 1089 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \ 1090 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \ 1091 WLAN_CFG_RXDMA_BUF_RING_SIZE, \ 1092 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring") 1093 1094 #define CFG_DP_RXDMA_REFILL_RING \ 1095 CFG_INI_UINT("dp_rxdma_refill_ring", \ 1096 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \ 1097 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \ 1098 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \ 1099 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring") 1100 1101 #define CFG_DP_RXDMA_REFILL_LT_DISABLE \ 1102 CFG_INI_BOOL("dp_disable_rx_buf_low_threshold", false, \ 1103 "Disable Low threshold interrupts for Rx Refill ring") 1104 1105 #define CFG_DP_TX_DESC_LIMIT_0 \ 1106 CFG_INI_UINT("dp_tx_desc_limit_0", \ 1107 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \ 1108 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \ 1109 WLAN_CFG_TX_DESC_LIMIT_0, \ 1110 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0") 1111 1112 #define CFG_DP_TX_DESC_LIMIT_1 \ 1113 CFG_INI_UINT("dp_tx_desc_limit_1", \ 1114 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \ 1115 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \ 1116 WLAN_CFG_TX_DESC_LIMIT_1, \ 1117 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1") 1118 1119 #define CFG_DP_TX_DESC_LIMIT_2 \ 1120 CFG_INI_UINT("dp_tx_desc_limit_2", \ 1121 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \ 1122 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \ 1123 WLAN_CFG_TX_DESC_LIMIT_2, \ 1124 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2") 1125 1126 #define CFG_DP_TX_DEVICE_LIMIT \ 1127 CFG_INI_UINT("dp_tx_device_limit", \ 1128 WLAN_CFG_TX_DEVICE_LIMIT_MIN, \ 1129 WLAN_CFG_TX_DEVICE_LIMIT_MAX, \ 1130 WLAN_CFG_TX_DEVICE_LIMIT, \ 1131 CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit") 1132 1133 #define CFG_DP_TX_SW_INTERNODE_QUEUE \ 1134 CFG_INI_UINT("dp_tx_sw_internode_queue", \ 1135 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \ 1136 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \ 1137 WLAN_CFG_TX_SW_INTERNODE_QUEUE, \ 1138 CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue") 1139 1140 #define CFG_DP_RXDMA_MONITOR_BUF_RING \ 1141 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \ 1142 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \ 1143 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \ 1144 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \ 1145 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring") 1146 1147 #define CFG_DP_TX_MONITOR_BUF_RING \ 1148 CFG_INI_UINT("dp_tx_monitor_buf_ring", \ 1149 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN, \ 1150 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX, \ 1151 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE, \ 1152 CFG_VALUE_OR_DEFAULT, "DP TX monitor buffer ring") 1153 1154 #define CFG_DP_RXDMA_MONITOR_DST_RING \ 1155 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \ 1156 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \ 1157 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \ 1158 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \ 1159 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 1160 1161 #define CFG_DP_TX_MONITOR_DST_RING \ 1162 CFG_INI_UINT("dp_tx_monitor_dst_ring", \ 1163 WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN, \ 1164 WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX, \ 1165 WLAN_CFG_TX_MONITOR_DST_RING_SIZE, \ 1166 CFG_VALUE_OR_DEFAULT, "DP TX monitor destination ring") 1167 1168 #define CFG_DP_RXDMA_MONITOR_STATUS_RING \ 1169 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \ 1170 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \ 1171 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \ 1172 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \ 1173 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring") 1174 1175 #define CFG_DP_RXDMA_MONITOR_DESC_RING \ 1176 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \ 1177 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \ 1178 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \ 1179 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \ 1180 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 1181 1182 #define CFG_DP_RXDMA_ERR_DST_RING \ 1183 CFG_INI_UINT("dp_rxdma_err_dst_ring", \ 1184 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \ 1185 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \ 1186 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \ 1187 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring") 1188 1189 #define CFG_DP_PER_PKT_LOGGING \ 1190 CFG_INI_UINT("enable_verbose_debug", \ 1191 0, 0xffff, 0, \ 1192 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging") 1193 1194 #define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \ 1195 CFG_INI_UINT("TxFlowStartQueueOffset", \ 1196 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \ 1197 CFG_VALUE_OR_DEFAULT, "Start queue offset") 1198 1199 #define CFG_DP_TX_FLOW_STOP_QUEUE_TH \ 1200 CFG_INI_UINT("TxFlowStopQueueThreshold", \ 1201 0, 50, 15, \ 1202 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold") 1203 1204 #define CFG_DP_IPA_UC_TX_BUF_SIZE \ 1205 CFG_INI_UINT("IpaUcTxBufSize", \ 1206 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \ 1207 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size") 1208 1209 #define CFG_DP_IPA_UC_TX_PARTITION_BASE \ 1210 CFG_INI_UINT("IpaUcTxPartitionBase", \ 1211 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \ 1212 CFG_VALUE_OR_DEFAULT, "IPA tx partition base") 1213 1214 #define CFG_DP_IPA_UC_RX_IND_RING_COUNT \ 1215 CFG_INI_UINT("IpaUcRxIndRingCount", \ 1216 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \ 1217 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count") 1218 1219 #define CFG_DP_AP_STA_SECURITY_SEPERATION \ 1220 CFG_INI_BOOL("gDisableIntraBssFwd", \ 1221 false, "Disable intrs BSS Rx packets") 1222 1223 #define CFG_DP_ENABLE_DATA_STALL_DETECTION \ 1224 CFG_INI_UINT("gEnableDataStallDetection", \ 1225 0, 0xFFFFFFFF, 0x1, \ 1226 CFG_VALUE_OR_DEFAULT, "Enable/Disable Data stall detection") 1227 1228 #define CFG_DP_RX_SW_DESC_WEIGHT \ 1229 CFG_INI_UINT("dp_rx_sw_desc_weight", \ 1230 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN, \ 1231 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX, \ 1232 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE, \ 1233 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC weight") 1234 1235 #define CFG_DP_RX_SW_DESC_NUM \ 1236 CFG_INI_UINT("dp_rx_sw_desc_num", \ 1237 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN, \ 1238 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX, \ 1239 WLAN_CFG_RX_SW_DESC_NUM_SIZE, \ 1240 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC num") 1241 1242 #define CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE \ 1243 CFG_INI_UINT("dp_rx_flow_search_table_size", \ 1244 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN, \ 1245 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX, \ 1246 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT, \ 1247 CFG_VALUE_OR_DEFAULT, \ 1248 "DP Rx Flow Search Table Size in number of entries") 1249 1250 #define CFG_DP_RX_FLOW_TAG_ENABLE \ 1251 CFG_INI_BOOL("dp_rx_flow_tag_enable", false, \ 1252 "Enable/Disable DP Rx Flow Tag") 1253 1254 #define CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV \ 1255 CFG_INI_BOOL("dp_rx_per_pdev_flow_search", false, \ 1256 "DP Rx Flow Search Table Is Per PDev") 1257 1258 #define CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE \ 1259 CFG_INI_BOOL("dp_rx_monitor_protocol_flow_tag_enable", true, \ 1260 "Enable/Disable Rx Protocol & Flow tags in Monitor mode") 1261 1262 #define CFG_DP_TX_PER_PKT_VDEV_ID_CHECK \ 1263 CFG_INI_BOOL("dp_tx_allow_per_pkt_vdev_id_check", false, \ 1264 "Enable/Disable tx Per Pkt vdev id check") 1265 1266 #define CFG_DP_HANDLE_INVALID_DECAP_TYPE_DISABLE \ 1267 CFG_INI_BOOL("dp_handle_invalid_decap_type_disable", false, \ 1268 "Enable/Disable DP TLV out of order WAR") 1269 1270 /* 1271 * <ini> 1272 * dp_rx_fisa_enable - Control Rx datapath FISA 1273 * @Min: 0 1274 * @Max: 1 1275 * @Default: 1 1276 * 1277 * This ini is used to enable DP Rx FISA feature 1278 * 1279 * Related: dp_rx_flow_search_table_size 1280 * 1281 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1282 * 1283 * Usage: Internal 1284 * 1285 * </ini> 1286 */ 1287 #define CFG_DP_RX_FISA_ENABLE \ 1288 CFG_INI_BOOL("dp_rx_fisa_enable", true, \ 1289 "Enable/Disable DP Rx FISA") 1290 1291 /* 1292 * <ini> 1293 * dp_rx_fisa_lru_del_enable - Control Rx datapath FISA 1294 * @Min: 0 1295 * @Max: 1 1296 * @Default: 1 1297 * 1298 * This ini is used to enable DP Rx FISA lru deletion feature 1299 * 1300 * Related: dp_rx_fisa_enable 1301 * 1302 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1303 * 1304 * Usage: Internal 1305 * 1306 * </ini> 1307 */ 1308 #define CFG_DP_RX_FISA_LRU_DEL_ENABLE \ 1309 CFG_INI_BOOL("dp_rx_fisa_lru_del_enable", true, \ 1310 "Enable/Disable DP Rx FISA LRU deletion") 1311 1312 #define CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD \ 1313 CFG_INI_UINT("mon_drop_thresh", \ 1314 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN, \ 1315 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX, \ 1316 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE, \ 1317 CFG_VALUE_OR_DEFAULT, "RXDMA monitor rx drop threshold") 1318 1319 #define CFG_DP_PKTLOG_BUFFER_SIZE \ 1320 CFG_INI_UINT("PktlogBufSize", \ 1321 WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE, \ 1322 WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE, \ 1323 WLAN_CFG_PKTLOG_BUFFER_SIZE, \ 1324 CFG_VALUE_OR_DEFAULT, "Packet Log buffer size") 1325 1326 #define CFG_DP_FULL_MON_MODE \ 1327 CFG_INI_BOOL("full_mon_mode", \ 1328 false, "Full Monitor mode support") 1329 1330 #define CFG_DP_REO_RINGS_MAP \ 1331 CFG_INI_UINT("dp_reo_rings_map", \ 1332 WLAN_CFG_NUM_REO_RINGS_MAP_MIN, \ 1333 WLAN_CFG_NUM_REO_RINGS_MAP_MAX, \ 1334 WLAN_CFG_NUM_REO_RINGS_MAP, \ 1335 CFG_VALUE_OR_DEFAULT, "REO Destination Rings Mapping") 1336 1337 #define CFG_DP_RX_RADIO_0_DEFAULT_REO \ 1338 CFG_INI_UINT("dp_rx_radio0_default_reo", \ 1339 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1340 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1341 WLAN_CFG_RADIO_0_DEFAULT_REO, \ 1342 CFG_VALUE_OR_DEFAULT, "Radio0 to REO destination default mapping") 1343 1344 #define CFG_DP_RX_RADIO_1_DEFAULT_REO \ 1345 CFG_INI_UINT("dp_rx_radio1_default_reo", \ 1346 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1347 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1348 WLAN_CFG_RADIO_1_DEFAULT_REO, \ 1349 CFG_VALUE_OR_DEFAULT, "Radio1 to REO destination default mapping") 1350 1351 #define CFG_DP_RX_RADIO_2_DEFAULT_REO \ 1352 CFG_INI_UINT("dp_rx_radio2_default_reo", \ 1353 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1354 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1355 WLAN_CFG_RADIO_2_DEFAULT_REO, \ 1356 CFG_VALUE_OR_DEFAULT, "Radio2 to REO destination default mapping") 1357 1358 #define CFG_DP_PEER_EXT_STATS \ 1359 CFG_INI_BOOL("peer_ext_stats", \ 1360 false, "Peer extended stats") 1361 1362 #define CFG_DP_PEER_JITTER_STATS \ 1363 CFG_INI_BOOL("peer_jitter_stats", \ 1364 false, "Peer Jitter stats") 1365 1366 #define CFG_DP_NAPI_SCALE_FACTOR \ 1367 CFG_INI_UINT("dp_napi_scale_factor", \ 1368 WLAN_CFG_DP_NAPI_SCALE_FACTOR_MIN, \ 1369 WLAN_CFG_DP_NAPI_SCALE_FACTOR_MAX, \ 1370 WLAN_CFG_DP_NAPI_SCALE_FACTOR, \ 1371 CFG_VALUE_OR_DEFAULT, "NAPI scale factor for DP") 1372 1373 /* 1374 * <ini> 1375 * legacy_mode_csum_disable - Disable csum offload for legacy 802.11abg modes 1376 * @Min: 0 1377 * @Max: 1 1378 * @Default: Default value indicating if checksum should be disabled for 1379 * legacy WLAN modes 1380 * 1381 * This ini is used to disable HW checksum offload capability for legacy 1382 * connections 1383 * 1384 * Related: gEnableIpTcpUdpChecksumOffload should be enabled 1385 * 1386 * Usage: Internal 1387 * 1388 * </ini> 1389 */ 1390 #ifndef DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1391 #define DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1 1392 #endif 1393 1394 #define CFG_DP_LEGACY_MODE_CSUM_DISABLE \ 1395 CFG_INI_BOOL("legacy_mode_csum_disable", \ 1396 DP_LEGACY_MODE_CSM_DEFAULT_DISABLE, \ 1397 "Enable/Disable legacy mode checksum") 1398 1399 #define CFG_DP_RX_BUFF_POOL_ENABLE \ 1400 CFG_INI_BOOL("dp_rx_buff_prealloc_pool", false, \ 1401 "Enable/Disable DP RX emergency buffer pool support") 1402 1403 #define CFG_DP_RX_REFILL_BUFF_POOL_ENABLE \ 1404 CFG_INI_BOOL("dp_rx_refill_buff_pool", false, \ 1405 "Enable/Disable DP RX refill buffer pool support") 1406 1407 #define CFG_DP_POLL_MODE_ENABLE \ 1408 CFG_INI_BOOL("dp_poll_mode_enable", false, \ 1409 "Enable/Disable Polling mode for data path") 1410 1411 #define CFG_DP_RX_FST_IN_CMEM \ 1412 CFG_INI_BOOL("dp_rx_fst_in_cmem", false, \ 1413 "Enable/Disable flow search table in CMEM") 1414 /* 1415 * <ini> 1416 * gEnableSWLM - Control DP Software latency manager 1417 * @Min: 0 1418 * @Max: 1 1419 * @Default: 0 1420 * 1421 * This ini is used to enable DP Software latency Manager 1422 * 1423 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1424 * 1425 * Usage: Internal 1426 * 1427 * </ini> 1428 */ 1429 #define CFG_DP_SWLM_ENABLE \ 1430 CFG_INI_BOOL("gEnableSWLM", false, \ 1431 "Enable/Disable DP SWLM") 1432 /* 1433 * <ini> 1434 * wow_check_rx_pending_enable - control to check RX frames pending in Wow 1435 * @Min: 0 1436 * @Max: 1 1437 * @Default: 0 1438 * 1439 * This ini is used to control DP Software to perform RX pending check 1440 * before entering WoW mode 1441 * 1442 * Usage: Internal 1443 * 1444 * </ini> 1445 */ 1446 #define CFG_DP_WOW_CHECK_RX_PENDING \ 1447 CFG_INI_BOOL("wow_check_rx_pending_enable", \ 1448 false, \ 1449 "enable rx frame pending check in WoW mode") 1450 #define CFG_DP_DELAY_MON_REPLENISH \ 1451 CFG_INI_BOOL("delay_mon_replenish", \ 1452 true, "Delay Monitor Replenish") 1453 1454 #ifdef QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT 1455 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN 500 1456 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX 2000 1457 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER 500 1458 1459 #define CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG \ 1460 CFG_INI_BOOL("vdev_stats_hw_offload_config", \ 1461 false, "Offload vdev stats to HW") 1462 #define CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER \ 1463 CFG_INI_UINT("vdev_stats_hw_offload_timer", \ 1464 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN, \ 1465 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX, \ 1466 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER, \ 1467 CFG_VALUE_OR_DEFAULT, \ 1468 "vdev stats hw offload timer duration") 1469 #define CFG_DP_VDEV_STATS_HW_OFFLOAD \ 1470 CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG) \ 1471 CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER) 1472 #else 1473 #define CFG_DP_VDEV_STATS_HW_OFFLOAD 1474 #endif 1475 1476 /* 1477 * <ini> 1478 * ghw_cc_enable - enable HW cookie conversion by register 1479 * @Min: 0 1480 * @Max: 1 1481 * @Default: 1 1482 * 1483 * This ini is used to control HW based 20 bits cookie to 64 bits 1484 * Desc virtual address conversion 1485 * 1486 * Usage: Internal 1487 * 1488 * </ini> 1489 */ 1490 #define CFG_DP_HW_CC_ENABLE \ 1491 CFG_INI_BOOL("ghw_cc_enable", \ 1492 true, "Enable/Disable HW cookie conversion") 1493 1494 #ifdef IPA_OFFLOAD 1495 /* 1496 * <ini> 1497 * dp_ipa_tx_ring_size - Set tcl ring size for IPA 1498 * @Min: 1024 1499 * @Max: 8096 1500 * @Default: 1024 1501 * 1502 * This ini sets the tcl ring size for IPA 1503 * 1504 * Related: N/A 1505 * 1506 * Supported Feature: IPA 1507 * 1508 * Usage: Internal 1509 * 1510 * </ini> 1511 */ 1512 #define CFG_DP_IPA_TX_RING_SIZE \ 1513 CFG_INI_UINT("dp_ipa_tx_ring_size", \ 1514 WLAN_CFG_IPA_TX_RING_SIZE_MIN, \ 1515 WLAN_CFG_IPA_TX_RING_SIZE_MAX, \ 1516 WLAN_CFG_IPA_TX_RING_SIZE, \ 1517 CFG_VALUE_OR_DEFAULT, "IPA TCL ring size") 1518 1519 /* 1520 * <ini> 1521 * dp_ipa_tx_comp_ring_size - Set tx comp ring size for IPA 1522 * @Min: 1024 1523 * @Max: 8096 1524 * @Default: 1024 1525 * 1526 * This ini sets the tx comp ring size for IPA 1527 * 1528 * Related: N/A 1529 * 1530 * Supported Feature: IPA 1531 * 1532 * Usage: Internal 1533 * 1534 * </ini> 1535 */ 1536 #define CFG_DP_IPA_TX_COMP_RING_SIZE \ 1537 CFG_INI_UINT("dp_ipa_tx_comp_ring_size", \ 1538 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN, \ 1539 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX, \ 1540 WLAN_CFG_IPA_TX_COMP_RING_SIZE, \ 1541 CFG_VALUE_OR_DEFAULT, "IPA tx comp ring size") 1542 1543 #ifdef IPA_WDI3_TX_TWO_PIPES 1544 /* 1545 * <ini> 1546 * dp_ipa_tx_alt_ring_size - Set alt tcl ring size for IPA 1547 * @Min: 1024 1548 * @Max: 8096 1549 * @Default: 1024 1550 * 1551 * This ini sets the alt tcl ring size for IPA 1552 * 1553 * Related: N/A 1554 * 1555 * Supported Feature: IPA 1556 * 1557 * Usage: Internal 1558 * 1559 * </ini> 1560 */ 1561 #define CFG_DP_IPA_TX_ALT_RING_SIZE \ 1562 CFG_INI_UINT("dp_ipa_tx_alt_ring_size", \ 1563 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN, \ 1564 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX, \ 1565 WLAN_CFG_IPA_TX_ALT_RING_SIZE, \ 1566 CFG_VALUE_OR_DEFAULT, \ 1567 "DP IPA TX Alternative Ring Size") 1568 1569 /* 1570 * <ini> 1571 * dp_ipa_tx_alt_comp_ring_size - Set tx alt comp ring size for IPA 1572 * @Min: 1024 1573 * @Max: 8096 1574 * @Default: 1024 1575 * 1576 * This ini sets the tx alt comp ring size for IPA 1577 * 1578 * Related: N/A 1579 * 1580 * Supported Feature: IPA 1581 * 1582 * Usage: Internal 1583 * 1584 * </ini> 1585 */ 1586 #define CFG_DP_IPA_TX_ALT_COMP_RING_SIZE \ 1587 CFG_INI_UINT("dp_ipa_tx_alt_comp_ring_size", \ 1588 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN, \ 1589 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX, \ 1590 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE, \ 1591 CFG_VALUE_OR_DEFAULT, \ 1592 "DP IPA TX Alternative Completion Ring Size") 1593 1594 #define CFG_DP_IPA_TX_ALT_RING_CFG \ 1595 CFG(CFG_DP_IPA_TX_ALT_RING_SIZE) \ 1596 CFG(CFG_DP_IPA_TX_ALT_COMP_RING_SIZE) 1597 1598 #else 1599 #define CFG_DP_IPA_TX_ALT_RING_CFG 1600 #endif 1601 1602 #define CFG_DP_IPA_TX_RING_CFG \ 1603 CFG(CFG_DP_IPA_TX_RING_SIZE) \ 1604 CFG(CFG_DP_IPA_TX_COMP_RING_SIZE) 1605 #else 1606 #define CFG_DP_IPA_TX_RING_CFG 1607 #define CFG_DP_IPA_TX_ALT_RING_CFG 1608 #endif 1609 1610 #ifdef WLAN_SUPPORT_PPEDS 1611 #define WLAN_CFG_NUM_PPEDS_TX_DESC_MIN 16 1612 #define WLAN_CFG_NUM_PPEDS_TX_DESC_MAX 0x8000 1613 #define WLAN_CFG_NUM_PPEDS_TX_DESC 0x8000 1614 1615 #define CFG_DP_PPEDS_TX_DESC \ 1616 CFG_INI_UINT("dp_ppeds_tx_desc", \ 1617 WLAN_CFG_NUM_PPEDS_TX_DESC_MIN, \ 1618 WLAN_CFG_NUM_PPEDS_TX_DESC_MAX, \ 1619 WLAN_CFG_NUM_PPEDS_TX_DESC, \ 1620 CFG_VALUE_OR_DEFAULT, "DP PPEDS Tx Descriptors") 1621 1622 #define CFG_DP_PPE_ENABLE \ 1623 CFG_INI_BOOL("ppe_enable", false, \ 1624 "DP ppe enable flag") 1625 1626 #define CFG_DP_REO2PPE_RING \ 1627 CFG_INI_UINT("dp_reo2ppe_ring", \ 1628 WLAN_CFG_REO2PPE_RING_SIZE_MIN, \ 1629 WLAN_CFG_REO2PPE_RING_SIZE_MAX, \ 1630 WLAN_CFG_REO2PPE_RING_SIZE, \ 1631 CFG_VALUE_OR_DEFAULT, "DP REO2PPE ring") 1632 1633 #define CFG_DP_PPE2TCL_RING \ 1634 CFG_INI_UINT("dp_ppe2tcl_ring", \ 1635 WLAN_CFG_PPE2TCL_RING_SIZE_MIN, \ 1636 WLAN_CFG_PPE2TCL_RING_SIZE_MAX, \ 1637 WLAN_CFG_PPE2TCL_RING_SIZE, \ 1638 CFG_VALUE_OR_DEFAULT, "DP PPE2TCL rings") 1639 1640 #define CFG_DP_PPE_RELEASE_RING \ 1641 CFG_INI_UINT("dp_ppe_release_ring", \ 1642 WLAN_CFG_PPE_RELEASE_RING_SIZE_MIN, \ 1643 WLAN_CFG_PPE_RELEASE_RING_SIZE_MAX, \ 1644 WLAN_CFG_PPE_RELEASE_RING_SIZE, \ 1645 CFG_VALUE_OR_DEFAULT, "DP PPE Release Ring") 1646 1647 #define CFG_DP_PPE_CONFIG \ 1648 CFG(CFG_DP_PPEDS_TX_DESC) \ 1649 CFG(CFG_DP_PPE_ENABLE) \ 1650 CFG(CFG_DP_REO2PPE_RING) \ 1651 CFG(CFG_DP_PPE2TCL_RING) \ 1652 CFG(CFG_DP_PPE_RELEASE_RING) 1653 #else 1654 #define CFG_DP_PPE_CONFIG 1655 #define WLAN_CFG_NUM_PPEDS_TX_DESC_MAX 0 1656 #endif 1657 1658 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 1659 /* 1660 * <ini> 1661 * dp_chip0_rx_ring_map - Set Rx ring map for CHIP 0 1662 * @Min: 0x0 1663 * @Max: 0xFF 1664 * @Default: 0xF 1665 * 1666 * This ini sets Rx ring map for CHIP 0 1667 * 1668 * Usage: Internal 1669 * 1670 * </ini> 1671 */ 1672 #define CFG_DP_MLO_RX_RING_MAP \ 1673 CFG_INI_UINT("dp_mlo_reo_rings_map", \ 1674 WLAN_CFG_MLO_RX_RING_MAP_MIN, \ 1675 WLAN_CFG_MLO_RX_RING_MAP_MAX, \ 1676 WLAN_CFG_MLO_RX_RING_MAP, \ 1677 CFG_VALUE_OR_DEFAULT, "DP MLO Rx ring map") 1678 1679 1680 #define CFG_DP_MLO_CONFIG \ 1681 CFG(CFG_DP_MLO_RX_RING_MAP) 1682 #else 1683 #define CFG_DP_MLO_CONFIG 1684 #endif 1685 1686 /* 1687 * <ini> 1688 * dp_mpdu_retry_threshold_1 - threshold to increment mpdu success with retries 1689 * @Min: 0 1690 * @Max: 255 1691 * @Default: 0 1692 * 1693 * This ini entry is used to set first threshold to increment the value of 1694 * mpdu_success_with_retries 1695 * 1696 * Usage: Internal 1697 * 1698 * </ini> 1699 */ 1700 #define CFG_DP_MPDU_RETRY_THRESHOLD_1 \ 1701 CFG_INI_UINT("dp_mpdu_retry_threshold_1", \ 1702 CFG_DP_MPDU_RETRY_THRESHOLD_MIN, \ 1703 CFG_DP_MPDU_RETRY_THRESHOLD_MAX, \ 1704 CFG_DP_MPDU_RETRY_THRESHOLD, \ 1705 CFG_VALUE_OR_DEFAULT, "DP mpdu retry threshold 1") 1706 1707 /* 1708 * <ini> 1709 * dp_mpdu_retry_threshold_2 - threshold to increment mpdu success with retries 1710 * @Min: 0 1711 * @Max: 255 1712 * @Default: 0 1713 * 1714 * This ini entry is used to set second threshold to increment the value of 1715 * mpdu_success_with_retries 1716 * 1717 * Usage: Internal 1718 * 1719 * </ini> 1720 */ 1721 #define CFG_DP_MPDU_RETRY_THRESHOLD_2 \ 1722 CFG_INI_UINT("dp_mpdu_retry_threshold_2", \ 1723 CFG_DP_MPDU_RETRY_THRESHOLD_MIN, \ 1724 CFG_DP_MPDU_RETRY_THRESHOLD_MAX, \ 1725 CFG_DP_MPDU_RETRY_THRESHOLD, \ 1726 CFG_VALUE_OR_DEFAULT, "DP mpdu retry threshold 2") 1727 1728 #ifdef QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES 1729 /* Macro enabling support marking of notify frames by host */ 1730 #define DP_MARK_NOTIFY_FRAME_SUPPORT 1 1731 #else 1732 #define DP_MARK_NOTIFY_FRAME_SUPPORT 0 1733 #endif /* QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES */ 1734 1735 /* 1736 * <ini> 1737 * Host DP AST entries database - Enable/Disable 1738 * 1739 * @Default: 0 1740 * 1741 * This ini enables/disables AST entries database on host 1742 * 1743 * Usage: Internal 1744 * 1745 * </ini> 1746 */ 1747 #define CFG_DP_HOST_AST_DB_ENABLE \ 1748 CFG_INI_BOOL("host_ast_db_enable", false, \ 1749 "Host AST entries database Enable/Disable") 1750 1751 #define CFG_DP \ 1752 CFG(CFG_DP_HTT_PACKET_TYPE) \ 1753 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \ 1754 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \ 1755 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \ 1756 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \ 1757 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \ 1758 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \ 1759 CFG(CFG_DP_MAX_ALLOC_SIZE) \ 1760 CFG(CFG_DP_MAX_CLIENTS) \ 1761 CFG(CFG_DP_MAX_PEER_ID) \ 1762 CFG(CFG_DP_REO_DEST_RINGS) \ 1763 CFG(CFG_DP_TX_COMP_RINGS) \ 1764 CFG(CFG_DP_TCL_DATA_RINGS) \ 1765 CFG(CFG_DP_NSS_REO_DEST_RINGS) \ 1766 CFG(CFG_DP_NSS_TCL_DATA_RINGS) \ 1767 CFG(CFG_DP_TX_DESC) \ 1768 CFG(CFG_DP_TX_EXT_DESC) \ 1769 CFG(CFG_DP_TX_EXT_DESC_POOLS) \ 1770 CFG(CFG_DP_PDEV_RX_RING) \ 1771 CFG(CFG_DP_PDEV_TX_RING) \ 1772 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \ 1773 CFG(CFG_DP_TX_COMPL_RING_SIZE) \ 1774 CFG(CFG_DP_TX_RING_SIZE) \ 1775 CFG(CFG_DP_NSS_COMP_RING_SIZE) \ 1776 CFG(CFG_DP_PDEV_LMAC_RING) \ 1777 CFG(CFG_DP_TIME_CONTROL_BP) \ 1778 CFG(CFG_DP_BASE_HW_MAC_ID) \ 1779 CFG(CFG_DP_RX_HASH) \ 1780 CFG(CFG_DP_TSO) \ 1781 CFG(CFG_DP_LRO) \ 1782 CFG(CFG_DP_SG) \ 1783 CFG(CFG_DP_GRO) \ 1784 CFG(CFG_DP_TC_INGRESS_PRIO) \ 1785 CFG(CFG_DP_OL_TX_CSUM) \ 1786 CFG(CFG_DP_OL_RX_CSUM) \ 1787 CFG(CFG_DP_RAWMODE) \ 1788 CFG(CFG_DP_PEER_FLOW_CTRL) \ 1789 CFG(CFG_DP_NAPI) \ 1790 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \ 1791 CFG(CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD) \ 1792 CFG(CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD) \ 1793 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \ 1794 CFG(CFG_DP_WBM_RELEASE_RING) \ 1795 CFG(CFG_DP_TCL_CMD_CREDIT_RING) \ 1796 CFG(CFG_DP_TCL_STATUS_RING) \ 1797 CFG(CFG_DP_REO_REINJECT_RING) \ 1798 CFG(CFG_DP_RX_RELEASE_RING) \ 1799 CFG(CFG_DP_REO_EXCEPTION_RING) \ 1800 CFG(CFG_DP_RX_DESTINATION_RING) \ 1801 CFG(CFG_DP_REO_CMD_RING) \ 1802 CFG(CFG_DP_REO_STATUS_RING) \ 1803 CFG(CFG_DP_RXDMA_BUF_RING) \ 1804 CFG(CFG_DP_RXDMA_REFILL_RING) \ 1805 CFG(CFG_DP_RXDMA_REFILL_LT_DISABLE) \ 1806 CFG(CFG_DP_TX_DESC_LIMIT_0) \ 1807 CFG(CFG_DP_TX_DESC_LIMIT_1) \ 1808 CFG(CFG_DP_TX_DESC_LIMIT_2) \ 1809 CFG(CFG_DP_TX_DEVICE_LIMIT) \ 1810 CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \ 1811 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \ 1812 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \ 1813 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \ 1814 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \ 1815 CFG(CFG_DP_RXDMA_ERR_DST_RING) \ 1816 CFG(CFG_DP_PER_PKT_LOGGING) \ 1817 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \ 1818 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \ 1819 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \ 1820 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \ 1821 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \ 1822 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \ 1823 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) \ 1824 CFG(CFG_DP_RX_SW_DESC_WEIGHT) \ 1825 CFG(CFG_DP_RX_SW_DESC_NUM) \ 1826 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE) \ 1827 CFG(CFG_DP_RX_FLOW_TAG_ENABLE) \ 1828 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV) \ 1829 CFG(CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE) \ 1830 CFG(CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD) \ 1831 CFG(CFG_DP_PKTLOG_BUFFER_SIZE) \ 1832 CFG(CFG_DP_RX_FISA_ENABLE) \ 1833 CFG(CFG_DP_RX_FISA_LRU_DEL_ENABLE) \ 1834 CFG(CFG_DP_FULL_MON_MODE) \ 1835 CFG(CFG_DP_REO_RINGS_MAP) \ 1836 CFG(CFG_DP_PEER_EXT_STATS) \ 1837 CFG(CFG_DP_PEER_JITTER_STATS) \ 1838 CFG(CFG_DP_RX_BUFF_POOL_ENABLE) \ 1839 CFG(CFG_DP_RX_REFILL_BUFF_POOL_ENABLE) \ 1840 CFG(CFG_DP_RX_PENDING_HL_THRESHOLD) \ 1841 CFG(CFG_DP_RX_PENDING_LO_THRESHOLD) \ 1842 CFG(CFG_DP_LEGACY_MODE_CSUM_DISABLE) \ 1843 CFG(CFG_DP_POLL_MODE_ENABLE) \ 1844 CFG(CFG_DP_SWLM_ENABLE) \ 1845 CFG(CFG_DP_TX_PER_PKT_VDEV_ID_CHECK) \ 1846 CFG(CFG_DP_RX_FST_IN_CMEM) \ 1847 CFG(CFG_DP_RX_RADIO_0_DEFAULT_REO) \ 1848 CFG(CFG_DP_RX_RADIO_1_DEFAULT_REO) \ 1849 CFG(CFG_DP_RX_RADIO_2_DEFAULT_REO) \ 1850 CFG(CFG_DP_WOW_CHECK_RX_PENDING) \ 1851 CFG(CFG_DP_HW_CC_ENABLE) \ 1852 CFG(CFG_DP_DELAY_MON_REPLENISH) \ 1853 CFG(CFG_DP_TX_MONITOR_BUF_RING) \ 1854 CFG(CFG_DP_TX_MONITOR_DST_RING) \ 1855 CFG(CFG_DP_MPDU_RETRY_THRESHOLD_1) \ 1856 CFG(CFG_DP_MPDU_RETRY_THRESHOLD_2) \ 1857 CFG_DP_IPA_TX_RING_CFG \ 1858 CFG_DP_PPE_CONFIG \ 1859 CFG_DP_IPA_TX_ALT_RING_CFG \ 1860 CFG_DP_MLO_CONFIG \ 1861 CFG_DP_INI_SECTION_PARAMS \ 1862 CFG_DP_VDEV_STATS_HW_OFFLOAD \ 1863 CFG(CFG_DP_TX_CAPT_MAX_MEM_MB) \ 1864 CFG(CFG_DP_NAPI_SCALE_FACTOR) \ 1865 CFG(CFG_DP_HOST_AST_DB_ENABLE) \ 1866 CFG_DP_SAWF_STATS_CONFIG \ 1867 CFG(CFG_DP_HANDLE_INVALID_DECAP_TYPE_DISABLE) 1868 #endif /* _CFG_DP_H_ */ 1869