1 /* 2 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /** 20 * DOC: This file contains definitions of Data Path configuration. 21 */ 22 23 #ifndef _CFG_DP_H_ 24 #define _CFG_DP_H_ 25 26 #include "cfg_define.h" 27 28 #define WLAN_CFG_MAX_CLIENTS 64 29 #define WLAN_CFG_MAX_CLIENTS_MIN 8 30 #define WLAN_CFG_MAX_CLIENTS_MAX 64 31 32 /* Change this to a lower value to enforce scattered idle list mode */ 33 #define WLAN_CFG_MAX_ALLOC_SIZE 0x200000 34 #define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000 35 #define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000 36 37 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 38 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3 39 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3 40 41 #if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \ 42 defined(QCA_LL_PDEV_TX_FLOW_CONTROL) 43 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10 44 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15 45 #else 46 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 47 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 48 #endif 49 50 #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0 51 #define WLAN_CFG_PER_PDEV_TX_RING_MAX 1 52 53 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 54 #define WLAN_CFG_PER_PDEV_RX_RING 0 55 #define WLAN_CFG_PER_PDEV_LMAC_RING 0 56 #define WLAN_LRO_ENABLE 0 57 #define WLAN_CFG_MAC_PER_TARGET 2 58 #ifdef IPA_OFFLOAD 59 /* Size of TCL TX Ring */ 60 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 61 #define WLAN_CFG_TX_RING_SIZE 2048 62 #else 63 #define WLAN_CFG_TX_RING_SIZE 1024 64 #endif 65 66 #define WLAN_CFG_IPA_TX_RING_SIZE 1024 67 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE 1024 68 69 #define WLAN_CFG_PER_PDEV_TX_RING 0 70 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048 71 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000 72 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024 73 #else 74 #define WLAN_CFG_TX_RING_SIZE 512 75 #define WLAN_CFG_PER_PDEV_TX_RING 1 76 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 77 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 78 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 79 #endif 80 81 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 82 #define WLAN_CFG_TX_COMP_RING_SIZE 4096 83 84 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 85 #define WLAN_CFG_NUM_TX_DESC 4096 86 #define WLAN_CFG_NUM_TX_EXT_DESC 4096 87 #else 88 #define WLAN_CFG_TX_COMP_RING_SIZE 1024 89 90 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 91 #define WLAN_CFG_NUM_TX_DESC 1024 92 #define WLAN_CFG_NUM_TX_EXT_DESC 1024 93 #endif 94 95 /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 96 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1 97 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1 98 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 99 100 /* Interrupt Mitigation - Timer threshold in us */ 101 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8 102 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8 103 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8 104 #endif 105 106 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256 107 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 512 108 109 #define WLAN_CFG_PER_PDEV_RX_RING_MIN 0 110 #define WLAN_CFG_PER_PDEV_RX_RING_MAX 0 111 112 #define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0 113 #define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1 114 115 #define WLAN_CFG_TX_RING_SIZE_MIN 512 116 #define WLAN_CFG_TX_RING_SIZE_MAX 0x80000 117 118 #define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512 119 #define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000 120 121 #define WLAN_CFG_NUM_TX_DESC_MIN 16 122 #define WLAN_CFG_NUM_TX_DESC_MAX 32768 123 124 #define WLAN_CFG_NUM_TX_EXT_DESC_MIN 16 125 #define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000 126 127 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1 128 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256 129 130 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 1 131 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128 132 133 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1 134 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128 135 136 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1 137 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128 138 139 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1 140 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1 141 142 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8 143 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 1000 144 145 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8 146 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500 147 148 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8 149 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000 150 151 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8 152 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 512 153 154 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8 155 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500 156 157 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000 158 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000 159 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000 160 161 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 162 163 /* Per vdev pools */ 164 #define WLAN_CFG_NUM_TX_DESC_POOL 3 165 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 166 167 #else /* QCA_LL_TX_FLOW_CONTROL_V2 */ 168 169 #ifdef TX_PER_PDEV_DESC_POOL 170 #define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT 171 #define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT 172 173 #else /* TX_PER_PDEV_DESC_POOL */ 174 175 #define WLAN_CFG_NUM_TX_DESC_POOL 3 176 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 177 178 #endif /* TX_PER_PDEV_DESC_POOL */ 179 #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */ 180 181 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1 182 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4 183 184 #define WLAN_CFG_HTT_PKT_TYPE 2 185 #define WLAN_CFG_HTT_PKT_TYPE_MIN 2 186 #define WLAN_CFG_HTT_PKT_TYPE_MAX 2 187 188 #define WLAN_CFG_MAX_PEER_ID 64 189 #define WLAN_CFG_MAX_PEER_ID_MIN 64 190 #define WLAN_CFG_MAX_PEER_ID_MAX 64 191 192 #define WLAN_CFG_RX_DEFRAG_TIMEOUT 100 193 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100 194 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100 195 196 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 197 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3 198 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3 199 200 #define WLAN_CFG_NUM_REO_DEST_RING 4 201 #define WLAN_CFG_NUM_REO_DEST_RING_MIN 4 202 #define WLAN_CFG_NUM_REO_DEST_RING_MAX 4 203 204 #define WLAN_CFG_WBM_RELEASE_RING_SIZE 1024 205 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64 206 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 1024 207 208 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE 32 209 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN 32 210 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX 32 211 212 #define WLAN_CFG_TCL_STATUS_RING_SIZE 32 213 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32 214 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32 215 216 #if defined(QCA_WIFI_QCA6290) 217 #define WLAN_CFG_REO_DST_RING_SIZE 1024 218 #else 219 #define WLAN_CFG_REO_DST_RING_SIZE 2048 220 #endif 221 222 #define WLAN_CFG_REO_DST_RING_SIZE_MIN 1024 223 #define WLAN_CFG_REO_DST_RING_SIZE_MAX 2048 224 225 #define WLAN_CFG_REO_REINJECT_RING_SIZE 32 226 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32 227 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 32 228 229 #define WLAN_CFG_RX_RELEASE_RING_SIZE 1024 230 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8 231 #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 232 defined(QCA_WIFI_QCA6750) 233 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024 234 #else 235 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 8192 236 #endif 237 238 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE 128 239 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128 240 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 128 241 242 #define WLAN_CFG_REO_CMD_RING_SIZE 128 243 #define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64 244 #define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128 245 246 #define WLAN_CFG_REO_STATUS_RING_SIZE 256 247 #define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128 248 #define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048 249 250 #define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024 251 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024 252 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 1024 253 254 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096 255 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16 256 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 4096 257 258 #define WLAN_CFG_TX_DESC_LIMIT_0 0 259 #define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096 260 #define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768 261 262 #define WLAN_CFG_TX_DESC_LIMIT_1 0 263 #define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096 264 #define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768 265 266 #define WLAN_CFG_TX_DESC_LIMIT_2 0 267 #define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096 268 #define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768 269 270 #define WLAN_CFG_TX_DEVICE_LIMIT 65536 271 #define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384 272 #define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536 273 274 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024 275 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128 276 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024 277 278 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096 279 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16 280 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192 281 282 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048 283 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48 284 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192 285 286 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024 287 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16 288 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192 289 290 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096 291 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096 292 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384 293 294 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024 295 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024 296 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192 297 298 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE 32 299 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN 0 300 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX 256 301 302 /** 303 * Allocate as many RX descriptors as buffers in the SW2RXDMA 304 * ring. This value may need to be tuned later. 305 */ 306 #if defined(QCA_HOST2FW_RXBUF_RING) 307 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 308 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 309 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 1 310 311 /** 312 * For low memory AP cases using 1 will reduce the rx descriptors memory req 313 */ 314 #elif defined(QCA_LOWMEM_CONFIG) || defined(QCA_512M_CONFIG) 315 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 316 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 317 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 318 319 /** 320 * AP use cases need to allocate more RX Descriptors than the number of 321 * entries avaialable in the SW2RXDMA buffer replenish ring. This is to account 322 * for frames sitting in REO queues, HW-HW DMA rings etc. Hence using a 323 * multiplication factor of 3, to allocate three times as many RX descriptors 324 * as RX buffers. 325 */ 326 #else 327 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 3 328 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 329 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 330 #endif //QCA_HOST2FW_RXBUF_RING 331 332 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE 16384 333 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN 1 334 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX 16384 335 336 #define WLAN_CFG_PKTLOG_BUFFER_SIZE 10 337 #define WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE 1 338 #define WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE 10 339 340 /* DP INI Declerations */ 341 #define CFG_DP_HTT_PACKET_TYPE \ 342 CFG_INI_UINT("dp_htt_packet_type", \ 343 WLAN_CFG_HTT_PKT_TYPE_MIN, \ 344 WLAN_CFG_HTT_PKT_TYPE_MAX, \ 345 WLAN_CFG_HTT_PKT_TYPE, \ 346 CFG_VALUE_OR_DEFAULT, "DP HTT packet type") 347 348 #define CFG_DP_INT_BATCH_THRESHOLD_OTHER \ 349 CFG_INI_UINT("dp_int_batch_threshold_other", \ 350 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \ 351 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \ 352 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \ 353 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other") 354 355 #define CFG_DP_INT_BATCH_THRESHOLD_RX \ 356 CFG_INI_UINT("dp_int_batch_threshold_rx", \ 357 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \ 358 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \ 359 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \ 360 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx") 361 362 #define CFG_DP_INT_BATCH_THRESHOLD_TX \ 363 CFG_INI_UINT("dp_int_batch_threshold_tx", \ 364 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \ 365 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \ 366 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \ 367 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx") 368 369 #define CFG_DP_INT_TIMER_THRESHOLD_OTHER \ 370 CFG_INI_UINT("dp_int_timer_threshold_other", \ 371 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \ 372 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \ 373 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \ 374 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other") 375 376 #define CFG_DP_INT_TIMER_THRESHOLD_RX \ 377 CFG_INI_UINT("dp_int_timer_threshold_rx", \ 378 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \ 379 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \ 380 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \ 381 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx") 382 383 #define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \ 384 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \ 385 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \ 386 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \ 387 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \ 388 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring") 389 390 #define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \ 391 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \ 392 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \ 393 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \ 394 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \ 395 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring") 396 397 #define CFG_DP_INT_TIMER_THRESHOLD_TX \ 398 CFG_INI_UINT("dp_int_timer_threshold_tx", \ 399 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \ 400 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \ 401 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \ 402 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx") 403 404 #define CFG_DP_MAX_ALLOC_SIZE \ 405 CFG_INI_UINT("dp_max_alloc_size", \ 406 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \ 407 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \ 408 WLAN_CFG_MAX_ALLOC_SIZE, \ 409 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size") 410 411 #define CFG_DP_MAX_CLIENTS \ 412 CFG_INI_UINT("dp_max_clients", \ 413 WLAN_CFG_MAX_CLIENTS_MIN, \ 414 WLAN_CFG_MAX_CLIENTS_MAX, \ 415 WLAN_CFG_MAX_CLIENTS, \ 416 CFG_VALUE_OR_DEFAULT, "DP Max Clients") 417 418 #define CFG_DP_MAX_PEER_ID \ 419 CFG_INI_UINT("dp_max_peer_id", \ 420 WLAN_CFG_MAX_PEER_ID_MIN, \ 421 WLAN_CFG_MAX_PEER_ID_MAX, \ 422 WLAN_CFG_MAX_PEER_ID, \ 423 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID") 424 425 #define CFG_DP_REO_DEST_RINGS \ 426 CFG_INI_UINT("dp_reo_dest_rings", \ 427 WLAN_CFG_NUM_REO_DEST_RING_MIN, \ 428 WLAN_CFG_NUM_REO_DEST_RING_MAX, \ 429 WLAN_CFG_NUM_REO_DEST_RING, \ 430 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings") 431 432 #define CFG_DP_TCL_DATA_RINGS \ 433 CFG_INI_UINT("dp_tcl_data_rings", \ 434 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \ 435 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \ 436 WLAN_CFG_NUM_TCL_DATA_RINGS, \ 437 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings") 438 439 #define CFG_DP_TX_DESC \ 440 CFG_INI_UINT("dp_tx_desc", \ 441 WLAN_CFG_NUM_TX_DESC_MIN, \ 442 WLAN_CFG_NUM_TX_DESC_MAX, \ 443 WLAN_CFG_NUM_TX_DESC, \ 444 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors") 445 446 #define CFG_DP_TX_EXT_DESC \ 447 CFG_INI_UINT("dp_tx_ext_desc", \ 448 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \ 449 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \ 450 WLAN_CFG_NUM_TX_EXT_DESC, \ 451 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors") 452 453 #define CFG_DP_TX_EXT_DESC_POOLS \ 454 CFG_INI_UINT("dp_tx_ext_desc_pool", \ 455 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \ 456 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \ 457 WLAN_CFG_NUM_TXEXT_DESC_POOL, \ 458 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool") 459 460 #define CFG_DP_PDEV_RX_RING \ 461 CFG_INI_UINT("dp_pdev_rx_ring", \ 462 WLAN_CFG_PER_PDEV_RX_RING_MIN, \ 463 WLAN_CFG_PER_PDEV_RX_RING_MAX, \ 464 WLAN_CFG_PER_PDEV_RX_RING, \ 465 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring") 466 467 #define CFG_DP_PDEV_TX_RING \ 468 CFG_INI_UINT("dp_pdev_tx_ring", \ 469 WLAN_CFG_PER_PDEV_TX_RING_MIN, \ 470 WLAN_CFG_PER_PDEV_TX_RING_MAX, \ 471 WLAN_CFG_PER_PDEV_TX_RING, \ 472 CFG_VALUE_OR_DEFAULT, \ 473 "DP PDEV Tx Ring") 474 475 #define CFG_DP_RX_DEFRAG_TIMEOUT \ 476 CFG_INI_UINT("dp_rx_defrag_timeout", \ 477 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \ 478 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \ 479 WLAN_CFG_RX_DEFRAG_TIMEOUT, \ 480 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout") 481 482 #define CFG_DP_TX_COMPL_RING_SIZE \ 483 CFG_INI_UINT("dp_tx_compl_ring_size", \ 484 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \ 485 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \ 486 WLAN_CFG_TX_COMP_RING_SIZE, \ 487 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size") 488 489 #define CFG_DP_TX_RING_SIZE \ 490 CFG_INI_UINT("dp_tx_ring_size", \ 491 WLAN_CFG_TX_RING_SIZE_MIN,\ 492 WLAN_CFG_TX_RING_SIZE_MAX,\ 493 WLAN_CFG_TX_RING_SIZE,\ 494 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size") 495 496 #define CFG_DP_NSS_COMP_RING_SIZE \ 497 CFG_INI_UINT("dp_nss_comp_ring_size", \ 498 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \ 499 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \ 500 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \ 501 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size") 502 503 #define CFG_DP_PDEV_LMAC_RING \ 504 CFG_INI_UINT("dp_pdev_lmac_ring", \ 505 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \ 506 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \ 507 WLAN_CFG_PER_PDEV_LMAC_RING, \ 508 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring") 509 510 #define CFG_DP_BASE_HW_MAC_ID \ 511 CFG_INI_UINT("dp_base_hw_macid", \ 512 0, 1, 1, \ 513 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID") 514 515 #define CFG_DP_RX_HASH \ 516 CFG_INI_BOOL("dp_rx_hash", true, \ 517 "DP Rx Hash") 518 519 #define CFG_DP_TSO \ 520 CFG_INI_BOOL("TSOEnable", false, \ 521 "DP TSO Enabled") 522 523 #define CFG_DP_LRO \ 524 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \ 525 "DP LRO Enable") 526 527 #define CFG_DP_SG \ 528 CFG_INI_BOOL("dp_sg_support", false, \ 529 "DP SG Enable") 530 531 #define CFG_DP_GRO \ 532 CFG_INI_BOOL("GROEnable", false, \ 533 "DP GRO Enable") 534 535 #define CFG_DP_OL_TX_CSUM \ 536 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \ 537 "DP tx csum Enable") 538 539 #define CFG_DP_OL_RX_CSUM \ 540 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \ 541 "DP rx csum Enable") 542 543 #define CFG_DP_RAWMODE \ 544 CFG_INI_BOOL("dp_rawmode_support", false, \ 545 "DP rawmode Enable") 546 547 #define CFG_DP_PEER_FLOW_CTRL \ 548 CFG_INI_BOOL("dp_peer_flow_control_support", false, \ 549 "DP peer flow ctrl Enable") 550 551 #define CFG_DP_NAPI \ 552 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \ 553 "DP Napi Enabled") 554 555 /* 556 * <ini> 557 * gEnableNanIpTcpUdpChecksumOffload - Enable checksum offload for NAN mode 558 * @Min: 0 559 * @Max: 1 560 * @Default: 1 561 * 562 * Usage: External 563 * 564 * </ini> 565 */ 566 #define CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD \ 567 CFG_INI_BOOL("gEnableNanIpTcpUdpChecksumOffload", true, \ 568 "DP TCP UDP Checksum Offload for NAN mode") 569 570 /* 571 * <ini> 572 * gEnableIpTcpUdpChecksumOffload - Enable checksum offload 573 * @Min: 0 574 * @Max: 1 575 * @Default: 1 576 * 577 * Usage: External 578 * 579 * </ini> 580 */ 581 #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \ 582 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \ 583 "DP TCP UDP Checksum Offload") 584 585 #define CFG_DP_DEFRAG_TIMEOUT_CHECK \ 586 CFG_INI_BOOL("dp_defrag_timeout_check", true, \ 587 "DP Defrag Timeout Check") 588 589 #define CFG_DP_WBM_RELEASE_RING \ 590 CFG_INI_UINT("dp_wbm_release_ring", \ 591 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \ 592 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \ 593 WLAN_CFG_WBM_RELEASE_RING_SIZE, \ 594 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring") 595 596 #define CFG_DP_TCL_CMD_CREDIT_RING \ 597 CFG_INI_UINT("dp_tcl_cmd_credit_ring", \ 598 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN, \ 599 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX, \ 600 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE, \ 601 CFG_VALUE_OR_DEFAULT, "DP TCL Cmd_Credit ring") 602 603 #define CFG_DP_TCL_STATUS_RING \ 604 CFG_INI_UINT("dp_tcl_status_ring",\ 605 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \ 606 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \ 607 WLAN_CFG_TCL_STATUS_RING_SIZE, \ 608 CFG_VALUE_OR_DEFAULT, "DP TCL status ring") 609 610 #define CFG_DP_REO_REINJECT_RING \ 611 CFG_INI_UINT("dp_reo_reinject_ring", \ 612 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \ 613 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \ 614 WLAN_CFG_REO_REINJECT_RING_SIZE, \ 615 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring") 616 617 #define CFG_DP_RX_RELEASE_RING \ 618 CFG_INI_UINT("dp_rx_release_ring", \ 619 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \ 620 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \ 621 WLAN_CFG_RX_RELEASE_RING_SIZE, \ 622 CFG_VALUE_OR_DEFAULT, "DP Rx release ring") 623 624 #define CFG_DP_REO_EXCEPTION_RING \ 625 CFG_INI_UINT("dp_reo_exception_ring", \ 626 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \ 627 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \ 628 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \ 629 CFG_VALUE_OR_DEFAULT, "DP REO exception ring") 630 631 #define CFG_DP_REO_CMD_RING \ 632 CFG_INI_UINT("dp_reo_cmd_ring", \ 633 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \ 634 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \ 635 WLAN_CFG_REO_CMD_RING_SIZE, \ 636 CFG_VALUE_OR_DEFAULT, "DP REO command ring") 637 638 #define CFG_DP_REO_STATUS_RING \ 639 CFG_INI_UINT("dp_reo_status_ring", \ 640 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \ 641 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \ 642 WLAN_CFG_REO_STATUS_RING_SIZE, \ 643 CFG_VALUE_OR_DEFAULT, "DP REO status ring") 644 645 #define CFG_DP_RXDMA_BUF_RING \ 646 CFG_INI_UINT("dp_rxdma_buf_ring", \ 647 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \ 648 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \ 649 WLAN_CFG_RXDMA_BUF_RING_SIZE, \ 650 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring") 651 652 #define CFG_DP_RXDMA_REFILL_RING \ 653 CFG_INI_UINT("dp_rxdma_refill_ring", \ 654 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \ 655 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \ 656 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \ 657 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring") 658 659 #define CFG_DP_TX_DESC_LIMIT_0 \ 660 CFG_INI_UINT("dp_tx_desc_limit_0", \ 661 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \ 662 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \ 663 WLAN_CFG_TX_DESC_LIMIT_0, \ 664 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0") 665 666 #define CFG_DP_TX_DESC_LIMIT_1 \ 667 CFG_INI_UINT("dp_tx_desc_limit_1", \ 668 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \ 669 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \ 670 WLAN_CFG_TX_DESC_LIMIT_1, \ 671 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1") 672 673 #define CFG_DP_TX_DESC_LIMIT_2 \ 674 CFG_INI_UINT("dp_tx_desc_limit_2", \ 675 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \ 676 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \ 677 WLAN_CFG_TX_DESC_LIMIT_2, \ 678 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2") 679 680 #define CFG_DP_TX_DEVICE_LIMIT \ 681 CFG_INI_UINT("dp_tx_device_limit", \ 682 WLAN_CFG_TX_DEVICE_LIMIT_MIN, \ 683 WLAN_CFG_TX_DEVICE_LIMIT_MAX, \ 684 WLAN_CFG_TX_DEVICE_LIMIT, \ 685 CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit") 686 687 #define CFG_DP_TX_SW_INTERNODE_QUEUE \ 688 CFG_INI_UINT("dp_tx_sw_internode_queue", \ 689 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \ 690 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \ 691 WLAN_CFG_TX_SW_INTERNODE_QUEUE, \ 692 CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue") 693 694 #define CFG_DP_RXDMA_MONITOR_BUF_RING \ 695 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \ 696 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \ 697 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \ 698 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \ 699 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring") 700 701 #define CFG_DP_RXDMA_MONITOR_DST_RING \ 702 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \ 703 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \ 704 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \ 705 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \ 706 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 707 708 #define CFG_DP_RXDMA_MONITOR_STATUS_RING \ 709 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \ 710 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \ 711 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \ 712 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \ 713 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring") 714 715 #define CFG_DP_RXDMA_MONITOR_DESC_RING \ 716 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \ 717 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \ 718 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \ 719 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \ 720 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 721 722 #define CFG_DP_RXDMA_ERR_DST_RING \ 723 CFG_INI_UINT("dp_rxdma_err_dst_ring", \ 724 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \ 725 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \ 726 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \ 727 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring") 728 729 #define CFG_DP_PER_PKT_LOGGING \ 730 CFG_INI_UINT("enable_verbose_debug", \ 731 0, 0xffff, 0, \ 732 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging") 733 734 #define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \ 735 CFG_INI_UINT("TxFlowStartQueueOffset", \ 736 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \ 737 CFG_VALUE_OR_DEFAULT, "Start queue offset") 738 739 #define CFG_DP_TX_FLOW_STOP_QUEUE_TH \ 740 CFG_INI_UINT("TxFlowStopQueueThreshold", \ 741 0, 50, 15, \ 742 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold") 743 744 #define CFG_DP_IPA_UC_TX_BUF_SIZE \ 745 CFG_INI_UINT("IpaUcTxBufSize", \ 746 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \ 747 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size") 748 749 #define CFG_DP_IPA_UC_TX_PARTITION_BASE \ 750 CFG_INI_UINT("IpaUcTxPartitionBase", \ 751 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \ 752 CFG_VALUE_OR_DEFAULT, "IPA tx partition base") 753 754 #define CFG_DP_IPA_UC_RX_IND_RING_COUNT \ 755 CFG_INI_UINT("IpaUcRxIndRingCount", \ 756 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \ 757 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count") 758 759 #define CFG_DP_REORDER_OFFLOAD_SUPPORT \ 760 CFG_INI_UINT("gReorderOffloadSupported", \ 761 0, 1, 1, \ 762 CFG_VALUE_OR_DEFAULT, "Packet reordering offload to firmware") 763 764 #define CFG_DP_AP_STA_SECURITY_SEPERATION \ 765 CFG_INI_BOOL("gDisableIntraBssFwd", \ 766 false, "Disable intrs BSS Rx packets") 767 768 #define CFG_DP_ENABLE_DATA_STALL_DETECTION \ 769 CFG_INI_BOOL("gEnableDataStallDetection", \ 770 true, "Enable/Disable Data stall detection") 771 772 #define CFG_DP_RX_SW_DESC_WEIGHT \ 773 CFG_INI_UINT("dp_rx_sw_desc_weight", \ 774 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN, \ 775 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX, \ 776 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE, \ 777 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC weight") 778 779 #define CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE \ 780 CFG_INI_UINT("dp_rx_flow_search_table_size", \ 781 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN, \ 782 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX, \ 783 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE, \ 784 CFG_VALUE_OR_DEFAULT, \ 785 "DP Rx Flow Search Table Size in number of entries") 786 787 #define CFG_DP_RX_FLOW_TAG_ENABLE \ 788 CFG_INI_BOOL("dp_rx_flow_tag_enable", false, \ 789 "Enable/Disable DP Rx Flow Tag") 790 791 #define CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV \ 792 CFG_INI_BOOL("dp_rx_per_pdev_flow_search", false, \ 793 "DP Rx Flow Search Table Is Per PDev") 794 795 #define CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE \ 796 CFG_INI_BOOL("dp_rx_monitor_protocol_flow_tag_enable", true, \ 797 "Enable/Disable Rx Protocol & Flow tags in Monitor mode") 798 799 /* 800 * <ini> 801 * dp_rx_fisa_enable - Control Rx datapath FISA 802 * @Min: 0 803 * @Max: 1 804 * @Default: 0 805 * 806 * This ini is used to enable DP Rx FISA feature 807 * 808 * Related: dp_rx_flow_search_table_size 809 * 810 * Supported Feature: STA,P2P and SAP IPA disabled terminating 811 * 812 * Usage: Internal/External 813 * 814 * </ini> 815 */ 816 #define CFG_DP_RX_FISA_ENABLE \ 817 CFG_INI_BOOL("dp_rx_fisa_enable", false, \ 818 "Enable/Disable DP Rx FISA") 819 820 #define CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD \ 821 CFG_INI_UINT("mon_drop_thresh", \ 822 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN, \ 823 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX, \ 824 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE, \ 825 CFG_VALUE_OR_DEFAULT, "RXDMA monitor rx drop theshold") 826 827 #define CFG_DP_PKTLOG_BUFFER_SIZE \ 828 CFG_INI_UINT("PktlogBufSize", \ 829 WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE, \ 830 WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE, \ 831 WLAN_CFG_PKTLOG_BUFFER_SIZE, \ 832 CFG_VALUE_OR_DEFAULT, "Packet Log buffer size") 833 834 #define CFG_DP_FULL_MON_MODE \ 835 CFG_INI_BOOL("full_mon_mode", \ 836 false, "Full Monitor mode support") 837 838 #define CFG_DP \ 839 CFG(CFG_DP_HTT_PACKET_TYPE) \ 840 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \ 841 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \ 842 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \ 843 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \ 844 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \ 845 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \ 846 CFG(CFG_DP_MAX_ALLOC_SIZE) \ 847 CFG(CFG_DP_MAX_CLIENTS) \ 848 CFG(CFG_DP_MAX_PEER_ID) \ 849 CFG(CFG_DP_REO_DEST_RINGS) \ 850 CFG(CFG_DP_TCL_DATA_RINGS) \ 851 CFG(CFG_DP_TX_DESC) \ 852 CFG(CFG_DP_TX_EXT_DESC) \ 853 CFG(CFG_DP_TX_EXT_DESC_POOLS) \ 854 CFG(CFG_DP_PDEV_RX_RING) \ 855 CFG(CFG_DP_PDEV_TX_RING) \ 856 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \ 857 CFG(CFG_DP_TX_COMPL_RING_SIZE) \ 858 CFG(CFG_DP_TX_RING_SIZE) \ 859 CFG(CFG_DP_NSS_COMP_RING_SIZE) \ 860 CFG(CFG_DP_PDEV_LMAC_RING) \ 861 CFG(CFG_DP_BASE_HW_MAC_ID) \ 862 CFG(CFG_DP_RX_HASH) \ 863 CFG(CFG_DP_TSO) \ 864 CFG(CFG_DP_LRO) \ 865 CFG(CFG_DP_SG) \ 866 CFG(CFG_DP_GRO) \ 867 CFG(CFG_DP_OL_TX_CSUM) \ 868 CFG(CFG_DP_OL_RX_CSUM) \ 869 CFG(CFG_DP_RAWMODE) \ 870 CFG(CFG_DP_PEER_FLOW_CTRL) \ 871 CFG(CFG_DP_NAPI) \ 872 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \ 873 CFG(CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD) \ 874 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \ 875 CFG(CFG_DP_WBM_RELEASE_RING) \ 876 CFG(CFG_DP_TCL_CMD_CREDIT_RING) \ 877 CFG(CFG_DP_TCL_STATUS_RING) \ 878 CFG(CFG_DP_REO_REINJECT_RING) \ 879 CFG(CFG_DP_RX_RELEASE_RING) \ 880 CFG(CFG_DP_REO_EXCEPTION_RING) \ 881 CFG(CFG_DP_REO_CMD_RING) \ 882 CFG(CFG_DP_REO_STATUS_RING) \ 883 CFG(CFG_DP_RXDMA_BUF_RING) \ 884 CFG(CFG_DP_RXDMA_REFILL_RING) \ 885 CFG(CFG_DP_TX_DESC_LIMIT_0) \ 886 CFG(CFG_DP_TX_DESC_LIMIT_1) \ 887 CFG(CFG_DP_TX_DESC_LIMIT_2) \ 888 CFG(CFG_DP_TX_DEVICE_LIMIT) \ 889 CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \ 890 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \ 891 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \ 892 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \ 893 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \ 894 CFG(CFG_DP_RXDMA_ERR_DST_RING) \ 895 CFG(CFG_DP_PER_PKT_LOGGING) \ 896 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \ 897 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \ 898 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \ 899 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \ 900 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \ 901 CFG(CFG_DP_REORDER_OFFLOAD_SUPPORT) \ 902 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \ 903 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) \ 904 CFG(CFG_DP_RX_SW_DESC_WEIGHT) \ 905 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE) \ 906 CFG(CFG_DP_RX_FLOW_TAG_ENABLE) \ 907 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV) \ 908 CFG(CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE) \ 909 CFG(CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD) \ 910 CFG(CFG_DP_PKTLOG_BUFFER_SIZE) \ 911 CFG(CFG_DP_RX_FISA_ENABLE) \ 912 CFG(CFG_DP_FULL_MON_MODE) 913 914 #endif /* _CFG_DP_H_ */ 915