1 /* 2 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * DOC: This file contains definitions of Data Path configuration. 22 */ 23 24 #ifndef _CFG_DP_H_ 25 #define _CFG_DP_H_ 26 27 #include "cfg_define.h" 28 #include "wlan_init_cfg.h" 29 30 #define WLAN_CFG_MAX_CLIENTS 64 31 #define WLAN_CFG_MAX_CLIENTS_MIN 8 32 #define WLAN_CFG_MAX_CLIENTS_MAX 64 33 34 /* Change this to a lower value to enforce scattered idle list mode */ 35 #define WLAN_CFG_MAX_ALLOC_SIZE 0x200000 36 #define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000 37 #define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000 38 39 #if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \ 40 defined(QCA_LL_PDEV_TX_FLOW_CONTROL) 41 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10 42 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15 43 #else 44 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 45 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 46 #endif 47 48 #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0 49 #define WLAN_CFG_PER_PDEV_TX_RING_MAX 1 50 51 #ifdef IPA_OFFLOAD 52 /* Size of TCL TX Ring */ 53 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 54 #define WLAN_CFG_TX_RING_SIZE 2048 55 #else 56 #define WLAN_CFG_TX_RING_SIZE 1024 57 #endif 58 59 #define WLAN_CFG_IPA_TX_RING_SIZE_MIN 1024 60 #define WLAN_CFG_IPA_TX_RING_SIZE 1024 61 #define WLAN_CFG_IPA_TX_RING_SIZE_MAX 8096 62 63 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN 1024 64 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE 1024 65 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX 8096 66 67 #ifdef IPA_WDI3_TX_TWO_PIPES 68 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN 1024 69 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE 1024 70 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX 8096 71 72 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN 1024 73 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE 1024 74 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX 8096 75 #endif 76 77 #define WLAN_CFG_PER_PDEV_TX_RING 0 78 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048 79 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000 80 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024 81 #else 82 #define WLAN_CFG_TX_RING_SIZE 512 83 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 84 #define WLAN_CFG_PER_PDEV_TX_RING 1 85 #else 86 #define WLAN_CFG_PER_PDEV_TX_RING 0 87 #endif 88 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 89 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 90 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 91 #endif /* IPA_OFFLOAD */ 92 93 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 94 #define WLAN_CFG_PER_PDEV_RX_RING 0 95 #define WLAN_CFG_PER_PDEV_LMAC_RING 0 96 #define WLAN_LRO_ENABLE 0 97 #ifdef QCA_WIFI_QCA6750 98 #define WLAN_CFG_MAC_PER_TARGET 1 99 #else 100 #define WLAN_CFG_MAC_PER_TARGET 2 101 #endif 102 103 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 104 #define WLAN_CFG_TX_COMP_RING_SIZE 4096 105 106 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 107 #define WLAN_CFG_NUM_TX_DESC 4096 108 #define WLAN_CFG_NUM_TX_EXT_DESC 4096 109 #else 110 #define WLAN_CFG_TX_COMP_RING_SIZE 1024 111 112 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 113 #define WLAN_CFG_NUM_TX_DESC 1024 114 #define WLAN_CFG_NUM_TX_EXT_DESC 1024 115 #endif 116 117 /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 118 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1 119 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 120 121 /* Interrupt Mitigation - Timer threshold in us */ 122 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8 123 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8 124 125 #ifdef WLAN_DP_PER_RING_TYPE_CONFIG 126 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX \ 127 WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 128 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX \ 129 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 130 #else 131 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1 132 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8 133 #endif 134 #endif /* WLAN_MAX_PDEVS */ 135 136 #ifdef NBUF_MEMORY_DEBUG 137 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0xFFFF 138 #else 139 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0x1FFFF 140 #endif 141 142 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD \ 143 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 144 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN 0 145 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX 0x200000 146 147 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD \ 148 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 149 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN 100 150 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX 0x200000 151 152 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256 153 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 512 154 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 0 155 156 #define WLAN_CFG_PER_PDEV_RX_RING_MIN 0 157 #define WLAN_CFG_PER_PDEV_RX_RING_MAX 0 158 159 #define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0 160 #define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1 161 162 #define WLAN_CFG_TX_RING_SIZE_MIN 512 163 #define WLAN_CFG_TX_RING_SIZE_MAX 0x80000 164 165 #define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512 166 #define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000 167 168 #define WLAN_CFG_NUM_TX_DESC_MIN 16 169 #define WLAN_CFG_NUM_TX_DESC_MAX 32768 170 171 #define WLAN_CFG_NUM_TX_EXT_DESC_MIN 16 172 #define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000 173 174 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1 175 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256 176 177 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 0 178 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128 179 180 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1 181 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128 182 183 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1 184 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128 185 186 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1 187 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1 188 189 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8 190 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 1000 191 192 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8 193 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500 194 195 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8 196 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000 197 198 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8 199 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 512 200 201 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8 202 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500 203 204 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000 205 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000 206 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000 207 208 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 209 210 /* Per vdev pools */ 211 #define WLAN_CFG_NUM_TX_DESC_POOL 3 212 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 213 214 #else /* QCA_LL_TX_FLOW_CONTROL_V2 */ 215 216 #ifdef TX_PER_PDEV_DESC_POOL 217 #define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT 218 #define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT 219 220 #else /* TX_PER_PDEV_DESC_POOL */ 221 222 #define WLAN_CFG_NUM_TX_DESC_POOL 3 223 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 224 225 #endif /* TX_PER_PDEV_DESC_POOL */ 226 #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */ 227 228 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1 229 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4 230 231 #define WLAN_CFG_HTT_PKT_TYPE 2 232 #define WLAN_CFG_HTT_PKT_TYPE_MIN 2 233 #define WLAN_CFG_HTT_PKT_TYPE_MAX 2 234 235 #define WLAN_CFG_MAX_PEER_ID 64 236 #define WLAN_CFG_MAX_PEER_ID_MIN 64 237 #define WLAN_CFG_MAX_PEER_ID_MAX 64 238 239 #define WLAN_CFG_RX_DEFRAG_TIMEOUT 100 240 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100 241 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100 242 243 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 244 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 1 245 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX MAX_TCL_DATA_RINGS 246 247 #define WLAN_CFG_NUM_TX_COMP_RINGS WLAN_CFG_NUM_TCL_DATA_RINGS 248 #define WLAN_CFG_NUM_TX_COMP_RINGS_MIN WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 249 #define WLAN_CFG_NUM_TX_COMP_RINGS_MAX WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 250 251 #if defined(CONFIG_BERYLLIUM) 252 #define WLAN_CFG_NUM_REO_DEST_RING 8 253 #else 254 #define WLAN_CFG_NUM_REO_DEST_RING 4 255 #endif 256 #define WLAN_CFG_NUM_REO_DEST_RING_MIN 4 257 #define WLAN_CFG_NUM_REO_DEST_RING_MAX MAX_REO_DEST_RINGS 258 259 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS 2 260 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN 1 261 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX 3 262 263 #define WLAN_CFG_NSS_NUM_REO_DEST_RING 2 264 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN 1 265 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX 3 266 267 #define WLAN_CFG_WBM_RELEASE_RING_SIZE 1024 268 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64 269 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 1024 270 271 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE 512 272 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN 32 273 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX 512 274 275 #define WLAN_CFG_TCL_STATUS_RING_SIZE 32 276 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32 277 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32 278 279 #if defined(QCA_WIFI_QCA6290) 280 #define WLAN_CFG_REO_DST_RING_SIZE 1024 281 #else 282 #define WLAN_CFG_REO_DST_RING_SIZE 2048 283 #endif 284 285 #define WLAN_CFG_REO_DST_RING_SIZE_MIN 8 286 #define WLAN_CFG_REO_DST_RING_SIZE_MAX 8192 287 288 #define WLAN_CFG_REO_REINJECT_RING_SIZE 128 289 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32 290 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 128 291 292 #define WLAN_CFG_RX_RELEASE_RING_SIZE 1024 293 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8 294 #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 295 defined(QCA_WIFI_QCA6750) || defined(QCA_WIFI_KIWI) 296 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024 297 #else 298 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 8192 299 #endif 300 301 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE 256 302 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128 303 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 512 304 305 #define WLAN_CFG_REO_CMD_RING_SIZE 128 306 #define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64 307 #define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128 308 309 #define WLAN_CFG_REO_STATUS_RING_SIZE 256 310 #define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128 311 #define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048 312 313 #define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024 314 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024 315 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 316 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 1024 317 #else 318 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 4096 319 #endif 320 321 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096 322 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16 323 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 4096 324 325 #define WLAN_CFG_TX_DESC_LIMIT_0 0 326 #define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096 327 #define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768 328 329 #define WLAN_CFG_TX_DESC_LIMIT_1 0 330 #define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096 331 #define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768 332 333 #define WLAN_CFG_TX_DESC_LIMIT_2 0 334 #define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096 335 #define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768 336 337 #define WLAN_CFG_TX_DEVICE_LIMIT 65536 338 #define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384 339 #define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536 340 341 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024 342 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128 343 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024 344 345 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096 346 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16 347 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192 348 349 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE 8192 350 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN 16 351 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX 8192 352 353 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048 354 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48 355 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192 356 357 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE 2048 358 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN 48 359 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX 4096 360 361 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024 362 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16 363 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192 364 365 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096 366 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096 367 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384 368 369 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024 370 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024 371 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192 372 373 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE 32 374 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN 0 375 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX 256 376 377 /** 378 * Allocate as many RX descriptors as buffers in the SW2RXDMA 379 * ring. This value may need to be tuned later. 380 */ 381 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 382 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 383 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 384 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 1 385 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 386 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 387 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 4096 388 389 /** 390 * For low memory AP cases using 1 will reduce the rx descriptors memory req 391 */ 392 #elif defined(QCA_LOWMEM_CONFIG) || defined(QCA_512M_CONFIG) 393 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 394 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 395 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 396 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 397 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 398 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 12288 399 400 /** 401 * AP use cases need to allocate more RX Descriptors than the number of 402 * entries avaialable in the SW2RXDMA buffer replenish ring. This is to account 403 * for frames sitting in REO queues, HW-HW DMA rings etc. Hence using a 404 * multiplication factor of 3, to allocate three times as many RX descriptors 405 * as RX buffers. 406 */ 407 #else 408 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 3 409 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 410 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 411 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 12288 412 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 4096 413 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 12288 414 #endif 415 416 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE 16384 417 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN 1 418 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX 16384 419 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT 128 420 421 #define WLAN_CFG_PKTLOG_BUFFER_SIZE 10 422 #define WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE 1 423 #define WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE 10 424 425 #ifdef QCA_WIFI_KIWI 426 #define WLAN_CFG_NUM_REO_RINGS_MAP 0x7 427 #else 428 #define WLAN_CFG_NUM_REO_RINGS_MAP 0xF 429 #endif 430 #define WLAN_CFG_NUM_REO_RINGS_MAP_MIN 0x1 431 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xF 432 433 #define WLAN_CFG_RADIO_0_DEFAULT_REO 0x1 434 #define WLAN_CFG_RADIO_1_DEFAULT_REO 0x2 435 #define WLAN_CFG_RADIO_2_DEFAULT_REO 0x3 436 437 #define WLAN_CFG_RADIO_DEFAULT_REO_MIN 0x1 438 #define WLAN_CFG_RADIO_DEFAULT_REO_MAX 0x4 439 440 #define WLAN_CFG_REO2PPE_RING_SIZE 1024 441 #define WLAN_CFG_REO2PPE_RING_SIZE_MIN 64 442 #define WLAN_CFG_REO2PPE_RING_SIZE_MAX 1024 443 444 #define WLAN_CFG_PPE2TCL_RING_SIZE 1024 445 #define WLAN_CFG_PPE2TCL_RING_SIZE_MIN 64 446 #define WLAN_CFG_PPE2TCL_RING_SIZE_MAX 1024 447 448 #define WLAN_CFG_PPE_RELEASE_RING_SIZE 1024 449 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MIN 64 450 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MAX 1024 451 452 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 453 #define WLAN_CFG_MLO_RX_RING_MAP 0xF 454 #define WLAN_CFG_MLO_RX_RING_MAP_MIN 0x0 455 #define WLAN_CFG_MLO_RX_RING_MAP_MAX 0xFF 456 #endif 457 458 #define WLAN_CFG_TX_CAPT_MAX_MEM_MIN 0 459 #define WLAN_CFG_TX_CAPT_MAX_MEM_MAX 512 460 #define WLAN_CFG_TX_CAPT_MAX_MEM_DEFAULT 0 461 462 /* 463 * <ini> 464 * "dp_tx_capt_max_mem_mb"- maximum memory used by Tx capture 465 * @Min: 0 466 * @Max: 512 MB 467 * @Default: 0 (disabled) 468 * 469 * This ini entry is used to set a max limit beyond which frames 470 * are dropped by Tx capture. User needs to set a non-zero value 471 * to enable it. 472 * 473 * Usage: External 474 * 475 * </ini> 476 */ 477 #define CFG_DP_TX_CAPT_MAX_MEM_MB \ 478 CFG_INI_UINT("dp_tx_capt_max_mem_mb", \ 479 WLAN_CFG_TX_CAPT_MAX_MEM_MIN, \ 480 WLAN_CFG_TX_CAPT_MAX_MEM_MAX, \ 481 WLAN_CFG_TX_CAPT_MAX_MEM_DEFAULT, \ 482 CFG_VALUE_OR_DEFAULT, "Max Memory (in MB) used by Tx Capture") 483 484 /* DP INI Declarations */ 485 #define CFG_DP_HTT_PACKET_TYPE \ 486 CFG_INI_UINT("dp_htt_packet_type", \ 487 WLAN_CFG_HTT_PKT_TYPE_MIN, \ 488 WLAN_CFG_HTT_PKT_TYPE_MAX, \ 489 WLAN_CFG_HTT_PKT_TYPE, \ 490 CFG_VALUE_OR_DEFAULT, "DP HTT packet type") 491 492 #define CFG_DP_INT_BATCH_THRESHOLD_OTHER \ 493 CFG_INI_UINT("dp_int_batch_threshold_other", \ 494 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \ 495 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \ 496 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \ 497 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other") 498 499 #define CFG_DP_INT_BATCH_THRESHOLD_RX \ 500 CFG_INI_UINT("dp_int_batch_threshold_rx", \ 501 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \ 502 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \ 503 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \ 504 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx") 505 506 #define CFG_DP_INT_BATCH_THRESHOLD_TX \ 507 CFG_INI_UINT("dp_int_batch_threshold_tx", \ 508 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \ 509 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \ 510 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \ 511 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx") 512 513 #define CFG_DP_INT_TIMER_THRESHOLD_OTHER \ 514 CFG_INI_UINT("dp_int_timer_threshold_other", \ 515 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \ 516 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \ 517 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \ 518 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other") 519 520 #define CFG_DP_INT_TIMER_THRESHOLD_RX \ 521 CFG_INI_UINT("dp_int_timer_threshold_rx", \ 522 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \ 523 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \ 524 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \ 525 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx") 526 527 #define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \ 528 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \ 529 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \ 530 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \ 531 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \ 532 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring") 533 534 #define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \ 535 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \ 536 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \ 537 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \ 538 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \ 539 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring") 540 541 #define CFG_DP_INT_TIMER_THRESHOLD_TX \ 542 CFG_INI_UINT("dp_int_timer_threshold_tx", \ 543 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \ 544 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \ 545 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \ 546 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx") 547 548 #define CFG_DP_MAX_ALLOC_SIZE \ 549 CFG_INI_UINT("dp_max_alloc_size", \ 550 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \ 551 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \ 552 WLAN_CFG_MAX_ALLOC_SIZE, \ 553 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size") 554 555 #define CFG_DP_MAX_CLIENTS \ 556 CFG_INI_UINT("dp_max_clients", \ 557 WLAN_CFG_MAX_CLIENTS_MIN, \ 558 WLAN_CFG_MAX_CLIENTS_MAX, \ 559 WLAN_CFG_MAX_CLIENTS, \ 560 CFG_VALUE_OR_DEFAULT, "DP Max Clients") 561 562 #define CFG_DP_MAX_PEER_ID \ 563 CFG_INI_UINT("dp_max_peer_id", \ 564 WLAN_CFG_MAX_PEER_ID_MIN, \ 565 WLAN_CFG_MAX_PEER_ID_MAX, \ 566 WLAN_CFG_MAX_PEER_ID, \ 567 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID") 568 569 #define CFG_DP_REO_DEST_RINGS \ 570 CFG_INI_UINT("dp_reo_dest_rings", \ 571 WLAN_CFG_NUM_REO_DEST_RING_MIN, \ 572 WLAN_CFG_NUM_REO_DEST_RING_MAX, \ 573 WLAN_CFG_NUM_REO_DEST_RING, \ 574 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings") 575 576 #define CFG_DP_TX_COMP_RINGS \ 577 CFG_INI_UINT("dp_tx_comp_rings", \ 578 WLAN_CFG_NUM_TX_COMP_RINGS_MIN, \ 579 WLAN_CFG_NUM_TX_COMP_RINGS_MAX, \ 580 WLAN_CFG_NUM_TX_COMP_RINGS, \ 581 CFG_VALUE_OR_DEFAULT, "DP Tx Comp Rings") 582 583 #define CFG_DP_TCL_DATA_RINGS \ 584 CFG_INI_UINT("dp_tcl_data_rings", \ 585 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \ 586 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \ 587 WLAN_CFG_NUM_TCL_DATA_RINGS, \ 588 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings") 589 590 #define CFG_DP_NSS_REO_DEST_RINGS \ 591 CFG_INI_UINT("dp_nss_reo_dest_rings", \ 592 WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN, \ 593 WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX, \ 594 WLAN_CFG_NSS_NUM_REO_DEST_RING, \ 595 CFG_VALUE_OR_DEFAULT, "DP NSS REO Destination Rings") 596 597 #define CFG_DP_NSS_TCL_DATA_RINGS \ 598 CFG_INI_UINT("dp_nss_tcl_data_rings", \ 599 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN, \ 600 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX, \ 601 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS, \ 602 CFG_VALUE_OR_DEFAULT, "DP NSS TCL Data Rings") 603 604 #define CFG_DP_TX_DESC \ 605 CFG_INI_UINT("dp_tx_desc", \ 606 WLAN_CFG_NUM_TX_DESC_MIN, \ 607 WLAN_CFG_NUM_TX_DESC_MAX, \ 608 WLAN_CFG_NUM_TX_DESC, \ 609 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors") 610 611 #define CFG_DP_TX_EXT_DESC \ 612 CFG_INI_UINT("dp_tx_ext_desc", \ 613 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \ 614 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \ 615 WLAN_CFG_NUM_TX_EXT_DESC, \ 616 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors") 617 618 #define CFG_DP_TX_EXT_DESC_POOLS \ 619 CFG_INI_UINT("dp_tx_ext_desc_pool", \ 620 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \ 621 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \ 622 WLAN_CFG_NUM_TXEXT_DESC_POOL, \ 623 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool") 624 625 #define CFG_DP_PDEV_RX_RING \ 626 CFG_INI_UINT("dp_pdev_rx_ring", \ 627 WLAN_CFG_PER_PDEV_RX_RING_MIN, \ 628 WLAN_CFG_PER_PDEV_RX_RING_MAX, \ 629 WLAN_CFG_PER_PDEV_RX_RING, \ 630 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring") 631 632 #define CFG_DP_PDEV_TX_RING \ 633 CFG_INI_UINT("dp_pdev_tx_ring", \ 634 WLAN_CFG_PER_PDEV_TX_RING_MIN, \ 635 WLAN_CFG_PER_PDEV_TX_RING_MAX, \ 636 WLAN_CFG_PER_PDEV_TX_RING, \ 637 CFG_VALUE_OR_DEFAULT, \ 638 "DP PDEV Tx Ring") 639 640 #define CFG_DP_RX_DEFRAG_TIMEOUT \ 641 CFG_INI_UINT("dp_rx_defrag_timeout", \ 642 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \ 643 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \ 644 WLAN_CFG_RX_DEFRAG_TIMEOUT, \ 645 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout") 646 647 #define CFG_DP_TX_COMPL_RING_SIZE \ 648 CFG_INI_UINT("dp_tx_compl_ring_size", \ 649 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \ 650 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \ 651 WLAN_CFG_TX_COMP_RING_SIZE, \ 652 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size") 653 654 #define CFG_DP_TX_RING_SIZE \ 655 CFG_INI_UINT("dp_tx_ring_size", \ 656 WLAN_CFG_TX_RING_SIZE_MIN,\ 657 WLAN_CFG_TX_RING_SIZE_MAX,\ 658 WLAN_CFG_TX_RING_SIZE,\ 659 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size") 660 661 #define CFG_DP_NSS_COMP_RING_SIZE \ 662 CFG_INI_UINT("dp_nss_comp_ring_size", \ 663 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \ 664 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \ 665 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \ 666 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size") 667 668 #define CFG_DP_PDEV_LMAC_RING \ 669 CFG_INI_UINT("dp_pdev_lmac_ring", \ 670 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \ 671 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \ 672 WLAN_CFG_PER_PDEV_LMAC_RING, \ 673 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring") 674 /* 675 * <ini> 676 * dp_rx_pending_hl_threshold - High threshold of frame number to start 677 * frame dropping scheme 678 * @Min: 0 679 * @Max: 524288 680 * @Default: 393216 681 * 682 * This ini entry is used to set a high limit threshold to start frame 683 * dropping scheme 684 * 685 * Usage: External 686 * 687 * </ini> 688 */ 689 #define CFG_DP_RX_PENDING_HL_THRESHOLD \ 690 CFG_INI_UINT("dp_rx_pending_hl_threshold", \ 691 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN, \ 692 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX, \ 693 WLAN_CFG_RX_PENDING_HL_THRESHOLD, \ 694 CFG_VALUE_OR_DEFAULT, "DP rx pending hl threshold") 695 696 /* 697 * <ini> 698 * dp_rx_pending_lo_threshold - Low threshold of frame number to stop 699 * frame dropping scheme 700 * @Min: 100 701 * @Max: 524288 702 * @Default: 393216 703 * 704 * This ini entry is used to set a low limit threshold to stop frame 705 * dropping scheme 706 * 707 * Usage: External 708 * 709 * </ini> 710 */ 711 #define CFG_DP_RX_PENDING_LO_THRESHOLD \ 712 CFG_INI_UINT("dp_rx_pending_lo_threshold", \ 713 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN, \ 714 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX, \ 715 WLAN_CFG_RX_PENDING_LO_THRESHOLD, \ 716 CFG_VALUE_OR_DEFAULT, "DP rx pending lo threshold") 717 718 #define CFG_DP_BASE_HW_MAC_ID \ 719 CFG_INI_UINT("dp_base_hw_macid", \ 720 0, 1, 1, \ 721 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID") 722 723 #define CFG_DP_RX_HASH \ 724 CFG_INI_BOOL("dp_rx_hash", true, \ 725 "DP Rx Hash") 726 727 #define CFG_DP_TSO \ 728 CFG_INI_BOOL("TSOEnable", false, \ 729 "DP TSO Enabled") 730 731 #define CFG_DP_LRO \ 732 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \ 733 "DP LRO Enable") 734 735 #ifdef WLAN_USE_CONFIG_PARAMS 736 /* 737 * <ini> 738 * dp_tx_desc_use_512p - Use 512M tx descriptor size 739 * @Min: 0 740 * @Max: 1 741 * @Default: 0 742 * 743 * This ini entry is used as flag to use 512M tx descriptor size or not 744 * 745 * Usage: Internal 746 * 747 * </ini> 748 */ 749 #define CFG_DP_TX_DESC_512P \ 750 CFG_INI_BOOL("dp_tx_desc_use_512p", false, \ 751 "DP TX DESC PINE SPECIFIC") 752 753 /* 754 * <ini> 755 * dp_nss_3radio_ring - Use 3 Radio NSS comp ring size 756 * @Min: 0 757 * @Max: 1 758 * @Default: 0 759 * 760 * This ini entry is used as flag to use 3 Radio NSS com ring size or not 761 * 762 * Usage: Internal 763 * 764 * </ini> 765 */ 766 #define CFG_DP_NSS_3RADIO_RING \ 767 CFG_INI_BOOL("dp_nss_3radio_ring", false, \ 768 "DP NSS 3 RADIO RING SIZE") 769 770 /* 771 * <ini> 772 * dp_mon_ring_per_512M - Update monitor status ring as 512M profile 773 * @Min: 0 774 * @Max: 1 775 * @Default: 0 776 * 777 * This ini entry is used as flag to update monitor status ring as 512M profile 778 * 779 * Usage: Internal 780 * 781 * </ini> 782 */ 783 #define CFG_DP_MON_STATUS_512M \ 784 CFG_INI_BOOL("dp_mon_ring_per_512M", false, \ 785 "DP MON STATUS RING SIZE PER 512M PROFILE") 786 787 /* 788 * <ini> 789 * dp_mon_2chain_ring - Reduce monitor rings size as for 2 Chains case 790 * @Min: 0 791 * @Max: 1 792 * @Default: 0 793 * 794 * This ini entry is used as flag to reduce monitor rings size as those used 795 * in case of 2 Tx/RxChains 796 * 797 * Usage: Internal 798 * 799 * </ini> 800 */ 801 #define CFG_DP_MON_2CHAIN_RING \ 802 CFG_INI_BOOL("dp_mon_2chain_ring", false, \ 803 "DP MON UPDATE RINGS FOR 2CHAIN") 804 805 /* 806 * <ini> 807 * dp_mon_4chain_ring - Update monitor rings size for 4 Chains case 808 * @Min: 0 809 * @Max: 1 810 * @Default: 0 811 * 812 * This ini entry is used as flag to reduce monitor rings size as those used 813 * in case of 4 Tx/RxChains 814 * 815 * Usage: Internal 816 * 817 * </ini> 818 */ 819 #define CFG_DP_MON_4CHAIN_RING \ 820 CFG_INI_BOOL("dp_mon_4chain_ring", false, \ 821 "DP MON UPDATE RINGS FOR 4CHAIN") 822 823 /* 824 * <ini> 825 * dp_4radip_rdp_reo - Update RDP REO map based on 4 radio config 826 * @Min: 0 827 * @Max: 1 828 * @Default: 0 829 * 830 * This ini entry is used as flag to update RDP reo map based on 4 Radio config 831 * 832 * Usage: Internal 833 * 834 * </ini> 835 */ 836 #define CFG_DP_4RADIO_RDP_REO \ 837 CFG_INI_BOOL("dp_nss_4radio_rdp_reo", \ 838 false, "Update REO destination mapping for 4radio") 839 840 #define CFG_DP_INI_SECTION_PARAMS \ 841 CFG(CFG_DP_NSS_3RADIO_RING) \ 842 CFG(CFG_DP_TX_DESC_512P) \ 843 CFG(CFG_DP_MON_STATUS_512M) \ 844 CFG(CFG_DP_MON_2CHAIN_RING) \ 845 CFG(CFG_DP_MON_4CHAIN_RING) \ 846 CFG(CFG_DP_4RADIO_RDP_REO) 847 #else 848 #define CFG_DP_INI_SECTION_PARAMS 849 #endif 850 851 /* 852 * <ini> 853 * CFG_DP_SG - Enable the SG feature standalonely 854 * @Min: 0 855 * @Max: 1 856 * @Default: 1 857 * 858 * This ini entry is used to enable/disable SG feature standalonely. 859 * Also does Rome support SG on TX, lithium does not. 860 * For example the lithium does not support SG on UDP frames. 861 * Which is able to handle SG only for TSO frames(in case TSO is enabled). 862 * 863 * Usage: External 864 * 865 * </ini> 866 */ 867 #define CFG_DP_SG \ 868 CFG_INI_BOOL("dp_sg_support", false, \ 869 "DP SG Enable") 870 871 #define WLAN_CFG_GRO_ENABLE_MIN 0 872 #define WLAN_CFG_GRO_ENABLE_MAX 3 873 #define WLAN_CFG_GRO_ENABLE_DEFAULT 0 874 #define DP_GRO_ENABLE_BIT_SET BIT(0) 875 #define DP_FORCE_USE_GRO_BIT_SET BIT(1) 876 /* 877 * <ini> 878 * CFG_DP_GRO - Enable the GRO feature standalonely 879 * @Min: 0 880 * @Max: 3 881 * @Default: 0 882 * 883 * This ini entry is used to enable/disable GRO feature standalonely. 884 * Value 0: Disable GRO feature 885 * Value 1: Enable Dynamic GRO feature, TC rule can control GRO 886 * behavior of STA mode 887 * Value 3: Enable GRO feature forcibly 888 * 889 * Usage: External 890 * 891 * </ini> 892 */ 893 #define CFG_DP_GRO \ 894 CFG_INI_UINT("GROEnable", \ 895 WLAN_CFG_GRO_ENABLE_MIN, \ 896 WLAN_CFG_GRO_ENABLE_MAX, \ 897 WLAN_CFG_GRO_ENABLE_DEFAULT, \ 898 CFG_VALUE_OR_DEFAULT, "DP GRO Enable") 899 900 #define CFG_DP_OL_TX_CSUM \ 901 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \ 902 "DP tx csum Enable") 903 904 #define CFG_DP_OL_RX_CSUM \ 905 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \ 906 "DP rx csum Enable") 907 908 #define CFG_DP_RAWMODE \ 909 CFG_INI_BOOL("dp_rawmode_support", false, \ 910 "DP rawmode Enable") 911 912 #define CFG_DP_PEER_FLOW_CTRL \ 913 CFG_INI_BOOL("dp_peer_flow_control_support", false, \ 914 "DP peer flow ctrl Enable") 915 916 #define CFG_DP_NAPI \ 917 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \ 918 "DP Napi Enabled") 919 /* 920 * <ini> 921 * gEnableP2pIpTcpUdpChecksumOffload - Enable checksum offload for P2P mode 922 * @Min: 0 923 * @Max: 1 924 * @Default: 1 925 * 926 * This ini entry is used to enable/disable TX checksum(UDP/TCP) for P2P modes. 927 * This includes P2P device mode, P2P client mode and P2P GO mode. 928 * The feature is enabled by default. To disable TX checksum for P2P, add the 929 * following entry in ini file: 930 * gEnableP2pIpTcpUdpChecksumOffload=0 931 * 932 * Usage: External 933 * 934 * </ini> 935 */ 936 #define CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD \ 937 CFG_INI_BOOL("gEnableP2pIpTcpUdpChecksumOffload", true, \ 938 "DP TCP UDP Checksum Offload for P2P mode (device/cli/go)") 939 940 /* 941 * <ini> 942 * gEnableNanIpTcpUdpChecksumOffload - Enable checksum offload for NAN mode 943 * @Min: 0 944 * @Max: 1 945 * @Default: 1 946 * 947 * Usage: External 948 * 949 * </ini> 950 */ 951 #define CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD \ 952 CFG_INI_BOOL("gEnableNanIpTcpUdpChecksumOffload", true, \ 953 "DP TCP UDP Checksum Offload for NAN mode") 954 955 /* 956 * <ini> 957 * gEnableIpTcpUdpChecksumOffload - Enable checksum offload 958 * @Min: 0 959 * @Max: 1 960 * @Default: 1 961 * 962 * Usage: External 963 * 964 * </ini> 965 */ 966 #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \ 967 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \ 968 "DP TCP UDP Checksum Offload") 969 970 #define CFG_DP_DEFRAG_TIMEOUT_CHECK \ 971 CFG_INI_BOOL("dp_defrag_timeout_check", true, \ 972 "DP Defrag Timeout Check") 973 974 #define CFG_DP_WBM_RELEASE_RING \ 975 CFG_INI_UINT("dp_wbm_release_ring", \ 976 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \ 977 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \ 978 WLAN_CFG_WBM_RELEASE_RING_SIZE, \ 979 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring") 980 981 #define CFG_DP_TCL_CMD_CREDIT_RING \ 982 CFG_INI_UINT("dp_tcl_cmd_credit_ring", \ 983 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN, \ 984 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX, \ 985 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE, \ 986 CFG_VALUE_OR_DEFAULT, "DP TCL Cmd_Credit ring") 987 988 #define CFG_DP_TCL_STATUS_RING \ 989 CFG_INI_UINT("dp_tcl_status_ring",\ 990 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \ 991 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \ 992 WLAN_CFG_TCL_STATUS_RING_SIZE, \ 993 CFG_VALUE_OR_DEFAULT, "DP TCL status ring") 994 995 #define CFG_DP_REO_REINJECT_RING \ 996 CFG_INI_UINT("dp_reo_reinject_ring", \ 997 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \ 998 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \ 999 WLAN_CFG_REO_REINJECT_RING_SIZE, \ 1000 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring") 1001 1002 #define CFG_DP_RX_RELEASE_RING \ 1003 CFG_INI_UINT("dp_rx_release_ring", \ 1004 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \ 1005 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \ 1006 WLAN_CFG_RX_RELEASE_RING_SIZE, \ 1007 CFG_VALUE_OR_DEFAULT, "DP Rx release ring") 1008 1009 #define CFG_DP_RX_DESTINATION_RING \ 1010 CFG_INI_UINT("dp_reo_dst_ring", \ 1011 WLAN_CFG_REO_DST_RING_SIZE_MIN, \ 1012 WLAN_CFG_REO_DST_RING_SIZE_MAX, \ 1013 WLAN_CFG_REO_DST_RING_SIZE, \ 1014 CFG_VALUE_OR_DEFAULT, "DP REO destination ring") 1015 1016 #define CFG_DP_REO_EXCEPTION_RING \ 1017 CFG_INI_UINT("dp_reo_exception_ring", \ 1018 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \ 1019 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \ 1020 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \ 1021 CFG_VALUE_OR_DEFAULT, "DP REO exception ring") 1022 1023 #define CFG_DP_REO_CMD_RING \ 1024 CFG_INI_UINT("dp_reo_cmd_ring", \ 1025 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \ 1026 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \ 1027 WLAN_CFG_REO_CMD_RING_SIZE, \ 1028 CFG_VALUE_OR_DEFAULT, "DP REO command ring") 1029 1030 #define CFG_DP_REO_STATUS_RING \ 1031 CFG_INI_UINT("dp_reo_status_ring", \ 1032 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \ 1033 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \ 1034 WLAN_CFG_REO_STATUS_RING_SIZE, \ 1035 CFG_VALUE_OR_DEFAULT, "DP REO status ring") 1036 1037 #define CFG_DP_RXDMA_BUF_RING \ 1038 CFG_INI_UINT("dp_rxdma_buf_ring", \ 1039 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \ 1040 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \ 1041 WLAN_CFG_RXDMA_BUF_RING_SIZE, \ 1042 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring") 1043 1044 #define CFG_DP_RXDMA_REFILL_RING \ 1045 CFG_INI_UINT("dp_rxdma_refill_ring", \ 1046 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \ 1047 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \ 1048 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \ 1049 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring") 1050 1051 #define CFG_DP_TX_DESC_LIMIT_0 \ 1052 CFG_INI_UINT("dp_tx_desc_limit_0", \ 1053 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \ 1054 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \ 1055 WLAN_CFG_TX_DESC_LIMIT_0, \ 1056 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0") 1057 1058 #define CFG_DP_TX_DESC_LIMIT_1 \ 1059 CFG_INI_UINT("dp_tx_desc_limit_1", \ 1060 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \ 1061 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \ 1062 WLAN_CFG_TX_DESC_LIMIT_1, \ 1063 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1") 1064 1065 #define CFG_DP_TX_DESC_LIMIT_2 \ 1066 CFG_INI_UINT("dp_tx_desc_limit_2", \ 1067 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \ 1068 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \ 1069 WLAN_CFG_TX_DESC_LIMIT_2, \ 1070 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2") 1071 1072 #define CFG_DP_TX_DEVICE_LIMIT \ 1073 CFG_INI_UINT("dp_tx_device_limit", \ 1074 WLAN_CFG_TX_DEVICE_LIMIT_MIN, \ 1075 WLAN_CFG_TX_DEVICE_LIMIT_MAX, \ 1076 WLAN_CFG_TX_DEVICE_LIMIT, \ 1077 CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit") 1078 1079 #define CFG_DP_TX_SW_INTERNODE_QUEUE \ 1080 CFG_INI_UINT("dp_tx_sw_internode_queue", \ 1081 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \ 1082 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \ 1083 WLAN_CFG_TX_SW_INTERNODE_QUEUE, \ 1084 CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue") 1085 1086 #define CFG_DP_RXDMA_MONITOR_BUF_RING \ 1087 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \ 1088 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \ 1089 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \ 1090 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \ 1091 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring") 1092 1093 #define CFG_DP_TX_MONITOR_BUF_RING \ 1094 CFG_INI_UINT("dp_tx_monitor_buf_ring", \ 1095 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN, \ 1096 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX, \ 1097 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE, \ 1098 CFG_VALUE_OR_DEFAULT, "DP TX monitor buffer ring") 1099 1100 #define CFG_DP_RXDMA_MONITOR_DST_RING \ 1101 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \ 1102 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \ 1103 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \ 1104 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \ 1105 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 1106 1107 #define CFG_DP_TX_MONITOR_DST_RING \ 1108 CFG_INI_UINT("dp_tx_monitor_dst_ring", \ 1109 WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN, \ 1110 WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX, \ 1111 WLAN_CFG_TX_MONITOR_DST_RING_SIZE, \ 1112 CFG_VALUE_OR_DEFAULT, "DP TX monitor destination ring") 1113 1114 #define CFG_DP_RXDMA_MONITOR_STATUS_RING \ 1115 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \ 1116 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \ 1117 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \ 1118 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \ 1119 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring") 1120 1121 #define CFG_DP_RXDMA_MONITOR_DESC_RING \ 1122 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \ 1123 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \ 1124 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \ 1125 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \ 1126 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 1127 1128 #define CFG_DP_RXDMA_ERR_DST_RING \ 1129 CFG_INI_UINT("dp_rxdma_err_dst_ring", \ 1130 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \ 1131 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \ 1132 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \ 1133 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring") 1134 1135 #define CFG_DP_PER_PKT_LOGGING \ 1136 CFG_INI_UINT("enable_verbose_debug", \ 1137 0, 0xffff, 0, \ 1138 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging") 1139 1140 #define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \ 1141 CFG_INI_UINT("TxFlowStartQueueOffset", \ 1142 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \ 1143 CFG_VALUE_OR_DEFAULT, "Start queue offset") 1144 1145 #define CFG_DP_TX_FLOW_STOP_QUEUE_TH \ 1146 CFG_INI_UINT("TxFlowStopQueueThreshold", \ 1147 0, 50, 15, \ 1148 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold") 1149 1150 #define CFG_DP_IPA_UC_TX_BUF_SIZE \ 1151 CFG_INI_UINT("IpaUcTxBufSize", \ 1152 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \ 1153 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size") 1154 1155 #define CFG_DP_IPA_UC_TX_PARTITION_BASE \ 1156 CFG_INI_UINT("IpaUcTxPartitionBase", \ 1157 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \ 1158 CFG_VALUE_OR_DEFAULT, "IPA tx partition base") 1159 1160 #define CFG_DP_IPA_UC_RX_IND_RING_COUNT \ 1161 CFG_INI_UINT("IpaUcRxIndRingCount", \ 1162 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \ 1163 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count") 1164 1165 #define CFG_DP_AP_STA_SECURITY_SEPERATION \ 1166 CFG_INI_BOOL("gDisableIntraBssFwd", \ 1167 false, "Disable intrs BSS Rx packets") 1168 1169 #define CFG_DP_ENABLE_DATA_STALL_DETECTION \ 1170 CFG_INI_BOOL("gEnableDataStallDetection", \ 1171 true, "Enable/Disable Data stall detection") 1172 1173 #define CFG_DP_RX_SW_DESC_WEIGHT \ 1174 CFG_INI_UINT("dp_rx_sw_desc_weight", \ 1175 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN, \ 1176 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX, \ 1177 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE, \ 1178 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC weight") 1179 1180 #define CFG_DP_RX_SW_DESC_NUM \ 1181 CFG_INI_UINT("dp_rx_sw_desc_num", \ 1182 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN, \ 1183 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX, \ 1184 WLAN_CFG_RX_SW_DESC_NUM_SIZE, \ 1185 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC num") 1186 1187 #define CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE \ 1188 CFG_INI_UINT("dp_rx_flow_search_table_size", \ 1189 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN, \ 1190 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX, \ 1191 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT, \ 1192 CFG_VALUE_OR_DEFAULT, \ 1193 "DP Rx Flow Search Table Size in number of entries") 1194 1195 #define CFG_DP_RX_FLOW_TAG_ENABLE \ 1196 CFG_INI_BOOL("dp_rx_flow_tag_enable", false, \ 1197 "Enable/Disable DP Rx Flow Tag") 1198 1199 #define CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV \ 1200 CFG_INI_BOOL("dp_rx_per_pdev_flow_search", false, \ 1201 "DP Rx Flow Search Table Is Per PDev") 1202 1203 #define CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE \ 1204 CFG_INI_BOOL("dp_rx_monitor_protocol_flow_tag_enable", true, \ 1205 "Enable/Disable Rx Protocol & Flow tags in Monitor mode") 1206 1207 #define CFG_DP_TX_PER_PKT_VDEV_ID_CHECK \ 1208 CFG_INI_BOOL("dp_tx_allow_per_pkt_vdev_id_check", false, \ 1209 "Enable/Disable tx Per Pkt vdev id check") 1210 1211 /* 1212 * <ini> 1213 * dp_rx_fisa_enable - Control Rx datapath FISA 1214 * @Min: 0 1215 * @Max: 1 1216 * @Default: 1 1217 * 1218 * This ini is used to enable DP Rx FISA feature 1219 * 1220 * Related: dp_rx_flow_search_table_size 1221 * 1222 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1223 * 1224 * Usage: Internal 1225 * 1226 * </ini> 1227 */ 1228 #define CFG_DP_RX_FISA_ENABLE \ 1229 CFG_INI_BOOL("dp_rx_fisa_enable", true, \ 1230 "Enable/Disable DP Rx FISA") 1231 1232 #define CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD \ 1233 CFG_INI_UINT("mon_drop_thresh", \ 1234 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN, \ 1235 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX, \ 1236 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE, \ 1237 CFG_VALUE_OR_DEFAULT, "RXDMA monitor rx drop theshold") 1238 1239 #define CFG_DP_PKTLOG_BUFFER_SIZE \ 1240 CFG_INI_UINT("PktlogBufSize", \ 1241 WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE, \ 1242 WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE, \ 1243 WLAN_CFG_PKTLOG_BUFFER_SIZE, \ 1244 CFG_VALUE_OR_DEFAULT, "Packet Log buffer size") 1245 1246 #define CFG_DP_FULL_MON_MODE \ 1247 CFG_INI_BOOL("full_mon_mode", \ 1248 false, "Full Monitor mode support") 1249 1250 #define CFG_DP_REO_RINGS_MAP \ 1251 CFG_INI_UINT("dp_reo_rings_map", \ 1252 WLAN_CFG_NUM_REO_RINGS_MAP_MIN, \ 1253 WLAN_CFG_NUM_REO_RINGS_MAP_MAX, \ 1254 WLAN_CFG_NUM_REO_RINGS_MAP, \ 1255 CFG_VALUE_OR_DEFAULT, "REO Destination Rings Mapping") 1256 1257 #define CFG_DP_RX_RADIO_0_DEFAULT_REO \ 1258 CFG_INI_UINT("dp_rx_radio0_default_reo", \ 1259 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1260 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1261 WLAN_CFG_RADIO_0_DEFAULT_REO, \ 1262 CFG_VALUE_OR_DEFAULT, "Radio0 to REO destination default mapping") 1263 1264 #define CFG_DP_RX_RADIO_1_DEFAULT_REO \ 1265 CFG_INI_UINT("dp_rx_radio1_default_reo", \ 1266 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1267 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1268 WLAN_CFG_RADIO_1_DEFAULT_REO, \ 1269 CFG_VALUE_OR_DEFAULT, "Radio1 to REO destination default mapping") 1270 1271 #define CFG_DP_RX_RADIO_2_DEFAULT_REO \ 1272 CFG_INI_UINT("dp_rx_radio2_default_reo", \ 1273 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1274 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1275 WLAN_CFG_RADIO_2_DEFAULT_REO, \ 1276 CFG_VALUE_OR_DEFAULT, "Radio2 to REO destination default mapping") 1277 1278 #define CFG_DP_PEER_EXT_STATS \ 1279 CFG_INI_BOOL("peer_ext_stats", \ 1280 false, "Peer extended stats") 1281 /* 1282 * <ini> 1283 * legacy_mode_csum_disable - Disable csum offload for legacy 802.11abg modes 1284 * @Min: 0 1285 * @Max: 1 1286 * @Default: Default value indicating if checksum should be disabled for 1287 * legacy WLAN modes 1288 * 1289 * This ini is used to disable HW checksum offload capability for legacy 1290 * connections 1291 * 1292 * Related: gEnableIpTcpUdpChecksumOffload should be enabled 1293 * 1294 * Usage: Internal 1295 * 1296 * </ini> 1297 */ 1298 #ifndef DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1299 #define DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1 1300 #endif 1301 1302 #define CFG_DP_LEGACY_MODE_CSUM_DISABLE \ 1303 CFG_INI_BOOL("legacy_mode_csum_disable", \ 1304 DP_LEGACY_MODE_CSM_DEFAULT_DISABLE, \ 1305 "Enable/Disable legacy mode checksum") 1306 1307 #define CFG_DP_RX_BUFF_POOL_ENABLE \ 1308 CFG_INI_BOOL("dp_rx_buff_prealloc_pool", false, \ 1309 "Enable/Disable DP RX emergency buffer pool support") 1310 1311 #define CFG_DP_RX_REFILL_BUFF_POOL_ENABLE \ 1312 CFG_INI_BOOL("dp_rx_refill_buff_pool", false, \ 1313 "Enable/Disable DP RX refill buffer pool support") 1314 1315 #define CFG_DP_POLL_MODE_ENABLE \ 1316 CFG_INI_BOOL("dp_poll_mode_enable", false, \ 1317 "Enable/Disable Polling mode for data path") 1318 1319 #define CFG_DP_RX_FST_IN_CMEM \ 1320 CFG_INI_BOOL("dp_rx_fst_in_cmem", false, \ 1321 "Enable/Disable flow search table in CMEM") 1322 /* 1323 * <ini> 1324 * gEnableSWLM - Control DP Software latency manager 1325 * @Min: 0 1326 * @Max: 1 1327 * @Default: 0 1328 * 1329 * This ini is used to enable DP Software latency Manager 1330 * 1331 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1332 * 1333 * Usage: Internal 1334 * 1335 * </ini> 1336 */ 1337 #define CFG_DP_SWLM_ENABLE \ 1338 CFG_INI_BOOL("gEnableSWLM", false, \ 1339 "Enable/Disable DP SWLM") 1340 /* 1341 * <ini> 1342 * wow_check_rx_pending_enable - control to check RX frames pending in Wow 1343 * @Min: 0 1344 * @Max: 1 1345 * @Default: 0 1346 * 1347 * This ini is used to control DP Software to perform RX pending check 1348 * before entering WoW mode 1349 * 1350 * Usage: Internal 1351 * 1352 * </ini> 1353 */ 1354 #define CFG_DP_WOW_CHECK_RX_PENDING \ 1355 CFG_INI_BOOL("wow_check_rx_pending_enable", \ 1356 false, \ 1357 "enable rx frame pending check in WoW mode") 1358 #define CFG_DP_DELAY_MON_REPLENISH \ 1359 CFG_INI_BOOL("delay_mon_replenish", \ 1360 true, "Delay Monitor Replenish") 1361 1362 #ifdef QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT 1363 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN 500 1364 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX 2000 1365 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER 500 1366 1367 #define CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG \ 1368 CFG_INI_BOOL("vdev_stats_hw_offload_config", \ 1369 false, "Offload vdev stats to HW") 1370 #define CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER \ 1371 CFG_INI_UINT("vdev_stats_hw_offload_timer", \ 1372 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN, \ 1373 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX, \ 1374 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER, \ 1375 CFG_VALUE_OR_DEFAULT, \ 1376 "vdev stats hw offload timer duration") 1377 #define CFG_DP_VDEV_STATS_HW_OFFLOAD \ 1378 CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG) \ 1379 CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER) 1380 #else 1381 #define CFG_DP_VDEV_STATS_HW_OFFLOAD 1382 #endif 1383 1384 /* 1385 * <ini> 1386 * ghw_cc_enable - enable HW cookie conversion by register 1387 * @Min: 0 1388 * @Max: 1 1389 * @Default: 1 1390 * 1391 * This ini is used to control HW based 20 bits cookie to 64 bits 1392 * Desc virtual address conversion 1393 * 1394 * Usage: Internal 1395 * 1396 * </ini> 1397 */ 1398 #define CFG_DP_HW_CC_ENABLE \ 1399 CFG_INI_BOOL("ghw_cc_enable", \ 1400 true, "Enable/Disable HW cookie conversion") 1401 1402 #ifdef IPA_OFFLOAD 1403 /* 1404 * <ini> 1405 * dp_ipa_tx_ring_size - Set tcl ring size for IPA 1406 * @Min: 1024 1407 * @Max: 8096 1408 * @Default: 1024 1409 * 1410 * This ini sets the tcl ring size for IPA 1411 * 1412 * Related: N/A 1413 * 1414 * Supported Feature: IPA 1415 * 1416 * Usage: Internal 1417 * 1418 * </ini> 1419 */ 1420 #define CFG_DP_IPA_TX_RING_SIZE \ 1421 CFG_INI_UINT("dp_ipa_tx_ring_size", \ 1422 WLAN_CFG_IPA_TX_RING_SIZE_MIN, \ 1423 WLAN_CFG_IPA_TX_RING_SIZE_MAX, \ 1424 WLAN_CFG_IPA_TX_RING_SIZE, \ 1425 CFG_VALUE_OR_DEFAULT, "IPA TCL ring size") 1426 1427 /* 1428 * <ini> 1429 * dp_ipa_tx_comp_ring_size - Set tx comp ring size for IPA 1430 * @Min: 1024 1431 * @Max: 8096 1432 * @Default: 1024 1433 * 1434 * This ini sets the tx comp ring size for IPA 1435 * 1436 * Related: N/A 1437 * 1438 * Supported Feature: IPA 1439 * 1440 * Usage: Internal 1441 * 1442 * </ini> 1443 */ 1444 #define CFG_DP_IPA_TX_COMP_RING_SIZE \ 1445 CFG_INI_UINT("dp_ipa_tx_comp_ring_size", \ 1446 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN, \ 1447 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX, \ 1448 WLAN_CFG_IPA_TX_COMP_RING_SIZE, \ 1449 CFG_VALUE_OR_DEFAULT, "IPA tx comp ring size") 1450 1451 #ifdef IPA_WDI3_TX_TWO_PIPES 1452 /* 1453 * <ini> 1454 * dp_ipa_tx_alt_ring_size - Set alt tcl ring size for IPA 1455 * @Min: 1024 1456 * @Max: 8096 1457 * @Default: 1024 1458 * 1459 * This ini sets the alt tcl ring size for IPA 1460 * 1461 * Related: N/A 1462 * 1463 * Supported Feature: IPA 1464 * 1465 * Usage: Internal 1466 * 1467 * </ini> 1468 */ 1469 #define CFG_DP_IPA_TX_ALT_RING_SIZE \ 1470 CFG_INI_UINT("dp_ipa_tx_alt_ring_size", \ 1471 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN, \ 1472 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX, \ 1473 WLAN_CFG_IPA_TX_ALT_RING_SIZE, \ 1474 CFG_VALUE_OR_DEFAULT, \ 1475 "DP IPA TX Alternative Ring Size") 1476 1477 /* 1478 * <ini> 1479 * dp_ipa_tx_alt_comp_ring_size - Set tx alt comp ring size for IPA 1480 * @Min: 1024 1481 * @Max: 8096 1482 * @Default: 1024 1483 * 1484 * This ini sets the tx alt comp ring size for IPA 1485 * 1486 * Related: N/A 1487 * 1488 * Supported Feature: IPA 1489 * 1490 * Usage: Internal 1491 * 1492 * </ini> 1493 */ 1494 #define CFG_DP_IPA_TX_ALT_COMP_RING_SIZE \ 1495 CFG_INI_UINT("dp_ipa_tx_alt_comp_ring_size", \ 1496 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN, \ 1497 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX, \ 1498 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE, \ 1499 CFG_VALUE_OR_DEFAULT, \ 1500 "DP IPA TX Alternative Completion Ring Size") 1501 1502 #define CFG_DP_IPA_TX_ALT_RING_CFG \ 1503 CFG(CFG_DP_IPA_TX_ALT_RING_SIZE) \ 1504 CFG(CFG_DP_IPA_TX_ALT_COMP_RING_SIZE) 1505 1506 #else 1507 #define CFG_DP_IPA_TX_ALT_RING_CFG 1508 #endif 1509 1510 #define CFG_DP_IPA_TX_RING_CFG \ 1511 CFG(CFG_DP_IPA_TX_RING_SIZE) \ 1512 CFG(CFG_DP_IPA_TX_COMP_RING_SIZE) 1513 #else 1514 #define CFG_DP_IPA_TX_RING_CFG 1515 #define CFG_DP_IPA_TX_ALT_RING_CFG 1516 #endif 1517 1518 #ifdef WLAN_SUPPORT_PPEDS 1519 #define CFG_DP_PPE_ENABLE \ 1520 CFG_INI_BOOL("ppe_enable", false, \ 1521 "DP ppe enable flag") 1522 1523 #define CFG_DP_REO2PPE_RING \ 1524 CFG_INI_UINT("dp_reo2ppe_ring", \ 1525 WLAN_CFG_REO2PPE_RING_SIZE_MIN, \ 1526 WLAN_CFG_REO2PPE_RING_SIZE_MAX, \ 1527 WLAN_CFG_REO2PPE_RING_SIZE, \ 1528 CFG_VALUE_OR_DEFAULT, "DP REO2PPE ring") 1529 1530 #define CFG_DP_PPE2TCL_RING \ 1531 CFG_INI_UINT("dp_ppe2tcl_ring", \ 1532 WLAN_CFG_PPE2TCL_RING_SIZE_MIN, \ 1533 WLAN_CFG_PPE2TCL_RING_SIZE_MAX, \ 1534 WLAN_CFG_PPE2TCL_RING_SIZE, \ 1535 CFG_VALUE_OR_DEFAULT, "DP PPE2TCL rings") 1536 1537 #define CFG_DP_PPE_RELEASE_RING \ 1538 CFG_INI_UINT("dp_ppe_release_ring", \ 1539 WLAN_CFG_PPE_RELEASE_RING_SIZE_MIN, \ 1540 WLAN_CFG_PPE_RELEASE_RING_SIZE_MAX, \ 1541 WLAN_CFG_PPE_RELEASE_RING_SIZE, \ 1542 CFG_VALUE_OR_DEFAULT, "DP PPE Release Ring") 1543 1544 #define CFG_DP_PPE_CONFIG \ 1545 CFG(CFG_DP_PPE_ENABLE) \ 1546 CFG(CFG_DP_REO2PPE_RING) \ 1547 CFG(CFG_DP_PPE2TCL_RING) \ 1548 CFG(CFG_DP_PPE_RELEASE_RING) 1549 #else 1550 #define CFG_DP_PPE_CONFIG 1551 #endif 1552 1553 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 1554 /* 1555 * <ini> 1556 * dp_chip0_rx_ring_map - Set Rx ring map for CHIP 0 1557 * @Min: 0x0 1558 * @Max: 0xFF 1559 * @Default: 0xF 1560 * 1561 * This ini sets Rx ring map for CHIP 0 1562 * 1563 * Usage: Internal 1564 * 1565 * </ini> 1566 */ 1567 #define CFG_DP_MLO_CHIP0_RX_RING_MAP \ 1568 CFG_INI_UINT("dp_chip0_rx_ring_map", \ 1569 WLAN_CFG_MLO_RX_RING_MAP_MIN, \ 1570 WLAN_CFG_MLO_RX_RING_MAP_MAX, \ 1571 WLAN_CFG_MLO_RX_RING_MAP, \ 1572 CFG_VALUE_OR_DEFAULT, "DP Rx ring map chip0") 1573 1574 /* 1575 * <ini> 1576 * dp_chip1_rx_ring_map - Set Rx ring map for CHIP 1 1577 * @Min: 0x0 1578 * @Max: 0xFF 1579 * @Default: 0xF 1580 * 1581 * This ini sets Rx ring map for CHIP 1 1582 * 1583 * Usage: Internal 1584 * 1585 * </ini> 1586 */ 1587 #define CFG_DP_MLO_CHIP1_RX_RING_MAP \ 1588 CFG_INI_UINT("dp_chip1_rx_ring_map", \ 1589 WLAN_CFG_MLO_RX_RING_MAP_MIN, \ 1590 WLAN_CFG_MLO_RX_RING_MAP_MAX, \ 1591 WLAN_CFG_MLO_RX_RING_MAP, \ 1592 CFG_VALUE_OR_DEFAULT, "DP Rx ring map chip1") 1593 1594 /* 1595 * <ini> 1596 * dp_chip2_rx_ring_map - Set Rx ring map for CHIP 2 1597 * @Min: 0x0 1598 * @Max: 0xFF 1599 * @Default: 0xF 1600 * 1601 * This ini sets Rx ring map for CHIP 2 1602 * 1603 * Usage: Internal 1604 * 1605 * </ini> 1606 */ 1607 #define CFG_DP_MLO_CHIP2_RX_RING_MAP \ 1608 CFG_INI_UINT("dp_chip2_rx_ring_map", \ 1609 WLAN_CFG_MLO_RX_RING_MAP_MIN, \ 1610 WLAN_CFG_MLO_RX_RING_MAP_MAX, \ 1611 WLAN_CFG_MLO_RX_RING_MAP, \ 1612 CFG_VALUE_OR_DEFAULT, "DP Rx ring map chip2") 1613 1614 #define CFG_DP_MLO_CONFIG \ 1615 CFG(CFG_DP_MLO_CHIP0_RX_RING_MAP) \ 1616 CFG(CFG_DP_MLO_CHIP1_RX_RING_MAP) \ 1617 CFG(CFG_DP_MLO_CHIP2_RX_RING_MAP) 1618 #else 1619 #define CFG_DP_MLO_CONFIG 1620 #endif 1621 1622 #define CFG_DP \ 1623 CFG(CFG_DP_HTT_PACKET_TYPE) \ 1624 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \ 1625 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \ 1626 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \ 1627 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \ 1628 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \ 1629 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \ 1630 CFG(CFG_DP_MAX_ALLOC_SIZE) \ 1631 CFG(CFG_DP_MAX_CLIENTS) \ 1632 CFG(CFG_DP_MAX_PEER_ID) \ 1633 CFG(CFG_DP_REO_DEST_RINGS) \ 1634 CFG(CFG_DP_TX_COMP_RINGS) \ 1635 CFG(CFG_DP_TCL_DATA_RINGS) \ 1636 CFG(CFG_DP_NSS_REO_DEST_RINGS) \ 1637 CFG(CFG_DP_NSS_TCL_DATA_RINGS) \ 1638 CFG(CFG_DP_TX_DESC) \ 1639 CFG(CFG_DP_TX_EXT_DESC) \ 1640 CFG(CFG_DP_TX_EXT_DESC_POOLS) \ 1641 CFG(CFG_DP_PDEV_RX_RING) \ 1642 CFG(CFG_DP_PDEV_TX_RING) \ 1643 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \ 1644 CFG(CFG_DP_TX_COMPL_RING_SIZE) \ 1645 CFG(CFG_DP_TX_RING_SIZE) \ 1646 CFG(CFG_DP_NSS_COMP_RING_SIZE) \ 1647 CFG(CFG_DP_PDEV_LMAC_RING) \ 1648 CFG(CFG_DP_BASE_HW_MAC_ID) \ 1649 CFG(CFG_DP_RX_HASH) \ 1650 CFG(CFG_DP_TSO) \ 1651 CFG(CFG_DP_LRO) \ 1652 CFG(CFG_DP_SG) \ 1653 CFG(CFG_DP_GRO) \ 1654 CFG(CFG_DP_OL_TX_CSUM) \ 1655 CFG(CFG_DP_OL_RX_CSUM) \ 1656 CFG(CFG_DP_RAWMODE) \ 1657 CFG(CFG_DP_PEER_FLOW_CTRL) \ 1658 CFG(CFG_DP_NAPI) \ 1659 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \ 1660 CFG(CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD) \ 1661 CFG(CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD) \ 1662 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \ 1663 CFG(CFG_DP_WBM_RELEASE_RING) \ 1664 CFG(CFG_DP_TCL_CMD_CREDIT_RING) \ 1665 CFG(CFG_DP_TCL_STATUS_RING) \ 1666 CFG(CFG_DP_REO_REINJECT_RING) \ 1667 CFG(CFG_DP_RX_RELEASE_RING) \ 1668 CFG(CFG_DP_REO_EXCEPTION_RING) \ 1669 CFG(CFG_DP_RX_DESTINATION_RING) \ 1670 CFG(CFG_DP_REO_CMD_RING) \ 1671 CFG(CFG_DP_REO_STATUS_RING) \ 1672 CFG(CFG_DP_RXDMA_BUF_RING) \ 1673 CFG(CFG_DP_RXDMA_REFILL_RING) \ 1674 CFG(CFG_DP_TX_DESC_LIMIT_0) \ 1675 CFG(CFG_DP_TX_DESC_LIMIT_1) \ 1676 CFG(CFG_DP_TX_DESC_LIMIT_2) \ 1677 CFG(CFG_DP_TX_DEVICE_LIMIT) \ 1678 CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \ 1679 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \ 1680 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \ 1681 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \ 1682 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \ 1683 CFG(CFG_DP_RXDMA_ERR_DST_RING) \ 1684 CFG(CFG_DP_PER_PKT_LOGGING) \ 1685 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \ 1686 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \ 1687 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \ 1688 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \ 1689 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \ 1690 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \ 1691 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) \ 1692 CFG(CFG_DP_RX_SW_DESC_WEIGHT) \ 1693 CFG(CFG_DP_RX_SW_DESC_NUM) \ 1694 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE) \ 1695 CFG(CFG_DP_RX_FLOW_TAG_ENABLE) \ 1696 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV) \ 1697 CFG(CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE) \ 1698 CFG(CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD) \ 1699 CFG(CFG_DP_PKTLOG_BUFFER_SIZE) \ 1700 CFG(CFG_DP_RX_FISA_ENABLE) \ 1701 CFG(CFG_DP_FULL_MON_MODE) \ 1702 CFG(CFG_DP_REO_RINGS_MAP) \ 1703 CFG(CFG_DP_PEER_EXT_STATS) \ 1704 CFG(CFG_DP_RX_BUFF_POOL_ENABLE) \ 1705 CFG(CFG_DP_RX_REFILL_BUFF_POOL_ENABLE) \ 1706 CFG(CFG_DP_RX_PENDING_HL_THRESHOLD) \ 1707 CFG(CFG_DP_RX_PENDING_LO_THRESHOLD) \ 1708 CFG(CFG_DP_LEGACY_MODE_CSUM_DISABLE) \ 1709 CFG(CFG_DP_POLL_MODE_ENABLE) \ 1710 CFG(CFG_DP_SWLM_ENABLE) \ 1711 CFG(CFG_DP_TX_PER_PKT_VDEV_ID_CHECK) \ 1712 CFG(CFG_DP_RX_FST_IN_CMEM) \ 1713 CFG(CFG_DP_RX_RADIO_0_DEFAULT_REO) \ 1714 CFG(CFG_DP_RX_RADIO_1_DEFAULT_REO) \ 1715 CFG(CFG_DP_RX_RADIO_2_DEFAULT_REO) \ 1716 CFG(CFG_DP_WOW_CHECK_RX_PENDING) \ 1717 CFG(CFG_DP_HW_CC_ENABLE) \ 1718 CFG(CFG_DP_DELAY_MON_REPLENISH) \ 1719 CFG(CFG_DP_TX_MONITOR_BUF_RING) \ 1720 CFG(CFG_DP_TX_MONITOR_DST_RING) \ 1721 CFG_DP_IPA_TX_RING_CFG \ 1722 CFG_DP_PPE_CONFIG \ 1723 CFG_DP_IPA_TX_ALT_RING_CFG \ 1724 CFG_DP_MLO_CONFIG \ 1725 CFG_DP_INI_SECTION_PARAMS \ 1726 CFG_DP_VDEV_STATS_HW_OFFLOAD \ 1727 CFG(CFG_DP_TX_CAPT_MAX_MEM_MB) 1728 #endif /* _CFG_DP_H_ */ 1729