1 /* 2 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /** 20 * DOC: This file contains definitions of Data Path configuration. 21 */ 22 23 #ifndef _CFG_DP_H_ 24 #define _CFG_DP_H_ 25 26 #include "cfg_define.h" 27 28 #define WLAN_CFG_MAX_CLIENTS 64 29 #define WLAN_CFG_MAX_CLIENTS_MIN 8 30 #define WLAN_CFG_MAX_CLIENTS_MAX 64 31 32 /* Change this to a lower value to enforce scattered idle list mode */ 33 #define WLAN_CFG_MAX_ALLOC_SIZE 0x200000 34 #define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000 35 #define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000 36 37 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 38 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3 39 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3 40 41 #if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \ 42 defined(QCA_LL_PDEV_TX_FLOW_CONTROL) 43 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10 44 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15 45 #else 46 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 47 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 48 #endif 49 50 #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0 51 #define WLAN_CFG_PER_PDEV_TX_RING_MAX 1 52 53 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 54 #define WLAN_CFG_PER_PDEV_RX_RING 0 55 #define WLAN_CFG_PER_PDEV_LMAC_RING 0 56 #define WLAN_LRO_ENABLE 0 57 #ifdef QCA_WIFI_QCA6750 58 #define WLAN_CFG_MAC_PER_TARGET 1 59 #else 60 #define WLAN_CFG_MAC_PER_TARGET 2 61 #endif 62 #ifdef IPA_OFFLOAD 63 /* Size of TCL TX Ring */ 64 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 65 #define WLAN_CFG_TX_RING_SIZE 2048 66 #else 67 #define WLAN_CFG_TX_RING_SIZE 1024 68 #endif 69 70 #define WLAN_CFG_IPA_TX_RING_SIZE 1024 71 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE 1024 72 73 #define WLAN_CFG_PER_PDEV_TX_RING 0 74 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048 75 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000 76 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024 77 #else 78 #define WLAN_CFG_TX_RING_SIZE 512 79 #define WLAN_CFG_PER_PDEV_TX_RING 1 80 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 81 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 82 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 83 #endif 84 85 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 86 #define WLAN_CFG_TX_COMP_RING_SIZE 4096 87 88 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 89 #define WLAN_CFG_NUM_TX_DESC 4096 90 #define WLAN_CFG_NUM_TX_EXT_DESC 4096 91 #else 92 #define WLAN_CFG_TX_COMP_RING_SIZE 1024 93 94 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 95 #define WLAN_CFG_NUM_TX_DESC 1024 96 #define WLAN_CFG_NUM_TX_EXT_DESC 1024 97 #endif 98 99 /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 100 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1 101 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1 102 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 103 104 /* Interrupt Mitigation - Timer threshold in us */ 105 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8 106 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8 107 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8 108 #endif 109 110 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD 0x60000 111 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN 0 112 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX 0x80000 113 114 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD 0x60000 115 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN 100 116 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX 0x80000 117 118 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256 119 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 512 120 121 #define WLAN_CFG_PER_PDEV_RX_RING_MIN 0 122 #define WLAN_CFG_PER_PDEV_RX_RING_MAX 0 123 124 #define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0 125 #define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1 126 127 #define WLAN_CFG_TX_RING_SIZE_MIN 512 128 #define WLAN_CFG_TX_RING_SIZE_MAX 0x80000 129 130 #define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512 131 #define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000 132 133 #define WLAN_CFG_NUM_TX_DESC_MIN 16 134 #define WLAN_CFG_NUM_TX_DESC_MAX 32768 135 136 #define WLAN_CFG_NUM_TX_EXT_DESC_MIN 16 137 #define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000 138 139 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1 140 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256 141 142 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 1 143 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128 144 145 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1 146 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128 147 148 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1 149 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128 150 151 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1 152 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1 153 154 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8 155 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 1000 156 157 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8 158 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500 159 160 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8 161 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000 162 163 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8 164 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 512 165 166 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8 167 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500 168 169 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000 170 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000 171 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000 172 173 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 174 175 /* Per vdev pools */ 176 #define WLAN_CFG_NUM_TX_DESC_POOL 3 177 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 178 179 #else /* QCA_LL_TX_FLOW_CONTROL_V2 */ 180 181 #ifdef TX_PER_PDEV_DESC_POOL 182 #define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT 183 #define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT 184 185 #else /* TX_PER_PDEV_DESC_POOL */ 186 187 #define WLAN_CFG_NUM_TX_DESC_POOL 3 188 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 189 190 #endif /* TX_PER_PDEV_DESC_POOL */ 191 #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */ 192 193 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1 194 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4 195 196 #define WLAN_CFG_HTT_PKT_TYPE 2 197 #define WLAN_CFG_HTT_PKT_TYPE_MIN 2 198 #define WLAN_CFG_HTT_PKT_TYPE_MAX 2 199 200 #define WLAN_CFG_MAX_PEER_ID 64 201 #define WLAN_CFG_MAX_PEER_ID_MIN 64 202 #define WLAN_CFG_MAX_PEER_ID_MAX 64 203 204 #define WLAN_CFG_RX_DEFRAG_TIMEOUT 100 205 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100 206 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100 207 208 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 209 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3 210 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3 211 212 #define WLAN_CFG_NUM_REO_DEST_RING 4 213 #define WLAN_CFG_NUM_REO_DEST_RING_MIN 4 214 #define WLAN_CFG_NUM_REO_DEST_RING_MAX 4 215 216 #define WLAN_CFG_WBM_RELEASE_RING_SIZE 1024 217 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64 218 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 1024 219 220 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE 32 221 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN 32 222 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX 32 223 224 #define WLAN_CFG_TCL_STATUS_RING_SIZE 32 225 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32 226 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32 227 228 #if defined(QCA_WIFI_QCA6290) 229 #define WLAN_CFG_REO_DST_RING_SIZE 1024 230 #else 231 #define WLAN_CFG_REO_DST_RING_SIZE 2048 232 #endif 233 234 #define WLAN_CFG_REO_DST_RING_SIZE_MIN 1024 235 #define WLAN_CFG_REO_DST_RING_SIZE_MAX 2048 236 237 #define WLAN_CFG_REO_REINJECT_RING_SIZE 128 238 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32 239 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 128 240 241 #define WLAN_CFG_RX_RELEASE_RING_SIZE 1024 242 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8 243 #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 244 defined(QCA_WIFI_QCA6750) 245 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024 246 #else 247 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 8192 248 #endif 249 250 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE 128 251 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128 252 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 128 253 254 #define WLAN_CFG_REO_CMD_RING_SIZE 128 255 #define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64 256 #define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128 257 258 #define WLAN_CFG_REO_STATUS_RING_SIZE 256 259 #define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128 260 #define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048 261 262 #define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024 263 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024 264 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 1024 265 266 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096 267 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16 268 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 4096 269 270 #define WLAN_CFG_TX_DESC_LIMIT_0 0 271 #define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096 272 #define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768 273 274 #define WLAN_CFG_TX_DESC_LIMIT_1 0 275 #define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096 276 #define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768 277 278 #define WLAN_CFG_TX_DESC_LIMIT_2 0 279 #define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096 280 #define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768 281 282 #define WLAN_CFG_TX_DEVICE_LIMIT 65536 283 #define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384 284 #define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536 285 286 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024 287 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128 288 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024 289 290 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096 291 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16 292 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192 293 294 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048 295 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48 296 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192 297 298 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024 299 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16 300 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192 301 302 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096 303 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096 304 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384 305 306 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024 307 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024 308 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192 309 310 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE 32 311 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN 0 312 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX 256 313 314 /** 315 * Allocate as many RX descriptors as buffers in the SW2RXDMA 316 * ring. This value may need to be tuned later. 317 */ 318 #if defined(QCA_HOST2FW_RXBUF_RING) 319 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 320 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 321 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 1 322 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 323 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 4096 324 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 4096 325 326 /** 327 * For low memory AP cases using 1 will reduce the rx descriptors memory req 328 */ 329 #elif defined(QCA_LOWMEM_CONFIG) || defined(QCA_512M_CONFIG) 330 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 331 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 332 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 333 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 334 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 335 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 12288 336 337 /** 338 * AP use cases need to allocate more RX Descriptors than the number of 339 * entries avaialable in the SW2RXDMA buffer replenish ring. This is to account 340 * for frames sitting in REO queues, HW-HW DMA rings etc. Hence using a 341 * multiplication factor of 3, to allocate three times as many RX descriptors 342 * as RX buffers. 343 */ 344 #else 345 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 3 346 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 347 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 348 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 12288 349 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 4096 350 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 12288 351 #endif //QCA_HOST2FW_RXBUF_RING 352 353 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE 16384 354 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN 1 355 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX 16384 356 357 #define WLAN_CFG_PKTLOG_BUFFER_SIZE 10 358 #define WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE 1 359 #define WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE 10 360 361 #define WLAN_CFG_NUM_REO_RINGS_MAP 0xF 362 #define WLAN_CFG_NUM_REO_RINGS_MAP_MIN 0x1 363 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xF 364 365 /* DP INI Declerations */ 366 #define CFG_DP_HTT_PACKET_TYPE \ 367 CFG_INI_UINT("dp_htt_packet_type", \ 368 WLAN_CFG_HTT_PKT_TYPE_MIN, \ 369 WLAN_CFG_HTT_PKT_TYPE_MAX, \ 370 WLAN_CFG_HTT_PKT_TYPE, \ 371 CFG_VALUE_OR_DEFAULT, "DP HTT packet type") 372 373 #define CFG_DP_INT_BATCH_THRESHOLD_OTHER \ 374 CFG_INI_UINT("dp_int_batch_threshold_other", \ 375 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \ 376 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \ 377 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \ 378 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other") 379 380 #define CFG_DP_INT_BATCH_THRESHOLD_RX \ 381 CFG_INI_UINT("dp_int_batch_threshold_rx", \ 382 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \ 383 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \ 384 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \ 385 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx") 386 387 #define CFG_DP_INT_BATCH_THRESHOLD_TX \ 388 CFG_INI_UINT("dp_int_batch_threshold_tx", \ 389 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \ 390 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \ 391 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \ 392 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx") 393 394 #define CFG_DP_INT_TIMER_THRESHOLD_OTHER \ 395 CFG_INI_UINT("dp_int_timer_threshold_other", \ 396 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \ 397 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \ 398 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \ 399 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other") 400 401 #define CFG_DP_INT_TIMER_THRESHOLD_RX \ 402 CFG_INI_UINT("dp_int_timer_threshold_rx", \ 403 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \ 404 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \ 405 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \ 406 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx") 407 408 #define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \ 409 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \ 410 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \ 411 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \ 412 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \ 413 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring") 414 415 #define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \ 416 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \ 417 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \ 418 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \ 419 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \ 420 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring") 421 422 #define CFG_DP_INT_TIMER_THRESHOLD_TX \ 423 CFG_INI_UINT("dp_int_timer_threshold_tx", \ 424 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \ 425 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \ 426 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \ 427 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx") 428 429 #define CFG_DP_MAX_ALLOC_SIZE \ 430 CFG_INI_UINT("dp_max_alloc_size", \ 431 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \ 432 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \ 433 WLAN_CFG_MAX_ALLOC_SIZE, \ 434 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size") 435 436 #define CFG_DP_MAX_CLIENTS \ 437 CFG_INI_UINT("dp_max_clients", \ 438 WLAN_CFG_MAX_CLIENTS_MIN, \ 439 WLAN_CFG_MAX_CLIENTS_MAX, \ 440 WLAN_CFG_MAX_CLIENTS, \ 441 CFG_VALUE_OR_DEFAULT, "DP Max Clients") 442 443 #define CFG_DP_MAX_PEER_ID \ 444 CFG_INI_UINT("dp_max_peer_id", \ 445 WLAN_CFG_MAX_PEER_ID_MIN, \ 446 WLAN_CFG_MAX_PEER_ID_MAX, \ 447 WLAN_CFG_MAX_PEER_ID, \ 448 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID") 449 450 #define CFG_DP_REO_DEST_RINGS \ 451 CFG_INI_UINT("dp_reo_dest_rings", \ 452 WLAN_CFG_NUM_REO_DEST_RING_MIN, \ 453 WLAN_CFG_NUM_REO_DEST_RING_MAX, \ 454 WLAN_CFG_NUM_REO_DEST_RING, \ 455 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings") 456 457 #define CFG_DP_TCL_DATA_RINGS \ 458 CFG_INI_UINT("dp_tcl_data_rings", \ 459 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \ 460 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \ 461 WLAN_CFG_NUM_TCL_DATA_RINGS, \ 462 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings") 463 464 #define CFG_DP_TX_DESC \ 465 CFG_INI_UINT("dp_tx_desc", \ 466 WLAN_CFG_NUM_TX_DESC_MIN, \ 467 WLAN_CFG_NUM_TX_DESC_MAX, \ 468 WLAN_CFG_NUM_TX_DESC, \ 469 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors") 470 471 #define CFG_DP_TX_EXT_DESC \ 472 CFG_INI_UINT("dp_tx_ext_desc", \ 473 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \ 474 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \ 475 WLAN_CFG_NUM_TX_EXT_DESC, \ 476 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors") 477 478 #define CFG_DP_TX_EXT_DESC_POOLS \ 479 CFG_INI_UINT("dp_tx_ext_desc_pool", \ 480 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \ 481 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \ 482 WLAN_CFG_NUM_TXEXT_DESC_POOL, \ 483 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool") 484 485 #define CFG_DP_PDEV_RX_RING \ 486 CFG_INI_UINT("dp_pdev_rx_ring", \ 487 WLAN_CFG_PER_PDEV_RX_RING_MIN, \ 488 WLAN_CFG_PER_PDEV_RX_RING_MAX, \ 489 WLAN_CFG_PER_PDEV_RX_RING, \ 490 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring") 491 492 #define CFG_DP_PDEV_TX_RING \ 493 CFG_INI_UINT("dp_pdev_tx_ring", \ 494 WLAN_CFG_PER_PDEV_TX_RING_MIN, \ 495 WLAN_CFG_PER_PDEV_TX_RING_MAX, \ 496 WLAN_CFG_PER_PDEV_TX_RING, \ 497 CFG_VALUE_OR_DEFAULT, \ 498 "DP PDEV Tx Ring") 499 500 #define CFG_DP_RX_DEFRAG_TIMEOUT \ 501 CFG_INI_UINT("dp_rx_defrag_timeout", \ 502 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \ 503 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \ 504 WLAN_CFG_RX_DEFRAG_TIMEOUT, \ 505 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout") 506 507 #define CFG_DP_TX_COMPL_RING_SIZE \ 508 CFG_INI_UINT("dp_tx_compl_ring_size", \ 509 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \ 510 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \ 511 WLAN_CFG_TX_COMP_RING_SIZE, \ 512 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size") 513 514 #define CFG_DP_TX_RING_SIZE \ 515 CFG_INI_UINT("dp_tx_ring_size", \ 516 WLAN_CFG_TX_RING_SIZE_MIN,\ 517 WLAN_CFG_TX_RING_SIZE_MAX,\ 518 WLAN_CFG_TX_RING_SIZE,\ 519 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size") 520 521 #define CFG_DP_NSS_COMP_RING_SIZE \ 522 CFG_INI_UINT("dp_nss_comp_ring_size", \ 523 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \ 524 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \ 525 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \ 526 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size") 527 528 #define CFG_DP_PDEV_LMAC_RING \ 529 CFG_INI_UINT("dp_pdev_lmac_ring", \ 530 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \ 531 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \ 532 WLAN_CFG_PER_PDEV_LMAC_RING, \ 533 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring") 534 /* 535 * <ini> 536 * dp_rx_pending_hl_threshold - High threshold of frame number to start 537 * frame dropping scheme 538 * @Min: 0 539 * @Max: 524288 540 * @Default: 393216 541 * 542 * This ini entry is used to set a high limit threshold to start frame 543 * dropping scheme 544 * 545 * Usage: External 546 * 547 * </ini> 548 */ 549 #define CFG_DP_RX_PENDING_HL_THRESHOLD \ 550 CFG_INI_UINT("dp_rx_pending_hl_threshold", \ 551 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN, \ 552 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX, \ 553 WLAN_CFG_RX_PENDING_HL_THRESHOLD, \ 554 CFG_VALUE_OR_DEFAULT, "DP rx pending hl threshold") 555 556 /* 557 * <ini> 558 * dp_rx_pending_lo_threshold - Low threshold of frame number to stop 559 * frame dropping scheme 560 * @Min: 100 561 * @Max: 524288 562 * @Default: 393216 563 * 564 * This ini entry is used to set a low limit threshold to stop frame 565 * dropping scheme 566 * 567 * Usage: External 568 * 569 * </ini> 570 */ 571 #define CFG_DP_RX_PENDING_LO_THRESHOLD \ 572 CFG_INI_UINT("dp_rx_pending_lo_threshold", \ 573 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN, \ 574 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX, \ 575 WLAN_CFG_RX_PENDING_LO_THRESHOLD, \ 576 CFG_VALUE_OR_DEFAULT, "DP rx pending lo threshold") 577 578 #define CFG_DP_BASE_HW_MAC_ID \ 579 CFG_INI_UINT("dp_base_hw_macid", \ 580 0, 1, 1, \ 581 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID") 582 583 #define CFG_DP_RX_HASH \ 584 CFG_INI_BOOL("dp_rx_hash", true, \ 585 "DP Rx Hash") 586 587 #define CFG_DP_TSO \ 588 CFG_INI_BOOL("TSOEnable", false, \ 589 "DP TSO Enabled") 590 591 #define CFG_DP_LRO \ 592 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \ 593 "DP LRO Enable") 594 595 #define CFG_DP_SG \ 596 CFG_INI_BOOL("dp_sg_support", false, \ 597 "DP SG Enable") 598 599 #define CFG_DP_GRO \ 600 CFG_INI_BOOL("GROEnable", false, \ 601 "DP GRO Enable") 602 603 #define CFG_DP_OL_TX_CSUM \ 604 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \ 605 "DP tx csum Enable") 606 607 #define CFG_DP_OL_RX_CSUM \ 608 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \ 609 "DP rx csum Enable") 610 611 #define CFG_DP_RAWMODE \ 612 CFG_INI_BOOL("dp_rawmode_support", false, \ 613 "DP rawmode Enable") 614 615 #define CFG_DP_PEER_FLOW_CTRL \ 616 CFG_INI_BOOL("dp_peer_flow_control_support", false, \ 617 "DP peer flow ctrl Enable") 618 619 #define CFG_DP_NAPI \ 620 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \ 621 "DP Napi Enabled") 622 /* 623 * <ini> 624 * gEnableP2pIpTcpUdpChecksumOffload - Enable checksum offload for P2P mode 625 * @Min: 0 626 * @Max: 1 627 * @Default: 1 628 * 629 * This ini entry is used to enable/disable TX checksum(UDP/TCP) for P2P modes. 630 * This includes P2P device mode, P2P client mode and P2P GO mode. 631 * The feature is enabled by default. To disable TX checksum for P2P, add the 632 * following entry in ini file: 633 * gEnableP2pIpTcpUdpChecksumOffload=0 634 * 635 * Usage: External 636 * 637 * </ini> 638 */ 639 #define CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD \ 640 CFG_INI_BOOL("gEnableP2pIpTcpUdpChecksumOffload", true, \ 641 "DP TCP UDP Checksum Offload for P2P mode (device/cli/go)") 642 643 /* 644 * <ini> 645 * gEnableNanIpTcpUdpChecksumOffload - Enable checksum offload for NAN mode 646 * @Min: 0 647 * @Max: 1 648 * @Default: 1 649 * 650 * Usage: External 651 * 652 * </ini> 653 */ 654 #define CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD \ 655 CFG_INI_BOOL("gEnableNanIpTcpUdpChecksumOffload", true, \ 656 "DP TCP UDP Checksum Offload for NAN mode") 657 658 /* 659 * <ini> 660 * gEnableIpTcpUdpChecksumOffload - Enable checksum offload 661 * @Min: 0 662 * @Max: 1 663 * @Default: 1 664 * 665 * Usage: External 666 * 667 * </ini> 668 */ 669 #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \ 670 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \ 671 "DP TCP UDP Checksum Offload") 672 673 #define CFG_DP_DEFRAG_TIMEOUT_CHECK \ 674 CFG_INI_BOOL("dp_defrag_timeout_check", true, \ 675 "DP Defrag Timeout Check") 676 677 #define CFG_DP_WBM_RELEASE_RING \ 678 CFG_INI_UINT("dp_wbm_release_ring", \ 679 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \ 680 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \ 681 WLAN_CFG_WBM_RELEASE_RING_SIZE, \ 682 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring") 683 684 #define CFG_DP_TCL_CMD_CREDIT_RING \ 685 CFG_INI_UINT("dp_tcl_cmd_credit_ring", \ 686 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN, \ 687 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX, \ 688 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE, \ 689 CFG_VALUE_OR_DEFAULT, "DP TCL Cmd_Credit ring") 690 691 #define CFG_DP_TCL_STATUS_RING \ 692 CFG_INI_UINT("dp_tcl_status_ring",\ 693 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \ 694 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \ 695 WLAN_CFG_TCL_STATUS_RING_SIZE, \ 696 CFG_VALUE_OR_DEFAULT, "DP TCL status ring") 697 698 #define CFG_DP_REO_REINJECT_RING \ 699 CFG_INI_UINT("dp_reo_reinject_ring", \ 700 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \ 701 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \ 702 WLAN_CFG_REO_REINJECT_RING_SIZE, \ 703 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring") 704 705 #define CFG_DP_RX_RELEASE_RING \ 706 CFG_INI_UINT("dp_rx_release_ring", \ 707 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \ 708 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \ 709 WLAN_CFG_RX_RELEASE_RING_SIZE, \ 710 CFG_VALUE_OR_DEFAULT, "DP Rx release ring") 711 712 #define CFG_DP_REO_EXCEPTION_RING \ 713 CFG_INI_UINT("dp_reo_exception_ring", \ 714 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \ 715 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \ 716 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \ 717 CFG_VALUE_OR_DEFAULT, "DP REO exception ring") 718 719 #define CFG_DP_REO_CMD_RING \ 720 CFG_INI_UINT("dp_reo_cmd_ring", \ 721 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \ 722 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \ 723 WLAN_CFG_REO_CMD_RING_SIZE, \ 724 CFG_VALUE_OR_DEFAULT, "DP REO command ring") 725 726 #define CFG_DP_REO_STATUS_RING \ 727 CFG_INI_UINT("dp_reo_status_ring", \ 728 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \ 729 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \ 730 WLAN_CFG_REO_STATUS_RING_SIZE, \ 731 CFG_VALUE_OR_DEFAULT, "DP REO status ring") 732 733 #define CFG_DP_RXDMA_BUF_RING \ 734 CFG_INI_UINT("dp_rxdma_buf_ring", \ 735 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \ 736 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \ 737 WLAN_CFG_RXDMA_BUF_RING_SIZE, \ 738 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring") 739 740 #define CFG_DP_RXDMA_REFILL_RING \ 741 CFG_INI_UINT("dp_rxdma_refill_ring", \ 742 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \ 743 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \ 744 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \ 745 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring") 746 747 #define CFG_DP_TX_DESC_LIMIT_0 \ 748 CFG_INI_UINT("dp_tx_desc_limit_0", \ 749 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \ 750 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \ 751 WLAN_CFG_TX_DESC_LIMIT_0, \ 752 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0") 753 754 #define CFG_DP_TX_DESC_LIMIT_1 \ 755 CFG_INI_UINT("dp_tx_desc_limit_1", \ 756 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \ 757 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \ 758 WLAN_CFG_TX_DESC_LIMIT_1, \ 759 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1") 760 761 #define CFG_DP_TX_DESC_LIMIT_2 \ 762 CFG_INI_UINT("dp_tx_desc_limit_2", \ 763 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \ 764 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \ 765 WLAN_CFG_TX_DESC_LIMIT_2, \ 766 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2") 767 768 #define CFG_DP_TX_DEVICE_LIMIT \ 769 CFG_INI_UINT("dp_tx_device_limit", \ 770 WLAN_CFG_TX_DEVICE_LIMIT_MIN, \ 771 WLAN_CFG_TX_DEVICE_LIMIT_MAX, \ 772 WLAN_CFG_TX_DEVICE_LIMIT, \ 773 CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit") 774 775 #define CFG_DP_TX_SW_INTERNODE_QUEUE \ 776 CFG_INI_UINT("dp_tx_sw_internode_queue", \ 777 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \ 778 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \ 779 WLAN_CFG_TX_SW_INTERNODE_QUEUE, \ 780 CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue") 781 782 #define CFG_DP_RXDMA_MONITOR_BUF_RING \ 783 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \ 784 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \ 785 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \ 786 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \ 787 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring") 788 789 #define CFG_DP_RXDMA_MONITOR_DST_RING \ 790 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \ 791 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \ 792 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \ 793 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \ 794 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 795 796 #define CFG_DP_RXDMA_MONITOR_STATUS_RING \ 797 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \ 798 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \ 799 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \ 800 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \ 801 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring") 802 803 #define CFG_DP_RXDMA_MONITOR_DESC_RING \ 804 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \ 805 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \ 806 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \ 807 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \ 808 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 809 810 #define CFG_DP_RXDMA_ERR_DST_RING \ 811 CFG_INI_UINT("dp_rxdma_err_dst_ring", \ 812 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \ 813 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \ 814 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \ 815 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring") 816 817 #define CFG_DP_PER_PKT_LOGGING \ 818 CFG_INI_UINT("enable_verbose_debug", \ 819 0, 0xffff, 0, \ 820 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging") 821 822 #define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \ 823 CFG_INI_UINT("TxFlowStartQueueOffset", \ 824 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \ 825 CFG_VALUE_OR_DEFAULT, "Start queue offset") 826 827 #define CFG_DP_TX_FLOW_STOP_QUEUE_TH \ 828 CFG_INI_UINT("TxFlowStopQueueThreshold", \ 829 0, 50, 15, \ 830 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold") 831 832 #define CFG_DP_IPA_UC_TX_BUF_SIZE \ 833 CFG_INI_UINT("IpaUcTxBufSize", \ 834 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \ 835 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size") 836 837 #define CFG_DP_IPA_UC_TX_PARTITION_BASE \ 838 CFG_INI_UINT("IpaUcTxPartitionBase", \ 839 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \ 840 CFG_VALUE_OR_DEFAULT, "IPA tx partition base") 841 842 #define CFG_DP_IPA_UC_RX_IND_RING_COUNT \ 843 CFG_INI_UINT("IpaUcRxIndRingCount", \ 844 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \ 845 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count") 846 847 #define CFG_DP_REORDER_OFFLOAD_SUPPORT \ 848 CFG_INI_UINT("gReorderOffloadSupported", \ 849 0, 1, 1, \ 850 CFG_VALUE_OR_DEFAULT, "Packet reordering offload to firmware") 851 852 #define CFG_DP_AP_STA_SECURITY_SEPERATION \ 853 CFG_INI_BOOL("gDisableIntraBssFwd", \ 854 false, "Disable intrs BSS Rx packets") 855 856 #define CFG_DP_ENABLE_DATA_STALL_DETECTION \ 857 CFG_INI_BOOL("gEnableDataStallDetection", \ 858 true, "Enable/Disable Data stall detection") 859 860 #define CFG_DP_RX_SW_DESC_WEIGHT \ 861 CFG_INI_UINT("dp_rx_sw_desc_weight", \ 862 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN, \ 863 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX, \ 864 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE, \ 865 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC weight") 866 867 #define CFG_DP_RX_SW_DESC_NUM \ 868 CFG_INI_UINT("dp_rx_sw_desc_num", \ 869 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN, \ 870 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX, \ 871 WLAN_CFG_RX_SW_DESC_NUM_SIZE, \ 872 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC num") 873 874 #define CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE \ 875 CFG_INI_UINT("dp_rx_flow_search_table_size", \ 876 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN, \ 877 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX, \ 878 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE, \ 879 CFG_VALUE_OR_DEFAULT, \ 880 "DP Rx Flow Search Table Size in number of entries") 881 882 #define CFG_DP_RX_FLOW_TAG_ENABLE \ 883 CFG_INI_BOOL("dp_rx_flow_tag_enable", false, \ 884 "Enable/Disable DP Rx Flow Tag") 885 886 #define CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV \ 887 CFG_INI_BOOL("dp_rx_per_pdev_flow_search", false, \ 888 "DP Rx Flow Search Table Is Per PDev") 889 890 #define CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE \ 891 CFG_INI_BOOL("dp_rx_monitor_protocol_flow_tag_enable", true, \ 892 "Enable/Disable Rx Protocol & Flow tags in Monitor mode") 893 894 /* 895 * <ini> 896 * dp_rx_fisa_enable - Control Rx datapath FISA 897 * @Min: 0 898 * @Max: 1 899 * @Default: 0 900 * 901 * This ini is used to enable DP Rx FISA feature 902 * 903 * Related: dp_rx_flow_search_table_size 904 * 905 * Supported Feature: STA,P2P and SAP IPA disabled terminating 906 * 907 * Usage: Internal/External 908 * 909 * </ini> 910 */ 911 #define CFG_DP_RX_FISA_ENABLE \ 912 CFG_INI_BOOL("dp_rx_fisa_enable", false, \ 913 "Enable/Disable DP Rx FISA") 914 915 #define CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD \ 916 CFG_INI_UINT("mon_drop_thresh", \ 917 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN, \ 918 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX, \ 919 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE, \ 920 CFG_VALUE_OR_DEFAULT, "RXDMA monitor rx drop theshold") 921 922 #define CFG_DP_PKTLOG_BUFFER_SIZE \ 923 CFG_INI_UINT("PktlogBufSize", \ 924 WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE, \ 925 WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE, \ 926 WLAN_CFG_PKTLOG_BUFFER_SIZE, \ 927 CFG_VALUE_OR_DEFAULT, "Packet Log buffer size") 928 929 #define CFG_DP_FULL_MON_MODE \ 930 CFG_INI_BOOL("full_mon_mode", \ 931 false, "Full Monitor mode support") 932 933 #define CFG_DP_REO_RINGS_MAP \ 934 CFG_INI_UINT("dp_reo_rings_map", \ 935 WLAN_CFG_NUM_REO_RINGS_MAP_MIN, \ 936 WLAN_CFG_NUM_REO_RINGS_MAP_MAX, \ 937 WLAN_CFG_NUM_REO_RINGS_MAP, \ 938 CFG_VALUE_OR_DEFAULT, "REO Destination Rings Mapping") 939 940 #define CFG_DP_PEER_EXT_STATS \ 941 CFG_INI_BOOL("peer_ext_stats", \ 942 false, "Peer extended stats") 943 944 #define CFG_DP_RX_BUFF_POOL_ENABLE \ 945 CFG_INI_BOOL("dp_rx_buff_prealloc_pool", false, \ 946 "Enable/Disable DP RX emergency buffer pool support") 947 948 #define CFG_DP \ 949 CFG(CFG_DP_HTT_PACKET_TYPE) \ 950 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \ 951 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \ 952 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \ 953 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \ 954 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \ 955 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \ 956 CFG(CFG_DP_MAX_ALLOC_SIZE) \ 957 CFG(CFG_DP_MAX_CLIENTS) \ 958 CFG(CFG_DP_MAX_PEER_ID) \ 959 CFG(CFG_DP_REO_DEST_RINGS) \ 960 CFG(CFG_DP_TCL_DATA_RINGS) \ 961 CFG(CFG_DP_TX_DESC) \ 962 CFG(CFG_DP_TX_EXT_DESC) \ 963 CFG(CFG_DP_TX_EXT_DESC_POOLS) \ 964 CFG(CFG_DP_PDEV_RX_RING) \ 965 CFG(CFG_DP_PDEV_TX_RING) \ 966 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \ 967 CFG(CFG_DP_TX_COMPL_RING_SIZE) \ 968 CFG(CFG_DP_TX_RING_SIZE) \ 969 CFG(CFG_DP_NSS_COMP_RING_SIZE) \ 970 CFG(CFG_DP_PDEV_LMAC_RING) \ 971 CFG(CFG_DP_BASE_HW_MAC_ID) \ 972 CFG(CFG_DP_RX_HASH) \ 973 CFG(CFG_DP_TSO) \ 974 CFG(CFG_DP_LRO) \ 975 CFG(CFG_DP_SG) \ 976 CFG(CFG_DP_GRO) \ 977 CFG(CFG_DP_OL_TX_CSUM) \ 978 CFG(CFG_DP_OL_RX_CSUM) \ 979 CFG(CFG_DP_RAWMODE) \ 980 CFG(CFG_DP_PEER_FLOW_CTRL) \ 981 CFG(CFG_DP_NAPI) \ 982 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \ 983 CFG(CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD) \ 984 CFG(CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD) \ 985 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \ 986 CFG(CFG_DP_WBM_RELEASE_RING) \ 987 CFG(CFG_DP_TCL_CMD_CREDIT_RING) \ 988 CFG(CFG_DP_TCL_STATUS_RING) \ 989 CFG(CFG_DP_REO_REINJECT_RING) \ 990 CFG(CFG_DP_RX_RELEASE_RING) \ 991 CFG(CFG_DP_REO_EXCEPTION_RING) \ 992 CFG(CFG_DP_REO_CMD_RING) \ 993 CFG(CFG_DP_REO_STATUS_RING) \ 994 CFG(CFG_DP_RXDMA_BUF_RING) \ 995 CFG(CFG_DP_RXDMA_REFILL_RING) \ 996 CFG(CFG_DP_TX_DESC_LIMIT_0) \ 997 CFG(CFG_DP_TX_DESC_LIMIT_1) \ 998 CFG(CFG_DP_TX_DESC_LIMIT_2) \ 999 CFG(CFG_DP_TX_DEVICE_LIMIT) \ 1000 CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \ 1001 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \ 1002 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \ 1003 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \ 1004 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \ 1005 CFG(CFG_DP_RXDMA_ERR_DST_RING) \ 1006 CFG(CFG_DP_PER_PKT_LOGGING) \ 1007 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \ 1008 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \ 1009 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \ 1010 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \ 1011 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \ 1012 CFG(CFG_DP_REORDER_OFFLOAD_SUPPORT) \ 1013 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \ 1014 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) \ 1015 CFG(CFG_DP_RX_SW_DESC_WEIGHT) \ 1016 CFG(CFG_DP_RX_SW_DESC_NUM) \ 1017 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE) \ 1018 CFG(CFG_DP_RX_FLOW_TAG_ENABLE) \ 1019 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV) \ 1020 CFG(CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE) \ 1021 CFG(CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD) \ 1022 CFG(CFG_DP_PKTLOG_BUFFER_SIZE) \ 1023 CFG(CFG_DP_RX_FISA_ENABLE) \ 1024 CFG(CFG_DP_FULL_MON_MODE) \ 1025 CFG(CFG_DP_REO_RINGS_MAP) \ 1026 CFG(CFG_DP_PEER_EXT_STATS) \ 1027 CFG(CFG_DP_RX_BUFF_POOL_ENABLE) \ 1028 CFG(CFG_DP_RX_PENDING_HL_THRESHOLD) \ 1029 CFG(CFG_DP_RX_PENDING_LO_THRESHOLD) 1030 1031 #endif /* _CFG_DP_H_ */ 1032