1 /* 2 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /** 20 * DOC: This file contains definitions of Data Path configuration. 21 */ 22 23 #ifndef _CFG_DP_H_ 24 #define _CFG_DP_H_ 25 26 #include "cfg_define.h" 27 #include "wlan_init_cfg.h" 28 29 #define WLAN_CFG_MAX_CLIENTS 64 30 #define WLAN_CFG_MAX_CLIENTS_MIN 8 31 #define WLAN_CFG_MAX_CLIENTS_MAX 64 32 33 /* Change this to a lower value to enforce scattered idle list mode */ 34 #define WLAN_CFG_MAX_ALLOC_SIZE 0x200000 35 #define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000 36 #define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000 37 38 #if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \ 39 defined(QCA_LL_PDEV_TX_FLOW_CONTROL) 40 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10 41 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15 42 #else 43 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 44 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 45 #endif 46 47 #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0 48 #define WLAN_CFG_PER_PDEV_TX_RING_MAX 1 49 50 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 51 #define WLAN_CFG_PER_PDEV_RX_RING 0 52 #define WLAN_CFG_PER_PDEV_LMAC_RING 0 53 #define WLAN_LRO_ENABLE 0 54 #ifdef QCA_WIFI_QCA6750 55 #define WLAN_CFG_MAC_PER_TARGET 1 56 #else 57 #define WLAN_CFG_MAC_PER_TARGET 2 58 #endif 59 #ifdef IPA_OFFLOAD 60 /* Size of TCL TX Ring */ 61 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 62 #define WLAN_CFG_TX_RING_SIZE 2048 63 #else 64 #define WLAN_CFG_TX_RING_SIZE 1024 65 #endif 66 67 #define WLAN_CFG_IPA_TX_RING_SIZE_MIN 1024 68 #define WLAN_CFG_IPA_TX_RING_SIZE 1024 69 #define WLAN_CFG_IPA_TX_RING_SIZE_MAX 8096 70 71 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN 1024 72 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE 1024 73 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX 8096 74 75 #ifdef IPA_WDI3_TX_TWO_PIPES 76 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN 1024 77 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE 1024 78 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX 8096 79 80 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN 1024 81 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE 1024 82 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX 8096 83 #endif 84 85 #define WLAN_CFG_PER_PDEV_TX_RING 0 86 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048 87 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000 88 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024 89 #else 90 #define WLAN_CFG_TX_RING_SIZE 512 91 #define WLAN_CFG_PER_PDEV_TX_RING 1 92 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 93 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 94 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 95 #endif 96 97 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 98 #define WLAN_CFG_TX_COMP_RING_SIZE 4096 99 100 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 101 #define WLAN_CFG_NUM_TX_DESC 4096 102 #define WLAN_CFG_NUM_TX_EXT_DESC 4096 103 #else 104 #define WLAN_CFG_TX_COMP_RING_SIZE 1024 105 106 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 107 #define WLAN_CFG_NUM_TX_DESC 1024 108 #define WLAN_CFG_NUM_TX_EXT_DESC 1024 109 #endif 110 111 /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 112 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1 113 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 114 115 /* Interrupt Mitigation - Timer threshold in us */ 116 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8 117 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8 118 119 #ifdef WLAN_DP_PER_RING_TYPE_CONFIG 120 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX \ 121 WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 122 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX \ 123 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 124 #else 125 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1 126 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8 127 #endif 128 #endif 129 130 #ifdef NBUF_MEMORY_DEBUG 131 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0xFFFF 132 #else 133 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0x1FFFF 134 #endif 135 136 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD \ 137 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 138 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN 0 139 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX 0x200000 140 141 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD \ 142 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 143 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN 100 144 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX 0x200000 145 146 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256 147 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 512 148 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 0 149 150 #define WLAN_CFG_PER_PDEV_RX_RING_MIN 0 151 #define WLAN_CFG_PER_PDEV_RX_RING_MAX 0 152 153 #define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0 154 #define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1 155 156 #define WLAN_CFG_TX_RING_SIZE_MIN 512 157 #define WLAN_CFG_TX_RING_SIZE_MAX 0x80000 158 159 #define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512 160 #define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000 161 162 #define WLAN_CFG_NUM_TX_DESC_MIN 16 163 #define WLAN_CFG_NUM_TX_DESC_MAX 32768 164 165 #define WLAN_CFG_NUM_TX_EXT_DESC_MIN 16 166 #define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000 167 168 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1 169 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256 170 171 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 0 172 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128 173 174 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1 175 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128 176 177 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1 178 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128 179 180 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1 181 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1 182 183 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8 184 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 1000 185 186 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8 187 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500 188 189 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8 190 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000 191 192 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8 193 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 512 194 195 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8 196 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500 197 198 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000 199 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000 200 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000 201 202 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 203 204 /* Per vdev pools */ 205 #define WLAN_CFG_NUM_TX_DESC_POOL 3 206 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 207 208 #else /* QCA_LL_TX_FLOW_CONTROL_V2 */ 209 210 #ifdef TX_PER_PDEV_DESC_POOL 211 #define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT 212 #define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT 213 214 #else /* TX_PER_PDEV_DESC_POOL */ 215 216 #define WLAN_CFG_NUM_TX_DESC_POOL 3 217 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 218 219 #endif /* TX_PER_PDEV_DESC_POOL */ 220 #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */ 221 222 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1 223 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4 224 225 #define WLAN_CFG_HTT_PKT_TYPE 2 226 #define WLAN_CFG_HTT_PKT_TYPE_MIN 2 227 #define WLAN_CFG_HTT_PKT_TYPE_MAX 2 228 229 #define WLAN_CFG_MAX_PEER_ID 64 230 #define WLAN_CFG_MAX_PEER_ID_MIN 64 231 #define WLAN_CFG_MAX_PEER_ID_MAX 64 232 233 #define WLAN_CFG_RX_DEFRAG_TIMEOUT 100 234 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100 235 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100 236 237 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 238 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3 239 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX MAX_TCL_DATA_RINGS 240 241 #if defined(CONFIG_BERYLLIUM) 242 #define WLAN_CFG_NUM_REO_DEST_RING 8 243 #else 244 #define WLAN_CFG_NUM_REO_DEST_RING 4 245 #endif 246 #define WLAN_CFG_NUM_REO_DEST_RING_MIN 4 247 #define WLAN_CFG_NUM_REO_DEST_RING_MAX MAX_REO_DEST_RINGS 248 249 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS 2 250 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN 1 251 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX 3 252 253 #define WLAN_CFG_NSS_NUM_REO_DEST_RING 2 254 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN 1 255 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX 3 256 257 #define WLAN_CFG_WBM_RELEASE_RING_SIZE 1024 258 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64 259 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 1024 260 261 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE 32 262 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN 32 263 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX 32 264 265 #define WLAN_CFG_TCL_STATUS_RING_SIZE 32 266 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32 267 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32 268 269 #if defined(QCA_WIFI_QCA6290) 270 #define WLAN_CFG_REO_DST_RING_SIZE 1024 271 #else 272 #define WLAN_CFG_REO_DST_RING_SIZE 2048 273 #endif 274 275 #define WLAN_CFG_REO_DST_RING_SIZE_MIN 8 276 #define WLAN_CFG_REO_DST_RING_SIZE_MAX 8192 277 278 #define WLAN_CFG_REO_REINJECT_RING_SIZE 128 279 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32 280 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 128 281 282 #define WLAN_CFG_RX_RELEASE_RING_SIZE 1024 283 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8 284 #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 285 defined(QCA_WIFI_QCA6750) || defined(QCA_WIFI_WCN7850) 286 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024 287 #else 288 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 8192 289 #endif 290 291 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE 256 292 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128 293 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 512 294 295 #define WLAN_CFG_REO_CMD_RING_SIZE 128 296 #define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64 297 #define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128 298 299 #define WLAN_CFG_REO_STATUS_RING_SIZE 256 300 #define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128 301 #define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048 302 303 #define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024 304 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024 305 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 1024 306 307 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096 308 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16 309 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 4096 310 311 #define WLAN_CFG_TX_DESC_LIMIT_0 0 312 #define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096 313 #define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768 314 315 #define WLAN_CFG_TX_DESC_LIMIT_1 0 316 #define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096 317 #define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768 318 319 #define WLAN_CFG_TX_DESC_LIMIT_2 0 320 #define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096 321 #define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768 322 323 #define WLAN_CFG_TX_DEVICE_LIMIT 65536 324 #define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384 325 #define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536 326 327 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024 328 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128 329 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024 330 331 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096 332 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16 333 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192 334 335 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048 336 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48 337 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192 338 339 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024 340 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16 341 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192 342 343 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096 344 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096 345 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384 346 347 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024 348 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024 349 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192 350 351 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE 32 352 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN 0 353 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX 256 354 355 /** 356 * Allocate as many RX descriptors as buffers in the SW2RXDMA 357 * ring. This value may need to be tuned later. 358 */ 359 #if defined(QCA_HOST2FW_RXBUF_RING) 360 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 361 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 362 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 1 363 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 364 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 365 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 4096 366 367 /** 368 * For low memory AP cases using 1 will reduce the rx descriptors memory req 369 */ 370 #elif defined(QCA_LOWMEM_CONFIG) || defined(QCA_512M_CONFIG) 371 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 372 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 373 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 374 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 375 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 376 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 12288 377 378 /** 379 * AP use cases need to allocate more RX Descriptors than the number of 380 * entries avaialable in the SW2RXDMA buffer replenish ring. This is to account 381 * for frames sitting in REO queues, HW-HW DMA rings etc. Hence using a 382 * multiplication factor of 3, to allocate three times as many RX descriptors 383 * as RX buffers. 384 */ 385 #else 386 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 3 387 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 388 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 389 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 12288 390 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 4096 391 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 12288 392 #endif //QCA_HOST2FW_RXBUF_RING 393 394 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE 16384 395 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN 1 396 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX 16384 397 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT 128 398 399 #define WLAN_CFG_PKTLOG_BUFFER_SIZE 10 400 #define WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE 1 401 #define WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE 10 402 403 #ifdef QCA_WIFI_WCN7850 404 #define WLAN_CFG_NUM_REO_RINGS_MAP 0x7 405 #else 406 #define WLAN_CFG_NUM_REO_RINGS_MAP 0xF 407 #endif 408 #define WLAN_CFG_NUM_REO_RINGS_MAP_MIN 0x1 409 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xF 410 411 #define WLAN_CFG_RADIO_0_DEFAULT_REO 0x1 412 #define WLAN_CFG_RADIO_1_DEFAULT_REO 0x2 413 #define WLAN_CFG_RADIO_2_DEFAULT_REO 0x3 414 415 #define WLAN_CFG_RADIO_DEFAULT_REO_MIN 0x1 416 #define WLAN_CFG_RADIO_DEFAULT_REO_MAX 0x4 417 418 #define WLAN_CFG_REO2PPE_RING_SIZE 1024 419 #define WLAN_CFG_REO2PPE_RING_SIZE_MIN 64 420 #define WLAN_CFG_REO2PPE_RING_SIZE_MAX 1024 421 422 #define WLAN_CFG_PPE2TCL_RING_SIZE 1024 423 #define WLAN_CFG_PPE2TCL_RING_SIZE_MIN 64 424 #define WLAN_CFG_PPE2TCL_RING_SIZE_MAX 1024 425 426 #define WLAN_CFG_PPE_RELEASE_RING_SIZE 1024 427 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MIN 64 428 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MAX 1024 429 430 /* DP INI Declerations */ 431 #define CFG_DP_HTT_PACKET_TYPE \ 432 CFG_INI_UINT("dp_htt_packet_type", \ 433 WLAN_CFG_HTT_PKT_TYPE_MIN, \ 434 WLAN_CFG_HTT_PKT_TYPE_MAX, \ 435 WLAN_CFG_HTT_PKT_TYPE, \ 436 CFG_VALUE_OR_DEFAULT, "DP HTT packet type") 437 438 #define CFG_DP_INT_BATCH_THRESHOLD_OTHER \ 439 CFG_INI_UINT("dp_int_batch_threshold_other", \ 440 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \ 441 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \ 442 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \ 443 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other") 444 445 #define CFG_DP_INT_BATCH_THRESHOLD_RX \ 446 CFG_INI_UINT("dp_int_batch_threshold_rx", \ 447 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \ 448 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \ 449 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \ 450 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx") 451 452 #define CFG_DP_INT_BATCH_THRESHOLD_TX \ 453 CFG_INI_UINT("dp_int_batch_threshold_tx", \ 454 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \ 455 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \ 456 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \ 457 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx") 458 459 #define CFG_DP_INT_TIMER_THRESHOLD_OTHER \ 460 CFG_INI_UINT("dp_int_timer_threshold_other", \ 461 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \ 462 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \ 463 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \ 464 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other") 465 466 #define CFG_DP_INT_TIMER_THRESHOLD_RX \ 467 CFG_INI_UINT("dp_int_timer_threshold_rx", \ 468 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \ 469 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \ 470 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \ 471 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx") 472 473 #define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \ 474 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \ 475 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \ 476 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \ 477 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \ 478 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring") 479 480 #define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \ 481 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \ 482 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \ 483 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \ 484 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \ 485 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring") 486 487 #define CFG_DP_INT_TIMER_THRESHOLD_TX \ 488 CFG_INI_UINT("dp_int_timer_threshold_tx", \ 489 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \ 490 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \ 491 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \ 492 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx") 493 494 #define CFG_DP_MAX_ALLOC_SIZE \ 495 CFG_INI_UINT("dp_max_alloc_size", \ 496 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \ 497 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \ 498 WLAN_CFG_MAX_ALLOC_SIZE, \ 499 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size") 500 501 #define CFG_DP_MAX_CLIENTS \ 502 CFG_INI_UINT("dp_max_clients", \ 503 WLAN_CFG_MAX_CLIENTS_MIN, \ 504 WLAN_CFG_MAX_CLIENTS_MAX, \ 505 WLAN_CFG_MAX_CLIENTS, \ 506 CFG_VALUE_OR_DEFAULT, "DP Max Clients") 507 508 #define CFG_DP_MAX_PEER_ID \ 509 CFG_INI_UINT("dp_max_peer_id", \ 510 WLAN_CFG_MAX_PEER_ID_MIN, \ 511 WLAN_CFG_MAX_PEER_ID_MAX, \ 512 WLAN_CFG_MAX_PEER_ID, \ 513 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID") 514 515 #define CFG_DP_REO_DEST_RINGS \ 516 CFG_INI_UINT("dp_reo_dest_rings", \ 517 WLAN_CFG_NUM_REO_DEST_RING_MIN, \ 518 WLAN_CFG_NUM_REO_DEST_RING_MAX, \ 519 WLAN_CFG_NUM_REO_DEST_RING, \ 520 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings") 521 522 #define CFG_DP_TCL_DATA_RINGS \ 523 CFG_INI_UINT("dp_tcl_data_rings", \ 524 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \ 525 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \ 526 WLAN_CFG_NUM_TCL_DATA_RINGS, \ 527 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings") 528 529 #define CFG_DP_NSS_REO_DEST_RINGS \ 530 CFG_INI_UINT("dp_nss_reo_dest_rings", \ 531 WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN, \ 532 WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX, \ 533 WLAN_CFG_NSS_NUM_REO_DEST_RING, \ 534 CFG_VALUE_OR_DEFAULT, "DP NSS REO Destination Rings") 535 536 #define CFG_DP_NSS_TCL_DATA_RINGS \ 537 CFG_INI_UINT("dp_nss_tcl_data_rings", \ 538 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN, \ 539 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX, \ 540 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS, \ 541 CFG_VALUE_OR_DEFAULT, "DP NSS TCL Data Rings") 542 543 #define CFG_DP_TX_DESC \ 544 CFG_INI_UINT("dp_tx_desc", \ 545 WLAN_CFG_NUM_TX_DESC_MIN, \ 546 WLAN_CFG_NUM_TX_DESC_MAX, \ 547 WLAN_CFG_NUM_TX_DESC, \ 548 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors") 549 550 #define CFG_DP_TX_EXT_DESC \ 551 CFG_INI_UINT("dp_tx_ext_desc", \ 552 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \ 553 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \ 554 WLAN_CFG_NUM_TX_EXT_DESC, \ 555 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors") 556 557 #define CFG_DP_TX_EXT_DESC_POOLS \ 558 CFG_INI_UINT("dp_tx_ext_desc_pool", \ 559 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \ 560 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \ 561 WLAN_CFG_NUM_TXEXT_DESC_POOL, \ 562 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool") 563 564 #define CFG_DP_PDEV_RX_RING \ 565 CFG_INI_UINT("dp_pdev_rx_ring", \ 566 WLAN_CFG_PER_PDEV_RX_RING_MIN, \ 567 WLAN_CFG_PER_PDEV_RX_RING_MAX, \ 568 WLAN_CFG_PER_PDEV_RX_RING, \ 569 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring") 570 571 #define CFG_DP_PDEV_TX_RING \ 572 CFG_INI_UINT("dp_pdev_tx_ring", \ 573 WLAN_CFG_PER_PDEV_TX_RING_MIN, \ 574 WLAN_CFG_PER_PDEV_TX_RING_MAX, \ 575 WLAN_CFG_PER_PDEV_TX_RING, \ 576 CFG_VALUE_OR_DEFAULT, \ 577 "DP PDEV Tx Ring") 578 579 #define CFG_DP_RX_DEFRAG_TIMEOUT \ 580 CFG_INI_UINT("dp_rx_defrag_timeout", \ 581 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \ 582 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \ 583 WLAN_CFG_RX_DEFRAG_TIMEOUT, \ 584 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout") 585 586 #define CFG_DP_TX_COMPL_RING_SIZE \ 587 CFG_INI_UINT("dp_tx_compl_ring_size", \ 588 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \ 589 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \ 590 WLAN_CFG_TX_COMP_RING_SIZE, \ 591 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size") 592 593 #define CFG_DP_TX_RING_SIZE \ 594 CFG_INI_UINT("dp_tx_ring_size", \ 595 WLAN_CFG_TX_RING_SIZE_MIN,\ 596 WLAN_CFG_TX_RING_SIZE_MAX,\ 597 WLAN_CFG_TX_RING_SIZE,\ 598 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size") 599 600 #define CFG_DP_NSS_COMP_RING_SIZE \ 601 CFG_INI_UINT("dp_nss_comp_ring_size", \ 602 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \ 603 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \ 604 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \ 605 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size") 606 607 #define CFG_DP_PDEV_LMAC_RING \ 608 CFG_INI_UINT("dp_pdev_lmac_ring", \ 609 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \ 610 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \ 611 WLAN_CFG_PER_PDEV_LMAC_RING, \ 612 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring") 613 /* 614 * <ini> 615 * dp_rx_pending_hl_threshold - High threshold of frame number to start 616 * frame dropping scheme 617 * @Min: 0 618 * @Max: 524288 619 * @Default: 393216 620 * 621 * This ini entry is used to set a high limit threshold to start frame 622 * dropping scheme 623 * 624 * Usage: External 625 * 626 * </ini> 627 */ 628 #define CFG_DP_RX_PENDING_HL_THRESHOLD \ 629 CFG_INI_UINT("dp_rx_pending_hl_threshold", \ 630 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN, \ 631 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX, \ 632 WLAN_CFG_RX_PENDING_HL_THRESHOLD, \ 633 CFG_VALUE_OR_DEFAULT, "DP rx pending hl threshold") 634 635 /* 636 * <ini> 637 * dp_rx_pending_lo_threshold - Low threshold of frame number to stop 638 * frame dropping scheme 639 * @Min: 100 640 * @Max: 524288 641 * @Default: 393216 642 * 643 * This ini entry is used to set a low limit threshold to stop frame 644 * dropping scheme 645 * 646 * Usage: External 647 * 648 * </ini> 649 */ 650 #define CFG_DP_RX_PENDING_LO_THRESHOLD \ 651 CFG_INI_UINT("dp_rx_pending_lo_threshold", \ 652 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN, \ 653 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX, \ 654 WLAN_CFG_RX_PENDING_LO_THRESHOLD, \ 655 CFG_VALUE_OR_DEFAULT, "DP rx pending lo threshold") 656 657 #define CFG_DP_BASE_HW_MAC_ID \ 658 CFG_INI_UINT("dp_base_hw_macid", \ 659 0, 1, 1, \ 660 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID") 661 662 #define CFG_DP_RX_HASH \ 663 CFG_INI_BOOL("dp_rx_hash", true, \ 664 "DP Rx Hash") 665 666 #define CFG_DP_TSO \ 667 CFG_INI_BOOL("TSOEnable", false, \ 668 "DP TSO Enabled") 669 670 #define CFG_DP_LRO \ 671 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \ 672 "DP LRO Enable") 673 674 /* 675 * <ini> 676 * CFG_DP_SG - Enable the SG feature standalonely 677 * @Min: 0 678 * @Max: 1 679 * @Default: 1 680 * 681 * This ini entry is used to enable/disable SG feature standalonely. 682 * Also does Rome support SG on TX, lithium does not. 683 * For example the lithium does not support SG on UDP frames. 684 * Which is able to handle SG only for TSO frames(in case TSO is enabled). 685 * 686 * Usage: External 687 * 688 * </ini> 689 */ 690 #define CFG_DP_SG \ 691 CFG_INI_BOOL("dp_sg_support", false, \ 692 "DP SG Enable") 693 694 #define CFG_DP_GRO \ 695 CFG_INI_BOOL("GROEnable", false, \ 696 "DP GRO Enable") 697 698 #define CFG_DP_OL_TX_CSUM \ 699 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \ 700 "DP tx csum Enable") 701 702 #define CFG_DP_OL_RX_CSUM \ 703 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \ 704 "DP rx csum Enable") 705 706 #define CFG_DP_RAWMODE \ 707 CFG_INI_BOOL("dp_rawmode_support", false, \ 708 "DP rawmode Enable") 709 710 #define CFG_DP_PEER_FLOW_CTRL \ 711 CFG_INI_BOOL("dp_peer_flow_control_support", false, \ 712 "DP peer flow ctrl Enable") 713 714 #define CFG_DP_NAPI \ 715 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \ 716 "DP Napi Enabled") 717 /* 718 * <ini> 719 * gEnableP2pIpTcpUdpChecksumOffload - Enable checksum offload for P2P mode 720 * @Min: 0 721 * @Max: 1 722 * @Default: 1 723 * 724 * This ini entry is used to enable/disable TX checksum(UDP/TCP) for P2P modes. 725 * This includes P2P device mode, P2P client mode and P2P GO mode. 726 * The feature is enabled by default. To disable TX checksum for P2P, add the 727 * following entry in ini file: 728 * gEnableP2pIpTcpUdpChecksumOffload=0 729 * 730 * Usage: External 731 * 732 * </ini> 733 */ 734 #define CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD \ 735 CFG_INI_BOOL("gEnableP2pIpTcpUdpChecksumOffload", true, \ 736 "DP TCP UDP Checksum Offload for P2P mode (device/cli/go)") 737 738 /* 739 * <ini> 740 * gEnableNanIpTcpUdpChecksumOffload - Enable checksum offload for NAN mode 741 * @Min: 0 742 * @Max: 1 743 * @Default: 1 744 * 745 * Usage: External 746 * 747 * </ini> 748 */ 749 #define CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD \ 750 CFG_INI_BOOL("gEnableNanIpTcpUdpChecksumOffload", true, \ 751 "DP TCP UDP Checksum Offload for NAN mode") 752 753 /* 754 * <ini> 755 * gEnableIpTcpUdpChecksumOffload - Enable checksum offload 756 * @Min: 0 757 * @Max: 1 758 * @Default: 1 759 * 760 * Usage: External 761 * 762 * </ini> 763 */ 764 #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \ 765 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \ 766 "DP TCP UDP Checksum Offload") 767 768 #define CFG_DP_DEFRAG_TIMEOUT_CHECK \ 769 CFG_INI_BOOL("dp_defrag_timeout_check", true, \ 770 "DP Defrag Timeout Check") 771 772 #define CFG_DP_WBM_RELEASE_RING \ 773 CFG_INI_UINT("dp_wbm_release_ring", \ 774 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \ 775 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \ 776 WLAN_CFG_WBM_RELEASE_RING_SIZE, \ 777 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring") 778 779 #define CFG_DP_TCL_CMD_CREDIT_RING \ 780 CFG_INI_UINT("dp_tcl_cmd_credit_ring", \ 781 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN, \ 782 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX, \ 783 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE, \ 784 CFG_VALUE_OR_DEFAULT, "DP TCL Cmd_Credit ring") 785 786 #define CFG_DP_TCL_STATUS_RING \ 787 CFG_INI_UINT("dp_tcl_status_ring",\ 788 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \ 789 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \ 790 WLAN_CFG_TCL_STATUS_RING_SIZE, \ 791 CFG_VALUE_OR_DEFAULT, "DP TCL status ring") 792 793 #define CFG_DP_REO_REINJECT_RING \ 794 CFG_INI_UINT("dp_reo_reinject_ring", \ 795 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \ 796 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \ 797 WLAN_CFG_REO_REINJECT_RING_SIZE, \ 798 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring") 799 800 #define CFG_DP_RX_RELEASE_RING \ 801 CFG_INI_UINT("dp_rx_release_ring", \ 802 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \ 803 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \ 804 WLAN_CFG_RX_RELEASE_RING_SIZE, \ 805 CFG_VALUE_OR_DEFAULT, "DP Rx release ring") 806 807 #define CFG_DP_RX_DESTINATION_RING \ 808 CFG_INI_UINT("dp_reo_dst_ring", \ 809 WLAN_CFG_REO_DST_RING_SIZE_MIN, \ 810 WLAN_CFG_REO_DST_RING_SIZE_MAX, \ 811 WLAN_CFG_REO_DST_RING_SIZE, \ 812 CFG_VALUE_OR_DEFAULT, "DP REO destination ring") 813 814 #define CFG_DP_REO_EXCEPTION_RING \ 815 CFG_INI_UINT("dp_reo_exception_ring", \ 816 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \ 817 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \ 818 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \ 819 CFG_VALUE_OR_DEFAULT, "DP REO exception ring") 820 821 #define CFG_DP_REO_CMD_RING \ 822 CFG_INI_UINT("dp_reo_cmd_ring", \ 823 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \ 824 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \ 825 WLAN_CFG_REO_CMD_RING_SIZE, \ 826 CFG_VALUE_OR_DEFAULT, "DP REO command ring") 827 828 #define CFG_DP_REO_STATUS_RING \ 829 CFG_INI_UINT("dp_reo_status_ring", \ 830 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \ 831 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \ 832 WLAN_CFG_REO_STATUS_RING_SIZE, \ 833 CFG_VALUE_OR_DEFAULT, "DP REO status ring") 834 835 #define CFG_DP_RXDMA_BUF_RING \ 836 CFG_INI_UINT("dp_rxdma_buf_ring", \ 837 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \ 838 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \ 839 WLAN_CFG_RXDMA_BUF_RING_SIZE, \ 840 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring") 841 842 #define CFG_DP_RXDMA_REFILL_RING \ 843 CFG_INI_UINT("dp_rxdma_refill_ring", \ 844 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \ 845 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \ 846 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \ 847 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring") 848 849 #define CFG_DP_TX_DESC_LIMIT_0 \ 850 CFG_INI_UINT("dp_tx_desc_limit_0", \ 851 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \ 852 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \ 853 WLAN_CFG_TX_DESC_LIMIT_0, \ 854 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0") 855 856 #define CFG_DP_TX_DESC_LIMIT_1 \ 857 CFG_INI_UINT("dp_tx_desc_limit_1", \ 858 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \ 859 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \ 860 WLAN_CFG_TX_DESC_LIMIT_1, \ 861 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1") 862 863 #define CFG_DP_TX_DESC_LIMIT_2 \ 864 CFG_INI_UINT("dp_tx_desc_limit_2", \ 865 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \ 866 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \ 867 WLAN_CFG_TX_DESC_LIMIT_2, \ 868 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2") 869 870 #define CFG_DP_TX_DEVICE_LIMIT \ 871 CFG_INI_UINT("dp_tx_device_limit", \ 872 WLAN_CFG_TX_DEVICE_LIMIT_MIN, \ 873 WLAN_CFG_TX_DEVICE_LIMIT_MAX, \ 874 WLAN_CFG_TX_DEVICE_LIMIT, \ 875 CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit") 876 877 #define CFG_DP_TX_SW_INTERNODE_QUEUE \ 878 CFG_INI_UINT("dp_tx_sw_internode_queue", \ 879 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \ 880 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \ 881 WLAN_CFG_TX_SW_INTERNODE_QUEUE, \ 882 CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue") 883 884 #define CFG_DP_RXDMA_MONITOR_BUF_RING \ 885 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \ 886 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \ 887 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \ 888 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \ 889 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring") 890 891 #define CFG_DP_RXDMA_MONITOR_DST_RING \ 892 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \ 893 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \ 894 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \ 895 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \ 896 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 897 898 #define CFG_DP_RXDMA_MONITOR_STATUS_RING \ 899 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \ 900 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \ 901 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \ 902 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \ 903 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring") 904 905 #define CFG_DP_RXDMA_MONITOR_DESC_RING \ 906 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \ 907 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \ 908 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \ 909 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \ 910 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 911 912 #define CFG_DP_RXDMA_ERR_DST_RING \ 913 CFG_INI_UINT("dp_rxdma_err_dst_ring", \ 914 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \ 915 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \ 916 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \ 917 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring") 918 919 #define CFG_DP_PER_PKT_LOGGING \ 920 CFG_INI_UINT("enable_verbose_debug", \ 921 0, 0xffff, 0, \ 922 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging") 923 924 #define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \ 925 CFG_INI_UINT("TxFlowStartQueueOffset", \ 926 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \ 927 CFG_VALUE_OR_DEFAULT, "Start queue offset") 928 929 #define CFG_DP_TX_FLOW_STOP_QUEUE_TH \ 930 CFG_INI_UINT("TxFlowStopQueueThreshold", \ 931 0, 50, 15, \ 932 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold") 933 934 #define CFG_DP_IPA_UC_TX_BUF_SIZE \ 935 CFG_INI_UINT("IpaUcTxBufSize", \ 936 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \ 937 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size") 938 939 #define CFG_DP_IPA_UC_TX_PARTITION_BASE \ 940 CFG_INI_UINT("IpaUcTxPartitionBase", \ 941 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \ 942 CFG_VALUE_OR_DEFAULT, "IPA tx partition base") 943 944 #define CFG_DP_IPA_UC_RX_IND_RING_COUNT \ 945 CFG_INI_UINT("IpaUcRxIndRingCount", \ 946 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \ 947 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count") 948 949 #define CFG_DP_AP_STA_SECURITY_SEPERATION \ 950 CFG_INI_BOOL("gDisableIntraBssFwd", \ 951 false, "Disable intrs BSS Rx packets") 952 953 #define CFG_DP_ENABLE_DATA_STALL_DETECTION \ 954 CFG_INI_BOOL("gEnableDataStallDetection", \ 955 true, "Enable/Disable Data stall detection") 956 957 #define CFG_DP_RX_SW_DESC_WEIGHT \ 958 CFG_INI_UINT("dp_rx_sw_desc_weight", \ 959 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN, \ 960 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX, \ 961 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE, \ 962 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC weight") 963 964 #define CFG_DP_RX_SW_DESC_NUM \ 965 CFG_INI_UINT("dp_rx_sw_desc_num", \ 966 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN, \ 967 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX, \ 968 WLAN_CFG_RX_SW_DESC_NUM_SIZE, \ 969 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC num") 970 971 #define CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE \ 972 CFG_INI_UINT("dp_rx_flow_search_table_size", \ 973 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN, \ 974 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX, \ 975 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT, \ 976 CFG_VALUE_OR_DEFAULT, \ 977 "DP Rx Flow Search Table Size in number of entries") 978 979 #define CFG_DP_RX_FLOW_TAG_ENABLE \ 980 CFG_INI_BOOL("dp_rx_flow_tag_enable", false, \ 981 "Enable/Disable DP Rx Flow Tag") 982 983 #define CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV \ 984 CFG_INI_BOOL("dp_rx_per_pdev_flow_search", false, \ 985 "DP Rx Flow Search Table Is Per PDev") 986 987 #define CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE \ 988 CFG_INI_BOOL("dp_rx_monitor_protocol_flow_tag_enable", true, \ 989 "Enable/Disable Rx Protocol & Flow tags in Monitor mode") 990 991 #define CFG_DP_TX_PER_PKT_VDEV_ID_CHECK \ 992 CFG_INI_BOOL("dp_tx_allow_per_pkt_vdev_id_check", false, \ 993 "Enable/Disable tx Per Pkt vdev id check") 994 995 /* 996 * <ini> 997 * dp_rx_fisa_enable - Control Rx datapath FISA 998 * @Min: 0 999 * @Max: 1 1000 * @Default: 1 1001 * 1002 * This ini is used to enable DP Rx FISA feature 1003 * 1004 * Related: dp_rx_flow_search_table_size 1005 * 1006 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1007 * 1008 * Usage: Internal 1009 * 1010 * </ini> 1011 */ 1012 #define CFG_DP_RX_FISA_ENABLE \ 1013 CFG_INI_BOOL("dp_rx_fisa_enable", true, \ 1014 "Enable/Disable DP Rx FISA") 1015 1016 #define CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD \ 1017 CFG_INI_UINT("mon_drop_thresh", \ 1018 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN, \ 1019 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX, \ 1020 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE, \ 1021 CFG_VALUE_OR_DEFAULT, "RXDMA monitor rx drop theshold") 1022 1023 #define CFG_DP_PKTLOG_BUFFER_SIZE \ 1024 CFG_INI_UINT("PktlogBufSize", \ 1025 WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE, \ 1026 WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE, \ 1027 WLAN_CFG_PKTLOG_BUFFER_SIZE, \ 1028 CFG_VALUE_OR_DEFAULT, "Packet Log buffer size") 1029 1030 #define CFG_DP_FULL_MON_MODE \ 1031 CFG_INI_BOOL("full_mon_mode", \ 1032 false, "Full Monitor mode support") 1033 1034 #define CFG_DP_REO_RINGS_MAP \ 1035 CFG_INI_UINT("dp_reo_rings_map", \ 1036 WLAN_CFG_NUM_REO_RINGS_MAP_MIN, \ 1037 WLAN_CFG_NUM_REO_RINGS_MAP_MAX, \ 1038 WLAN_CFG_NUM_REO_RINGS_MAP, \ 1039 CFG_VALUE_OR_DEFAULT, "REO Destination Rings Mapping") 1040 1041 #define CFG_DP_RX_RADIO_0_DEFAULT_REO \ 1042 CFG_INI_UINT("dp_rx_radio0_default_reo", \ 1043 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1044 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1045 WLAN_CFG_RADIO_0_DEFAULT_REO, \ 1046 CFG_VALUE_OR_DEFAULT, "Radio0 to REO destination default mapping") 1047 1048 #define CFG_DP_RX_RADIO_1_DEFAULT_REO \ 1049 CFG_INI_UINT("dp_rx_radio1_default_reo", \ 1050 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1051 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1052 WLAN_CFG_RADIO_1_DEFAULT_REO, \ 1053 CFG_VALUE_OR_DEFAULT, "Radio1 to REO destination default mapping") 1054 1055 #define CFG_DP_RX_RADIO_2_DEFAULT_REO \ 1056 CFG_INI_UINT("dp_rx_radio2_default_reo", \ 1057 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1058 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1059 WLAN_CFG_RADIO_2_DEFAULT_REO, \ 1060 CFG_VALUE_OR_DEFAULT, "Radio2 to REO destination default mapping") 1061 1062 #define CFG_DP_PEER_EXT_STATS \ 1063 CFG_INI_BOOL("peer_ext_stats", \ 1064 false, "Peer extended stats") 1065 /* 1066 * <ini> 1067 * legacy_mode_csum_disable - Disable csum offload for legacy 802.11abg modes 1068 * @Min: 0 1069 * @Max: 1 1070 * @Default: Default value indicating if checksum should be disabled for 1071 * legacy WLAN modes 1072 * 1073 * This ini is used to disable HW checksum offload capability for legacy 1074 * connections 1075 * 1076 * Related: gEnableIpTcpUdpChecksumOffload should be enabled 1077 * 1078 * Usage: Internal 1079 * 1080 * </ini> 1081 */ 1082 #ifndef DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1083 #define DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1 1084 #endif 1085 1086 #define CFG_DP_LEGACY_MODE_CSUM_DISABLE \ 1087 CFG_INI_BOOL("legacy_mode_csum_disable", \ 1088 DP_LEGACY_MODE_CSM_DEFAULT_DISABLE, \ 1089 "Enable/Disable legacy mode checksum") 1090 1091 #define CFG_DP_RX_BUFF_POOL_ENABLE \ 1092 CFG_INI_BOOL("dp_rx_buff_prealloc_pool", false, \ 1093 "Enable/Disable DP RX emergency buffer pool support") 1094 1095 #define CFG_DP_RX_REFILL_BUFF_POOL_ENABLE \ 1096 CFG_INI_BOOL("dp_rx_refill_buff_pool", false, \ 1097 "Enable/Disable DP RX refill buffer pool support") 1098 1099 #define CFG_DP_POLL_MODE_ENABLE \ 1100 CFG_INI_BOOL("dp_poll_mode_enable", false, \ 1101 "Enable/Disable Polling mode for data path") 1102 1103 #define CFG_DP_RX_FST_IN_CMEM \ 1104 CFG_INI_BOOL("dp_rx_fst_in_cmem", false, \ 1105 "Enable/Disable flow search table in CMEM") 1106 /* 1107 * <ini> 1108 * gEnableSWLM - Control DP Software latency manager 1109 * @Min: 0 1110 * @Max: 1 1111 * @Default: 0 1112 * 1113 * This ini is used to enable DP Software latency Manager 1114 * 1115 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1116 * 1117 * Usage: Internal 1118 * 1119 * </ini> 1120 */ 1121 #define CFG_DP_SWLM_ENABLE \ 1122 CFG_INI_BOOL("gEnableSWLM", false, \ 1123 "Enable/Disable DP SWLM") 1124 /* 1125 * <ini> 1126 * wow_check_rx_pending_enable - control to check RX frames pending in Wow 1127 * @Min: 0 1128 * @Max: 1 1129 * @Default: 0 1130 * 1131 * This ini is used to control DP Software to perform RX pending check 1132 * before entering WoW mode 1133 * 1134 * Usage: Internal 1135 * 1136 * </ini> 1137 */ 1138 #define CFG_DP_WOW_CHECK_RX_PENDING \ 1139 CFG_INI_BOOL("wow_check_rx_pending_enable", \ 1140 false, \ 1141 "enable rx frame pending check in WoW mode") 1142 #define CFG_DP_DELAY_MON_REPLENISH \ 1143 CFG_INI_BOOL("delay_mon_replenish", \ 1144 true, "Delay Monitor Replenish") 1145 1146 /* 1147 * <ini> 1148 * gForceRX64BA - enable force 64 blockack mode for RX 1149 * @Min: 0 1150 * @Max: 1 1151 * @Default: 0 1152 * 1153 * This ini is used to control DP Software to use 64 blockack 1154 * for RX direction forcibly 1155 * 1156 * Usage: Internal 1157 * 1158 * </ini> 1159 */ 1160 #define CFG_FORCE_RX_64_BA \ 1161 CFG_INI_BOOL("gForceRX64BA", \ 1162 false, "Enable/Disable force 64 blockack in RX side") 1163 1164 /* 1165 * <ini> 1166 * ghw_cc_enable - enable HW cookie conversion by register 1167 * @Min: 0 1168 * @Max: 1 1169 * @Default: 1 1170 * 1171 * This ini is used to control HW based 20 bits cookie to 64 bits 1172 * Desc virtual address conversion 1173 * 1174 * Usage: Internal 1175 * 1176 * </ini> 1177 */ 1178 #define CFG_DP_HW_CC_ENABLE \ 1179 CFG_INI_BOOL("ghw_cc_enable", \ 1180 true, "Enable/Disable HW cookie conversion") 1181 1182 #ifdef IPA_OFFLOAD 1183 /* 1184 * <ini> 1185 * dp_ipa_tx_ring_size - Set tcl ring size for IPA 1186 * @Min: 1024 1187 * @Max: 8096 1188 * @Default: 1024 1189 * 1190 * This ini sets the tcl ring size for IPA 1191 * 1192 * Related: N/A 1193 * 1194 * Supported Feature: IPA 1195 * 1196 * Usage: Internal 1197 * 1198 * </ini> 1199 */ 1200 #define CFG_DP_IPA_TX_RING_SIZE \ 1201 CFG_INI_UINT("dp_ipa_tx_ring_size", \ 1202 WLAN_CFG_IPA_TX_RING_SIZE_MIN, \ 1203 WLAN_CFG_IPA_TX_RING_SIZE_MAX, \ 1204 WLAN_CFG_IPA_TX_RING_SIZE, \ 1205 CFG_VALUE_OR_DEFAULT, "IPA TCL ring size") 1206 1207 /* 1208 * <ini> 1209 * dp_ipa_tx_comp_ring_size - Set tx comp ring size for IPA 1210 * @Min: 1024 1211 * @Max: 8096 1212 * @Default: 1024 1213 * 1214 * This ini sets the tx comp ring size for IPA 1215 * 1216 * Related: N/A 1217 * 1218 * Supported Feature: IPA 1219 * 1220 * Usage: Internal 1221 * 1222 * </ini> 1223 */ 1224 #define CFG_DP_IPA_TX_COMP_RING_SIZE \ 1225 CFG_INI_UINT("dp_ipa_tx_comp_ring_size", \ 1226 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN, \ 1227 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX, \ 1228 WLAN_CFG_IPA_TX_COMP_RING_SIZE, \ 1229 CFG_VALUE_OR_DEFAULT, "IPA tx comp ring size") 1230 1231 #ifdef IPA_WDI3_TX_TWO_PIPES 1232 /* 1233 * <ini> 1234 * dp_ipa_tx_alt_ring_size - Set alt tcl ring size for IPA 1235 * @Min: 1024 1236 * @Max: 8096 1237 * @Default: 1024 1238 * 1239 * This ini sets the alt tcl ring size for IPA 1240 * 1241 * Related: N/A 1242 * 1243 * Supported Feature: IPA 1244 * 1245 * Usage: Internal 1246 * 1247 * </ini> 1248 */ 1249 #define CFG_DP_IPA_TX_ALT_RING_SIZE \ 1250 CFG_INI_UINT("dp_ipa_tx_alt_ring_size", \ 1251 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN, \ 1252 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX, \ 1253 WLAN_CFG_IPA_TX_ALT_RING_SIZE, \ 1254 CFG_VALUE_OR_DEFAULT, \ 1255 "DP IPA TX Alternative Ring Size") 1256 1257 /* 1258 * <ini> 1259 * dp_ipa_tx_alt_comp_ring_size - Set tx alt comp ring size for IPA 1260 * @Min: 1024 1261 * @Max: 8096 1262 * @Default: 1024 1263 * 1264 * This ini sets the tx alt comp ring size for IPA 1265 * 1266 * Related: N/A 1267 * 1268 * Supported Feature: IPA 1269 * 1270 * Usage: Internal 1271 * 1272 * </ini> 1273 */ 1274 #define CFG_DP_IPA_TX_ALT_COMP_RING_SIZE \ 1275 CFG_INI_UINT("dp_ipa_tx_alt_comp_ring_size", \ 1276 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN, \ 1277 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX, \ 1278 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE, \ 1279 CFG_VALUE_OR_DEFAULT, \ 1280 "DP IPA TX Alternative Completion Ring Size") 1281 1282 #define CFG_DP_IPA_TX_ALT_RING_CFG \ 1283 CFG(CFG_DP_IPA_TX_ALT_RING_SIZE) \ 1284 CFG(CFG_DP_IPA_TX_ALT_COMP_RING_SIZE) 1285 1286 #else 1287 #define CFG_DP_IPA_TX_ALT_RING_CFG 1288 #endif 1289 1290 #define CFG_DP_IPA_TX_RING_CFG \ 1291 CFG(CFG_DP_IPA_TX_RING_SIZE) \ 1292 CFG(CFG_DP_IPA_TX_COMP_RING_SIZE) 1293 #else 1294 #define CFG_DP_IPA_TX_RING_CFG 1295 #define CFG_DP_IPA_TX_ALT_RING_CFG 1296 #endif 1297 1298 #ifdef WLAN_SUPPORT_PPEDS 1299 #define CFG_DP_PPE_ENABLE \ 1300 CFG_INI_BOOL("ppe_enable", false, \ 1301 "DP ppe enable flag") 1302 1303 #define CFG_DP_REO2PPE_RING \ 1304 CFG_INI_UINT("dp_reo2ppe_ring", \ 1305 WLAN_CFG_REO2PPE_RING_SIZE_MIN, \ 1306 WLAN_CFG_REO2PPE_RING_SIZE_MAX, \ 1307 WLAN_CFG_REO2PPE_RING_SIZE, \ 1308 CFG_VALUE_OR_DEFAULT, "DP REO2PPE ring") 1309 1310 #define CFG_DP_PPE2TCL_RING \ 1311 CFG_INI_UINT("dp_ppe2tcl_ring", \ 1312 WLAN_CFG_PPE2TCL_RING_SIZE_MIN, \ 1313 WLAN_CFG_PPE2TCL_RING_SIZE_MAX, \ 1314 WLAN_CFG_PPE2TCL_RING_SIZE, \ 1315 CFG_VALUE_OR_DEFAULT, "DP PPE2TCL rings") 1316 1317 #define CFG_DP_PPE_RELEASE_RING \ 1318 CFG_INI_UINT("dp_ppe_release_ring", \ 1319 WLAN_CFG_PPE_RELEASE_RING_SIZE_MIN, \ 1320 WLAN_CFG_PPE_RELEASE_RING_SIZE_MAX, \ 1321 WLAN_CFG_PPE_RELEASE_RING_SIZE, \ 1322 CFG_VALUE_OR_DEFAULT, "DP PPE Release Ring") 1323 1324 #define CFG_DP_PPE_CONFIG \ 1325 CFG(CFG_DP_PPE_ENABLE) \ 1326 CFG(CFG_DP_REO2PPE_RING) \ 1327 CFG(CFG_DP_PPE2TCL_RING) \ 1328 CFG(CFG_DP_PPE_RELEASE_RING) 1329 #else 1330 #define CFG_DP_PPE_CONFIG 1331 #endif 1332 1333 #define CFG_DP \ 1334 CFG(CFG_DP_HTT_PACKET_TYPE) \ 1335 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \ 1336 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \ 1337 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \ 1338 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \ 1339 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \ 1340 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \ 1341 CFG(CFG_DP_MAX_ALLOC_SIZE) \ 1342 CFG(CFG_DP_MAX_CLIENTS) \ 1343 CFG(CFG_DP_MAX_PEER_ID) \ 1344 CFG(CFG_DP_REO_DEST_RINGS) \ 1345 CFG(CFG_DP_TCL_DATA_RINGS) \ 1346 CFG(CFG_DP_NSS_REO_DEST_RINGS) \ 1347 CFG(CFG_DP_NSS_TCL_DATA_RINGS) \ 1348 CFG(CFG_DP_TX_DESC) \ 1349 CFG(CFG_DP_TX_EXT_DESC) \ 1350 CFG(CFG_DP_TX_EXT_DESC_POOLS) \ 1351 CFG(CFG_DP_PDEV_RX_RING) \ 1352 CFG(CFG_DP_PDEV_TX_RING) \ 1353 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \ 1354 CFG(CFG_DP_TX_COMPL_RING_SIZE) \ 1355 CFG(CFG_DP_TX_RING_SIZE) \ 1356 CFG(CFG_DP_NSS_COMP_RING_SIZE) \ 1357 CFG(CFG_DP_PDEV_LMAC_RING) \ 1358 CFG(CFG_DP_BASE_HW_MAC_ID) \ 1359 CFG(CFG_DP_RX_HASH) \ 1360 CFG(CFG_DP_TSO) \ 1361 CFG(CFG_DP_LRO) \ 1362 CFG(CFG_DP_SG) \ 1363 CFG(CFG_DP_GRO) \ 1364 CFG(CFG_DP_OL_TX_CSUM) \ 1365 CFG(CFG_DP_OL_RX_CSUM) \ 1366 CFG(CFG_DP_RAWMODE) \ 1367 CFG(CFG_DP_PEER_FLOW_CTRL) \ 1368 CFG(CFG_DP_NAPI) \ 1369 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \ 1370 CFG(CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD) \ 1371 CFG(CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD) \ 1372 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \ 1373 CFG(CFG_DP_WBM_RELEASE_RING) \ 1374 CFG(CFG_DP_TCL_CMD_CREDIT_RING) \ 1375 CFG(CFG_DP_TCL_STATUS_RING) \ 1376 CFG(CFG_DP_REO_REINJECT_RING) \ 1377 CFG(CFG_DP_RX_RELEASE_RING) \ 1378 CFG(CFG_DP_REO_EXCEPTION_RING) \ 1379 CFG(CFG_DP_RX_DESTINATION_RING) \ 1380 CFG(CFG_DP_REO_CMD_RING) \ 1381 CFG(CFG_DP_REO_STATUS_RING) \ 1382 CFG(CFG_DP_RXDMA_BUF_RING) \ 1383 CFG(CFG_DP_RXDMA_REFILL_RING) \ 1384 CFG(CFG_DP_TX_DESC_LIMIT_0) \ 1385 CFG(CFG_DP_TX_DESC_LIMIT_1) \ 1386 CFG(CFG_DP_TX_DESC_LIMIT_2) \ 1387 CFG(CFG_DP_TX_DEVICE_LIMIT) \ 1388 CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \ 1389 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \ 1390 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \ 1391 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \ 1392 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \ 1393 CFG(CFG_DP_RXDMA_ERR_DST_RING) \ 1394 CFG(CFG_DP_PER_PKT_LOGGING) \ 1395 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \ 1396 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \ 1397 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \ 1398 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \ 1399 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \ 1400 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \ 1401 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) \ 1402 CFG(CFG_DP_RX_SW_DESC_WEIGHT) \ 1403 CFG(CFG_DP_RX_SW_DESC_NUM) \ 1404 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE) \ 1405 CFG(CFG_DP_RX_FLOW_TAG_ENABLE) \ 1406 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV) \ 1407 CFG(CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE) \ 1408 CFG(CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD) \ 1409 CFG(CFG_DP_PKTLOG_BUFFER_SIZE) \ 1410 CFG(CFG_DP_RX_FISA_ENABLE) \ 1411 CFG(CFG_DP_FULL_MON_MODE) \ 1412 CFG(CFG_DP_REO_RINGS_MAP) \ 1413 CFG(CFG_DP_PEER_EXT_STATS) \ 1414 CFG(CFG_DP_RX_BUFF_POOL_ENABLE) \ 1415 CFG(CFG_DP_RX_REFILL_BUFF_POOL_ENABLE) \ 1416 CFG(CFG_DP_RX_PENDING_HL_THRESHOLD) \ 1417 CFG(CFG_DP_RX_PENDING_LO_THRESHOLD) \ 1418 CFG(CFG_DP_LEGACY_MODE_CSUM_DISABLE) \ 1419 CFG(CFG_DP_POLL_MODE_ENABLE) \ 1420 CFG(CFG_DP_SWLM_ENABLE) \ 1421 CFG(CFG_DP_TX_PER_PKT_VDEV_ID_CHECK) \ 1422 CFG(CFG_DP_RX_FST_IN_CMEM) \ 1423 CFG(CFG_DP_RX_RADIO_0_DEFAULT_REO) \ 1424 CFG(CFG_DP_RX_RADIO_1_DEFAULT_REO) \ 1425 CFG(CFG_DP_RX_RADIO_2_DEFAULT_REO) \ 1426 CFG(CFG_DP_WOW_CHECK_RX_PENDING) \ 1427 CFG(CFG_DP_HW_CC_ENABLE) \ 1428 CFG(CFG_FORCE_RX_64_BA) \ 1429 CFG(CFG_DP_DELAY_MON_REPLENISH) \ 1430 CFG_DP_IPA_TX_RING_CFG \ 1431 CFG_DP_PPE_CONFIG \ 1432 CFG_DP_IPA_TX_ALT_RING_CFG 1433 #endif /* _CFG_DP_H_ */ 1434