1 /* 2 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * DOC: This file contains definitions of Data Path configuration. 22 */ 23 24 #ifndef _CFG_DP_H_ 25 #define _CFG_DP_H_ 26 27 #include "cfg_define.h" 28 #include "wlan_init_cfg.h" 29 30 #define WLAN_CFG_MAX_CLIENTS 64 31 #define WLAN_CFG_MAX_CLIENTS_MIN 8 32 #define WLAN_CFG_MAX_CLIENTS_MAX 64 33 34 /* Change this to a lower value to enforce scattered idle list mode */ 35 #define WLAN_CFG_MAX_ALLOC_SIZE 0x200000 36 #define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000 37 #define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000 38 39 #if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \ 40 defined(QCA_LL_PDEV_TX_FLOW_CONTROL) 41 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10 42 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15 43 #else 44 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 45 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 46 #endif 47 48 #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0 49 #define WLAN_CFG_PER_PDEV_TX_RING_MAX 1 50 51 #ifdef IPA_OFFLOAD 52 /* Size of TCL TX Ring */ 53 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 54 #define WLAN_CFG_TX_RING_SIZE 2048 55 #else 56 #define WLAN_CFG_TX_RING_SIZE 1024 57 #endif 58 59 #define WLAN_CFG_IPA_TX_RING_SIZE_MIN 512 60 #define WLAN_CFG_IPA_TX_RING_SIZE 1024 61 #define WLAN_CFG_IPA_TX_RING_SIZE_MAX 0x80000 62 63 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN 512 64 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE 1024 65 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX 0x80000 66 67 #ifdef IPA_WDI3_TX_TWO_PIPES 68 #ifdef WLAN_MEMORY_OPT 69 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN 128 70 #else 71 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN 512 72 #endif 73 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE 1024 74 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX 0x80000 75 76 #ifdef WLAN_MEMORY_OPT 77 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN 128 78 #else 79 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN 512 80 #endif 81 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE 1024 82 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX 0x80000 83 #endif 84 85 #define WLAN_CFG_PER_PDEV_TX_RING 0 86 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048 87 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000 88 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024 89 #else 90 #define WLAN_CFG_TX_RING_SIZE 512 91 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 92 #define WLAN_CFG_PER_PDEV_TX_RING 1 93 #else 94 #define WLAN_CFG_PER_PDEV_TX_RING 0 95 #endif 96 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 97 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 98 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 99 #endif /* IPA_OFFLOAD */ 100 101 #define WLAN_CFG_TIME_CONTROL_BP 3000 102 103 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 104 #define WLAN_CFG_PER_PDEV_RX_RING 0 105 #define WLAN_CFG_PER_PDEV_LMAC_RING 0 106 #define WLAN_LRO_ENABLE 0 107 #ifdef QCA_WIFI_QCA6750 108 #define WLAN_CFG_MAC_PER_TARGET 1 109 #else 110 #define WLAN_CFG_MAC_PER_TARGET 2 111 #endif 112 113 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 114 #define WLAN_CFG_TX_COMP_RING_SIZE 4096 115 116 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 117 #define WLAN_CFG_NUM_TX_DESC 4096 118 #define WLAN_CFG_NUM_TX_EXT_DESC 4096 119 #else 120 #define WLAN_CFG_TX_COMP_RING_SIZE 1024 121 122 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 123 #define WLAN_CFG_NUM_TX_DESC 1024 124 #define WLAN_CFG_NUM_TX_EXT_DESC 1024 125 #endif 126 127 /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 128 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1 129 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 130 131 /* Interrupt Mitigation - Timer threshold in us */ 132 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8 133 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8 134 135 #ifdef WLAN_DP_PER_RING_TYPE_CONFIG 136 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX \ 137 WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 138 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX \ 139 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 140 #else 141 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1 142 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8 143 #endif 144 #endif /* WLAN_MAX_PDEVS */ 145 146 #define WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL 0 147 #define WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL 30 148 149 #ifdef NBUF_MEMORY_DEBUG 150 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0xFFFF 151 #else 152 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0x1FFFF 153 #endif 154 155 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD \ 156 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 157 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN 0 158 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX 0x200000 159 160 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD \ 161 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 162 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN 100 163 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX 0x200000 164 165 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256 166 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 512 167 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 0 168 169 #define WLAN_CFG_PER_PDEV_RX_RING_MIN 0 170 #define WLAN_CFG_PER_PDEV_RX_RING_MAX 0 171 172 #define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0 173 #define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1 174 175 #define WLAN_CFG_TX_RING_SIZE_MIN 512 176 #define WLAN_CFG_TX_RING_SIZE_MAX 0x80000 177 178 #define WLAN_CFG_TIME_CONTROL_BP_MIN 3000 179 #define WLAN_CFG_TIME_CONTROL_BP_MAX 1800000 180 181 #define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512 182 #define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000 183 184 #define WLAN_CFG_NUM_TX_DESC_MIN 16 185 #define WLAN_CFG_NUM_TX_DESC_MAX 0x10000 186 187 #define WLAN_CFG_NUM_TX_SPL_DESC 1024 188 #define WLAN_CFG_NUM_TX_SPL_DESC_MIN 0 189 #define WLAN_CFG_NUM_TX_SPL_DESC_MAX 0x1000 190 191 #define WLAN_CFG_NUM_TX_EXT_DESC_MIN 16 192 #define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000 193 194 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1 195 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256 196 197 #define WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MIN 0 198 #define WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MAX 1024 199 200 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 0 201 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128 202 203 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1 204 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128 205 206 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1 207 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128 208 209 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1 210 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1 211 212 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8 213 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 1000 214 215 #define WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MIN 8 216 #define WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MAX 1000 217 218 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8 219 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500 220 221 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8 222 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000 223 224 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8 225 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 512 226 227 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8 228 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500 229 230 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000 231 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000 232 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000 233 234 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 235 236 /* Per vdev pools */ 237 #define WLAN_CFG_NUM_TX_DESC_POOL 3 238 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 239 240 #else /* QCA_LL_TX_FLOW_CONTROL_V2 */ 241 242 #ifdef TX_PER_PDEV_DESC_POOL 243 #define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT 244 #define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT 245 246 #else /* TX_PER_PDEV_DESC_POOL */ 247 248 #define WLAN_CFG_NUM_TX_DESC_POOL 3 249 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 250 251 #endif /* TX_PER_PDEV_DESC_POOL */ 252 #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */ 253 254 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1 255 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4 256 257 #define WLAN_CFG_HTT_PKT_TYPE 2 258 #define WLAN_CFG_HTT_PKT_TYPE_MIN 2 259 #define WLAN_CFG_HTT_PKT_TYPE_MAX 2 260 261 #define WLAN_CFG_MAX_PEER_ID 64 262 #define WLAN_CFG_MAX_PEER_ID_MIN 64 263 #define WLAN_CFG_MAX_PEER_ID_MAX 64 264 265 #define WLAN_CFG_RX_DEFRAG_TIMEOUT 100 266 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100 267 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100 268 269 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 270 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 1 271 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX MAX_TCL_DATA_RINGS 272 273 #define WLAN_CFG_NUM_TX_COMP_RINGS WLAN_CFG_NUM_TCL_DATA_RINGS 274 #define WLAN_CFG_NUM_TX_COMP_RINGS_MIN WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 275 #define WLAN_CFG_NUM_TX_COMP_RINGS_MAX WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 276 277 #if defined(CONFIG_BERYLLIUM) 278 #define WLAN_CFG_NUM_REO_DEST_RING 8 279 #else 280 #define WLAN_CFG_NUM_REO_DEST_RING 4 281 #endif 282 #define WLAN_CFG_NUM_REO_DEST_RING_MIN 4 283 #define WLAN_CFG_NUM_REO_DEST_RING_MAX MAX_REO_DEST_RINGS 284 285 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS 2 286 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN 1 287 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX 3 288 289 #define WLAN_CFG_NSS_NUM_REO_DEST_RING 2 290 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN 1 291 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX 3 292 293 #define WLAN_CFG_WBM_RELEASE_RING_SIZE 1024 294 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64 295 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 1024 296 297 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE 512 298 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN 32 299 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX 512 300 301 #define WLAN_CFG_TCL_STATUS_RING_SIZE 32 302 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32 303 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32 304 305 #if defined(QCA_WIFI_QCA6290) 306 #define WLAN_CFG_REO_DST_RING_SIZE 1024 307 #else 308 #define WLAN_CFG_REO_DST_RING_SIZE 2048 309 #endif 310 311 #define WLAN_CFG_REO_DST_RING_SIZE_MIN 8 312 #define WLAN_CFG_REO_DST_RING_SIZE_MAX 8192 313 314 #define WLAN_CFG_REO_REINJECT_RING_SIZE 128 315 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32 316 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 128 317 318 #define WLAN_CFG_RX_RELEASE_RING_SIZE 1024 319 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8 320 #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 321 defined(QCA_WIFI_QCA6750) || defined(QCA_WIFI_KIWI) 322 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024 323 #else 324 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 32768 325 #endif 326 327 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE 256 328 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128 329 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 512 330 331 #define WLAN_CFG_REO_CMD_RING_SIZE 128 332 #define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64 333 #define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128 334 335 #define WLAN_CFG_REO_STATUS_RING_SIZE 256 336 #define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128 337 #define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048 338 339 #define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024 340 #ifdef WLAN_MEMORY_OPT 341 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 128 342 #else 343 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024 344 #endif 345 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 4096 346 347 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096 348 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16 349 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 16384 350 351 #define WLAN_CFG_TX_DESC_LIMIT_0 0 352 #define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096 353 #define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768 354 355 #define WLAN_CFG_TX_DESC_LIMIT_1 0 356 #define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096 357 #define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768 358 359 #define WLAN_CFG_TX_DESC_LIMIT_2 0 360 #define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096 361 #define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768 362 363 #define WLAN_CFG_TX_DEVICE_LIMIT 65536 364 #define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384 365 #define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536 366 367 #define WLAN_CFG_TX_SPL_DEVICE_LIMIT 1024 368 #define WLAN_CFG_TX_SPL_DEVICE_LIMIT_MIN 0 369 #define WLAN_CFG_TX_SPL_DEVICE_LIMIT_MAX 4096 370 371 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024 372 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128 373 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024 374 375 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096 376 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16 377 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192 378 379 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE 4096 380 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN 16 381 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX 8192 382 383 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048 384 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48 385 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192 386 387 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE 2048 388 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN 48 389 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX 8192 390 391 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024 392 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16 393 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192 394 395 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096 396 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096 397 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384 398 399 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024 400 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024 401 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192 402 403 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE 32 404 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN 0 405 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX 256 406 407 /* 408 * Allocate as many RX descriptors as buffers in the SW2RXDMA 409 * ring. This value may need to be tuned later. 410 */ 411 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 412 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 413 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 414 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 1 415 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 416 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 417 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 418 419 /* 420 * For low memory AP cases using 1 will reduce the rx descriptors memory req 421 */ 422 #elif defined(QCA_LOWMEM_CONFIG) || defined(QCA_512M_CONFIG) 423 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 424 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 425 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 426 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 427 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 428 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 429 430 /* 431 * AP use cases need to allocate more RX Descriptors than the number of 432 * entries available in the SW2RXDMA buffer replenish ring. This is to account 433 * for frames sitting in REO queues, HW-HW DMA rings etc. Hence using a 434 * multiplication factor of 3, to allocate three times as many RX descriptors 435 * as RX buffers. 436 */ 437 #else 438 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 3 439 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 440 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 441 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 12288 442 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 4096 443 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 444 #endif 445 446 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE 16384 447 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN 1 448 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX 16384 449 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT 128 450 451 #define WLAN_CFG_PKTLOG_BUFFER_SIZE 10 452 #define WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE 1 453 #define WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE 10 454 455 #ifdef IPA_OFFLOAD 456 #define WLAN_CFG_NUM_REO_RINGS_MAP 0x7 457 #else 458 #define WLAN_CFG_NUM_REO_RINGS_MAP 0xF 459 #endif 460 #define WLAN_CFG_NUM_REO_RINGS_MAP_MIN 0x1 461 #if defined(CONFIG_BERYLLIUM) 462 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xFF 463 #else 464 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xF 465 #endif 466 467 #define WLAN_CFG_RADIO_0_DEFAULT_REO 0x1 468 #define WLAN_CFG_RADIO_1_DEFAULT_REO 0x2 469 #define WLAN_CFG_RADIO_2_DEFAULT_REO 0x3 470 471 #define WLAN_CFG_RADIO_DEFAULT_REO_MIN 0x1 472 #define WLAN_CFG_RADIO_DEFAULT_REO_MAX 0x4 473 474 #define WLAN_CFG_REO2PPE_RING_SIZE 8192 475 #define WLAN_CFG_REO2PPE_RING_SIZE_MIN 64 476 #define WLAN_CFG_REO2PPE_RING_SIZE_MAX 16384 477 478 #define WLAN_CFG_PPE2TCL_RING_SIZE 8192 479 #define WLAN_CFG_PPE2TCL_RING_SIZE_MIN 64 480 #define WLAN_CFG_PPE2TCL_RING_SIZE_MAX 32768 481 482 #define WLAN_CFG_PPE_RELEASE_RING_SIZE 1024 483 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MIN 64 484 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MAX 1024 485 486 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 487 #define WLAN_CFG_MLO_RX_RING_MAP 0x7 488 #define WLAN_CFG_MLO_RX_RING_MAP_MIN 0x0 489 #define WLAN_CFG_MLO_RX_RING_MAP_MAX 0xFF 490 #endif 491 492 #define WLAN_CFG_TX_CAPT_MAX_MEM_MIN 0 493 #define WLAN_CFG_TX_CAPT_MAX_MEM_MAX 512 494 #define WLAN_CFG_TX_CAPT_MAX_MEM_DEFAULT 0 495 496 #define CFG_DP_MPDU_RETRY_THRESHOLD_MIN 0 497 #define CFG_DP_MPDU_RETRY_THRESHOLD_MAX 255 498 #define CFG_DP_MPDU_RETRY_THRESHOLD 0 499 500 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR 0 501 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR_MIN 0 502 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR_MAX 4 503 504 #ifdef CONFIG_SAWF_STATS 505 #define WLAN_CFG_SAWF_STATS 0x0 506 #define WLAN_CFG_SAWF_STATS_MIN 0x0 507 #define WLAN_CFG_SAWF_STATS_MAX 0x7 508 #endif 509 /* 510 * <ini> 511 * "dp_tx_capt_max_mem_mb"- maximum memory used by Tx capture 512 * @Min: 0 513 * @Max: 512 MB 514 * @Default: 0 (disabled) 515 * 516 * This ini entry is used to set a max limit beyond which frames 517 * are dropped by Tx capture. User needs to set a non-zero value 518 * to enable it. 519 * 520 * Usage: External 521 * 522 * </ini> 523 */ 524 #define CFG_DP_TX_CAPT_MAX_MEM_MB \ 525 CFG_INI_UINT("dp_tx_capt_max_mem_mb", \ 526 WLAN_CFG_TX_CAPT_MAX_MEM_MIN, \ 527 WLAN_CFG_TX_CAPT_MAX_MEM_MAX, \ 528 WLAN_CFG_TX_CAPT_MAX_MEM_DEFAULT, \ 529 CFG_VALUE_OR_DEFAULT, "Max Memory (in MB) used by Tx Capture") 530 531 /* DP INI Declarations */ 532 #define CFG_DP_HTT_PACKET_TYPE \ 533 CFG_INI_UINT("dp_htt_packet_type", \ 534 WLAN_CFG_HTT_PKT_TYPE_MIN, \ 535 WLAN_CFG_HTT_PKT_TYPE_MAX, \ 536 WLAN_CFG_HTT_PKT_TYPE, \ 537 CFG_VALUE_OR_DEFAULT, "DP HTT packet type") 538 539 #define CFG_DP_INT_BATCH_THRESHOLD_OTHER \ 540 CFG_INI_UINT("dp_int_batch_threshold_other", \ 541 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \ 542 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \ 543 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \ 544 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other") 545 546 #define CFG_DP_INT_BATCH_THRESHOLD_RX \ 547 CFG_INI_UINT("dp_int_batch_threshold_rx", \ 548 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \ 549 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \ 550 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \ 551 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx") 552 553 #define CFG_DP_INT_BATCH_THRESHOLD_TX \ 554 CFG_INI_UINT("dp_int_batch_threshold_tx", \ 555 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \ 556 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \ 557 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \ 558 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx") 559 560 #define CFG_DP_INT_BATCH_THRESHOLD_PPE2TCL \ 561 CFG_INI_UINT("dp_int_batch_threshold_ppe2tcl", \ 562 WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MIN, \ 563 WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MAX, \ 564 WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL, \ 565 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold ppe2tcl") 566 567 #define CFG_DP_INT_TIMER_THRESHOLD_PPE2TCL \ 568 CFG_INI_UINT("dp_int_timer_threshold_ppe2tcl", \ 569 WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MIN, \ 570 WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MAX, \ 571 WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL, \ 572 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold ppe2tcl") 573 574 #define CFG_DP_INT_TIMER_THRESHOLD_OTHER \ 575 CFG_INI_UINT("dp_int_timer_threshold_other", \ 576 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \ 577 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \ 578 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \ 579 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other") 580 581 #define CFG_DP_INT_TIMER_THRESHOLD_RX \ 582 CFG_INI_UINT("dp_int_timer_threshold_rx", \ 583 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \ 584 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \ 585 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \ 586 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx") 587 588 #define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \ 589 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \ 590 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \ 591 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \ 592 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \ 593 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring") 594 595 #define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \ 596 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \ 597 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \ 598 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \ 599 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \ 600 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring") 601 602 #define CFG_DP_INT_TIMER_THRESHOLD_TX \ 603 CFG_INI_UINT("dp_int_timer_threshold_tx", \ 604 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \ 605 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \ 606 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \ 607 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx") 608 609 #define CFG_DP_MAX_ALLOC_SIZE \ 610 CFG_INI_UINT("dp_max_alloc_size", \ 611 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \ 612 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \ 613 WLAN_CFG_MAX_ALLOC_SIZE, \ 614 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size") 615 616 #define CFG_DP_MAX_CLIENTS \ 617 CFG_INI_UINT("dp_max_clients", \ 618 WLAN_CFG_MAX_CLIENTS_MIN, \ 619 WLAN_CFG_MAX_CLIENTS_MAX, \ 620 WLAN_CFG_MAX_CLIENTS, \ 621 CFG_VALUE_OR_DEFAULT, "DP Max Clients") 622 623 #define CFG_DP_MAX_PEER_ID \ 624 CFG_INI_UINT("dp_max_peer_id", \ 625 WLAN_CFG_MAX_PEER_ID_MIN, \ 626 WLAN_CFG_MAX_PEER_ID_MAX, \ 627 WLAN_CFG_MAX_PEER_ID, \ 628 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID") 629 630 #define CFG_DP_REO_DEST_RINGS \ 631 CFG_INI_UINT("dp_reo_dest_rings", \ 632 WLAN_CFG_NUM_REO_DEST_RING_MIN, \ 633 WLAN_CFG_NUM_REO_DEST_RING_MAX, \ 634 WLAN_CFG_NUM_REO_DEST_RING, \ 635 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings") 636 637 #define CFG_DP_TX_COMP_RINGS \ 638 CFG_INI_UINT("dp_tx_comp_rings", \ 639 WLAN_CFG_NUM_TX_COMP_RINGS_MIN, \ 640 WLAN_CFG_NUM_TX_COMP_RINGS_MAX, \ 641 WLAN_CFG_NUM_TX_COMP_RINGS, \ 642 CFG_VALUE_OR_DEFAULT, "DP Tx Comp Rings") 643 644 #define CFG_DP_TCL_DATA_RINGS \ 645 CFG_INI_UINT("dp_tcl_data_rings", \ 646 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \ 647 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \ 648 WLAN_CFG_NUM_TCL_DATA_RINGS, \ 649 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings") 650 651 #define CFG_DP_NSS_REO_DEST_RINGS \ 652 CFG_INI_UINT("dp_nss_reo_dest_rings", \ 653 WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN, \ 654 WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX, \ 655 WLAN_CFG_NSS_NUM_REO_DEST_RING, \ 656 CFG_VALUE_OR_DEFAULT, "DP NSS REO Destination Rings") 657 658 #define CFG_DP_NSS_TCL_DATA_RINGS \ 659 CFG_INI_UINT("dp_nss_tcl_data_rings", \ 660 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN, \ 661 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX, \ 662 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS, \ 663 CFG_VALUE_OR_DEFAULT, "DP NSS TCL Data Rings") 664 665 #define CFG_DP_TX_DESC \ 666 CFG_INI_UINT("dp_tx_desc", \ 667 WLAN_CFG_NUM_TX_DESC_MIN, \ 668 WLAN_CFG_NUM_TX_DESC_MAX, \ 669 WLAN_CFG_NUM_TX_DESC, \ 670 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors") 671 672 #define CFG_DP_TX_SPL_DESC \ 673 CFG_INI_UINT("dp_tx_spl_desc", \ 674 WLAN_CFG_NUM_TX_SPL_DESC_MIN, \ 675 WLAN_CFG_NUM_TX_SPL_DESC_MAX, \ 676 WLAN_CFG_NUM_TX_SPL_DESC, \ 677 CFG_VALUE_OR_DEFAULT, "DP Tx Special Descriptors") 678 679 #define CFG_DP_TX_EXT_DESC \ 680 CFG_INI_UINT("dp_tx_ext_desc", \ 681 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \ 682 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \ 683 WLAN_CFG_NUM_TX_EXT_DESC, \ 684 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors") 685 686 #define CFG_DP_TX_EXT_DESC_POOLS \ 687 CFG_INI_UINT("dp_tx_ext_desc_pool", \ 688 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \ 689 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \ 690 WLAN_CFG_NUM_TXEXT_DESC_POOL, \ 691 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool") 692 693 #define CFG_DP_PDEV_RX_RING \ 694 CFG_INI_UINT("dp_pdev_rx_ring", \ 695 WLAN_CFG_PER_PDEV_RX_RING_MIN, \ 696 WLAN_CFG_PER_PDEV_RX_RING_MAX, \ 697 WLAN_CFG_PER_PDEV_RX_RING, \ 698 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring") 699 700 #define CFG_DP_PDEV_TX_RING \ 701 CFG_INI_UINT("dp_pdev_tx_ring", \ 702 WLAN_CFG_PER_PDEV_TX_RING_MIN, \ 703 WLAN_CFG_PER_PDEV_TX_RING_MAX, \ 704 WLAN_CFG_PER_PDEV_TX_RING, \ 705 CFG_VALUE_OR_DEFAULT, \ 706 "DP PDEV Tx Ring") 707 708 #define CFG_DP_RX_DEFRAG_TIMEOUT \ 709 CFG_INI_UINT("dp_rx_defrag_timeout", \ 710 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \ 711 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \ 712 WLAN_CFG_RX_DEFRAG_TIMEOUT, \ 713 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout") 714 715 #define CFG_DP_TX_COMPL_RING_SIZE \ 716 CFG_INI_UINT("dp_tx_compl_ring_size", \ 717 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \ 718 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \ 719 WLAN_CFG_TX_COMP_RING_SIZE, \ 720 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size") 721 722 #define CFG_DP_TX_RING_SIZE \ 723 CFG_INI_UINT("dp_tx_ring_size", \ 724 WLAN_CFG_TX_RING_SIZE_MIN,\ 725 WLAN_CFG_TX_RING_SIZE_MAX,\ 726 WLAN_CFG_TX_RING_SIZE,\ 727 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size") 728 729 #define CFG_DP_NSS_COMP_RING_SIZE \ 730 CFG_INI_UINT("dp_nss_comp_ring_size", \ 731 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \ 732 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \ 733 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \ 734 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size") 735 736 #define CFG_DP_PDEV_LMAC_RING \ 737 CFG_INI_UINT("dp_pdev_lmac_ring", \ 738 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \ 739 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \ 740 WLAN_CFG_PER_PDEV_LMAC_RING, \ 741 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring") 742 743 #define CFG_DP_TIME_CONTROL_BP \ 744 CFG_INI_UINT("dp_time_control_bp", \ 745 WLAN_CFG_TIME_CONTROL_BP_MIN,\ 746 WLAN_CFG_TIME_CONTROL_BP_MAX,\ 747 WLAN_CFG_TIME_CONTROL_BP,\ 748 CFG_VALUE_OR_DEFAULT, "DP time control back pressure") 749 750 #ifdef CONFIG_SAWF_STATS 751 #define CFG_DP_SAWF_STATS \ 752 CFG_INI_UINT("dp_sawf_stats", \ 753 WLAN_CFG_SAWF_STATS_MIN,\ 754 WLAN_CFG_SAWF_STATS_MAX,\ 755 WLAN_CFG_SAWF_STATS,\ 756 CFG_VALUE_OR_DEFAULT, "DP sawf stats config") 757 #define CFG_DP_SAWF_STATS_CONFIG CFG(CFG_DP_SAWF_STATS) 758 #else 759 #define CFG_DP_SAWF_STATS_CONFIG 760 #endif 761 762 /* 763 * <ini> 764 * dp_rx_pending_hl_threshold - High threshold of frame number to start 765 * frame dropping scheme 766 * @Min: 0 767 * @Max: 524288 768 * @Default: 393216 769 * 770 * This ini entry is used to set a high limit threshold to start frame 771 * dropping scheme 772 * 773 * Usage: External 774 * 775 * </ini> 776 */ 777 #define CFG_DP_RX_PENDING_HL_THRESHOLD \ 778 CFG_INI_UINT("dp_rx_pending_hl_threshold", \ 779 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN, \ 780 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX, \ 781 WLAN_CFG_RX_PENDING_HL_THRESHOLD, \ 782 CFG_VALUE_OR_DEFAULT, "DP rx pending hl threshold") 783 784 /* 785 * <ini> 786 * dp_rx_pending_lo_threshold - Low threshold of frame number to stop 787 * frame dropping scheme 788 * @Min: 100 789 * @Max: 524288 790 * @Default: 393216 791 * 792 * This ini entry is used to set a low limit threshold to stop frame 793 * dropping scheme 794 * 795 * Usage: External 796 * 797 * </ini> 798 */ 799 #define CFG_DP_RX_PENDING_LO_THRESHOLD \ 800 CFG_INI_UINT("dp_rx_pending_lo_threshold", \ 801 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN, \ 802 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX, \ 803 WLAN_CFG_RX_PENDING_LO_THRESHOLD, \ 804 CFG_VALUE_OR_DEFAULT, "DP rx pending lo threshold") 805 806 #define CFG_DP_BASE_HW_MAC_ID \ 807 CFG_INI_UINT("dp_base_hw_macid", \ 808 0, 1, 1, \ 809 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID") 810 811 #define CFG_DP_RX_HASH \ 812 CFG_INI_BOOL("dp_rx_hash", true, \ 813 "DP Rx Hash") 814 815 #define CFG_DP_TSO \ 816 CFG_INI_BOOL("TSOEnable", false, \ 817 "DP TSO Enabled") 818 819 #define CFG_DP_LRO \ 820 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \ 821 "DP LRO Enable") 822 823 #ifdef WLAN_USE_CONFIG_PARAMS 824 /* 825 * <ini> 826 * dp_tx_desc_use_512p - Use 512M tx descriptor size 827 * @Min: 0 828 * @Max: 1 829 * @Default: 0 830 * 831 * This ini entry is used as flag to use 512M tx descriptor size or not 832 * 833 * Usage: Internal 834 * 835 * </ini> 836 */ 837 #define CFG_DP_TX_DESC_512P \ 838 CFG_INI_BOOL("dp_tx_desc_use_512p", false, \ 839 "DP TX DESC PINE SPECIFIC") 840 841 /* 842 * <ini> 843 * dp_nss_3radio_ring - Use 3 Radio NSS comp ring size 844 * @Min: 0 845 * @Max: 1 846 * @Default: 0 847 * 848 * This ini entry is used as flag to use 3 Radio NSS com ring size or not 849 * 850 * Usage: Internal 851 * 852 * </ini> 853 */ 854 #define CFG_DP_NSS_3RADIO_RING \ 855 CFG_INI_BOOL("dp_nss_3radio_ring", false, \ 856 "DP NSS 3 RADIO RING SIZE") 857 858 /* 859 * <ini> 860 * dp_mon_ring_per_512M - Update monitor status ring as 512M profile 861 * @Min: 0 862 * @Max: 1 863 * @Default: 0 864 * 865 * This ini entry is used as flag to update monitor status ring as 512M profile 866 * 867 * Usage: Internal 868 * 869 * </ini> 870 */ 871 #define CFG_DP_MON_STATUS_512M \ 872 CFG_INI_BOOL("dp_mon_ring_per_512M", false, \ 873 "DP MON STATUS RING SIZE PER 512M PROFILE") 874 875 /* 876 * <ini> 877 * dp_mon_2chain_ring - Reduce monitor rings size as for 2 Chains case 878 * @Min: 0 879 * @Max: 1 880 * @Default: 0 881 * 882 * This ini entry is used as flag to reduce monitor rings size as those used 883 * in case of 2 Tx/RxChains 884 * 885 * Usage: Internal 886 * 887 * </ini> 888 */ 889 #define CFG_DP_MON_2CHAIN_RING \ 890 CFG_INI_BOOL("dp_mon_2chain_ring", false, \ 891 "DP MON UPDATE RINGS FOR 2CHAIN") 892 893 /* 894 * <ini> 895 * dp_mon_4chain_ring - Update monitor rings size for 4 Chains case 896 * @Min: 0 897 * @Max: 1 898 * @Default: 0 899 * 900 * This ini entry is used as flag to reduce monitor rings size as those used 901 * in case of 4 Tx/RxChains 902 * 903 * Usage: Internal 904 * 905 * </ini> 906 */ 907 #define CFG_DP_MON_4CHAIN_RING \ 908 CFG_INI_BOOL("dp_mon_4chain_ring", false, \ 909 "DP MON UPDATE RINGS FOR 4CHAIN") 910 911 /* 912 * <ini> 913 * dp_4radip_rdp_reo - Update RDP REO map based on 4 radio config 914 * @Min: 0 915 * @Max: 1 916 * @Default: 0 917 * 918 * This ini entry is used as flag to update RDP reo map based on 4 Radio config 919 * 920 * Usage: Internal 921 * 922 * </ini> 923 */ 924 #define CFG_DP_4RADIO_RDP_REO \ 925 CFG_INI_BOOL("dp_nss_4radio_rdp_reo", \ 926 false, "Update REO destination mapping for 4radio") 927 928 #define CFG_DP_INI_SECTION_PARAMS \ 929 CFG(CFG_DP_NSS_3RADIO_RING) \ 930 CFG(CFG_DP_TX_DESC_512P) \ 931 CFG(CFG_DP_MON_STATUS_512M) \ 932 CFG(CFG_DP_MON_2CHAIN_RING) \ 933 CFG(CFG_DP_MON_4CHAIN_RING) \ 934 CFG(CFG_DP_4RADIO_RDP_REO) 935 #else 936 #define CFG_DP_INI_SECTION_PARAMS 937 #endif 938 939 /* 940 * <ini> 941 * CFG_DP_SG - Enable the SG feature standalonely 942 * @Min: 0 943 * @Max: 1 944 * @Default: 1 945 * 946 * This ini entry is used to enable/disable SG feature standalonely. 947 * Also does Rome support SG on TX, lithium does not. 948 * For example the lithium does not support SG on UDP frames. 949 * Which is able to handle SG only for TSO frames(in case TSO is enabled). 950 * 951 * Usage: External 952 * 953 * </ini> 954 */ 955 #define CFG_DP_SG \ 956 CFG_INI_BOOL("dp_sg_support", false, \ 957 "DP SG Enable") 958 959 #define WLAN_CFG_GRO_ENABLE_MIN 0 960 #define WLAN_CFG_GRO_ENABLE_MAX 3 961 #define WLAN_CFG_GRO_ENABLE_DEFAULT 0 962 #define DP_GRO_ENABLE_BIT_SET BIT(0) 963 #define DP_TC_BASED_DYNAMIC_GRO BIT(1) 964 965 /* 966 * <ini> 967 * CFG_DP_GRO - Enable the GRO feature standalonely 968 * @Min: 0 969 * @Max: 3 970 * @Default: 0 971 * 972 * This ini entry is used to enable/disable GRO feature standalonely. 973 * Value 0: Disable GRO feature 974 * Value 1: Enable GRO feature always 975 * Value 3: Enable GRO dynamic feature where TC rule can control GRO 976 * behavior 977 * 978 * Usage: External 979 * 980 * </ini> 981 */ 982 #define CFG_DP_GRO \ 983 CFG_INI_UINT("GROEnable", \ 984 WLAN_CFG_GRO_ENABLE_MIN, \ 985 WLAN_CFG_GRO_ENABLE_MAX, \ 986 WLAN_CFG_GRO_ENABLE_DEFAULT, \ 987 CFG_VALUE_OR_DEFAULT, "DP GRO Enable") 988 989 #define WLAN_CFG_TC_INGRESS_PRIO_MIN 0 990 #define WLAN_CFG_TC_INGRESS_PRIO_MAX 0xFFFF 991 #define WLAN_CFG_TC_INGRESS_PRIO_DEFAULT 0 992 993 #define CFG_DP_TC_INGRESS_PRIO \ 994 CFG_INI_UINT("tc_ingress_prio", \ 995 WLAN_CFG_TC_INGRESS_PRIO_MIN, \ 996 WLAN_CFG_TC_INGRESS_PRIO_MAX, \ 997 WLAN_CFG_TC_INGRESS_PRIO_DEFAULT, \ 998 CFG_VALUE_OR_DEFAULT, "DP tc ingress prio") 999 1000 #define CFG_DP_OL_TX_CSUM \ 1001 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \ 1002 "DP tx csum Enable") 1003 1004 #define CFG_DP_OL_RX_CSUM \ 1005 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \ 1006 "DP rx csum Enable") 1007 1008 #define CFG_DP_RAWMODE \ 1009 CFG_INI_BOOL("dp_rawmode_support", false, \ 1010 "DP rawmode Enable") 1011 1012 #define CFG_DP_PEER_FLOW_CTRL \ 1013 CFG_INI_BOOL("dp_peer_flow_control_support", false, \ 1014 "DP peer flow ctrl Enable") 1015 1016 #define CFG_DP_NAPI \ 1017 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \ 1018 "DP Napi Enabled") 1019 /* 1020 * <ini> 1021 * gEnableP2pIpTcpUdpChecksumOffload - Enable checksum offload for P2P mode 1022 * @Min: 0 1023 * @Max: 1 1024 * @Default: 1 1025 * 1026 * This ini entry is used to enable/disable TX checksum(UDP/TCP) for P2P modes. 1027 * This includes P2P device mode, P2P client mode and P2P GO mode. 1028 * The feature is enabled by default. To disable TX checksum for P2P, add the 1029 * following entry in ini file: 1030 * gEnableP2pIpTcpUdpChecksumOffload=0 1031 * 1032 * Usage: External 1033 * 1034 * </ini> 1035 */ 1036 #define CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD \ 1037 CFG_INI_BOOL("gEnableP2pIpTcpUdpChecksumOffload", true, \ 1038 "DP TCP UDP Checksum Offload for P2P mode (device/cli/go)") 1039 1040 /* 1041 * <ini> 1042 * gEnableNanIpTcpUdpChecksumOffload - Enable checksum offload for NAN mode 1043 * @Min: 0 1044 * @Max: 1 1045 * @Default: 1 1046 * 1047 * Usage: External 1048 * 1049 * </ini> 1050 */ 1051 #define CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD \ 1052 CFG_INI_BOOL("gEnableNanIpTcpUdpChecksumOffload", true, \ 1053 "DP TCP UDP Checksum Offload for NAN mode") 1054 1055 /* 1056 * <ini> 1057 * gEnableIpTcpUdpChecksumOffload - Enable checksum offload 1058 * @Min: 0 1059 * @Max: 1 1060 * @Default: 1 1061 * 1062 * Usage: External 1063 * 1064 * </ini> 1065 */ 1066 #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \ 1067 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \ 1068 "DP TCP UDP Checksum Offload") 1069 1070 #define CFG_DP_DEFRAG_TIMEOUT_CHECK \ 1071 CFG_INI_BOOL("dp_defrag_timeout_check", true, \ 1072 "DP Defrag Timeout Check") 1073 1074 #define CFG_DP_WBM_RELEASE_RING \ 1075 CFG_INI_UINT("dp_wbm_release_ring", \ 1076 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \ 1077 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \ 1078 WLAN_CFG_WBM_RELEASE_RING_SIZE, \ 1079 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring") 1080 1081 #define CFG_DP_TCL_CMD_CREDIT_RING \ 1082 CFG_INI_UINT("dp_tcl_cmd_credit_ring", \ 1083 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN, \ 1084 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX, \ 1085 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE, \ 1086 CFG_VALUE_OR_DEFAULT, "DP TCL Cmd_Credit ring") 1087 1088 #define CFG_DP_TCL_STATUS_RING \ 1089 CFG_INI_UINT("dp_tcl_status_ring",\ 1090 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \ 1091 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \ 1092 WLAN_CFG_TCL_STATUS_RING_SIZE, \ 1093 CFG_VALUE_OR_DEFAULT, "DP TCL status ring") 1094 1095 #define CFG_DP_REO_REINJECT_RING \ 1096 CFG_INI_UINT("dp_reo_reinject_ring", \ 1097 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \ 1098 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \ 1099 WLAN_CFG_REO_REINJECT_RING_SIZE, \ 1100 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring") 1101 1102 #define CFG_DP_RX_RELEASE_RING \ 1103 CFG_INI_UINT("dp_rx_release_ring", \ 1104 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \ 1105 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \ 1106 WLAN_CFG_RX_RELEASE_RING_SIZE, \ 1107 CFG_VALUE_OR_DEFAULT, "DP Rx release ring") 1108 1109 #define CFG_DP_RX_DESTINATION_RING \ 1110 CFG_INI_UINT("dp_reo_dst_ring", \ 1111 WLAN_CFG_REO_DST_RING_SIZE_MIN, \ 1112 WLAN_CFG_REO_DST_RING_SIZE_MAX, \ 1113 WLAN_CFG_REO_DST_RING_SIZE, \ 1114 CFG_VALUE_OR_DEFAULT, "DP REO destination ring") 1115 1116 #define CFG_DP_REO_EXCEPTION_RING \ 1117 CFG_INI_UINT("dp_reo_exception_ring", \ 1118 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \ 1119 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \ 1120 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \ 1121 CFG_VALUE_OR_DEFAULT, "DP REO exception ring") 1122 1123 #define CFG_DP_REO_CMD_RING \ 1124 CFG_INI_UINT("dp_reo_cmd_ring", \ 1125 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \ 1126 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \ 1127 WLAN_CFG_REO_CMD_RING_SIZE, \ 1128 CFG_VALUE_OR_DEFAULT, "DP REO command ring") 1129 1130 #define CFG_DP_REO_STATUS_RING \ 1131 CFG_INI_UINT("dp_reo_status_ring", \ 1132 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \ 1133 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \ 1134 WLAN_CFG_REO_STATUS_RING_SIZE, \ 1135 CFG_VALUE_OR_DEFAULT, "DP REO status ring") 1136 1137 #define CFG_DP_RXDMA_BUF_RING \ 1138 CFG_INI_UINT("dp_rxdma_buf_ring", \ 1139 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \ 1140 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \ 1141 WLAN_CFG_RXDMA_BUF_RING_SIZE, \ 1142 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring") 1143 1144 #define CFG_DP_RXDMA_REFILL_RING \ 1145 CFG_INI_UINT("dp_rxdma_refill_ring", \ 1146 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \ 1147 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \ 1148 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \ 1149 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring") 1150 1151 #define CFG_DP_RXDMA_REFILL_LT_DISABLE \ 1152 CFG_INI_BOOL("dp_disable_rx_buf_low_threshold", false, \ 1153 "Disable Low threshold interrupts for Rx Refill ring") 1154 1155 #define CFG_DP_TX_DESC_LIMIT_0 \ 1156 CFG_INI_UINT("dp_tx_desc_limit_0", \ 1157 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \ 1158 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \ 1159 WLAN_CFG_TX_DESC_LIMIT_0, \ 1160 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0") 1161 1162 #define CFG_DP_TX_DESC_LIMIT_1 \ 1163 CFG_INI_UINT("dp_tx_desc_limit_1", \ 1164 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \ 1165 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \ 1166 WLAN_CFG_TX_DESC_LIMIT_1, \ 1167 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1") 1168 1169 #define CFG_DP_TX_DESC_LIMIT_2 \ 1170 CFG_INI_UINT("dp_tx_desc_limit_2", \ 1171 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \ 1172 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \ 1173 WLAN_CFG_TX_DESC_LIMIT_2, \ 1174 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2") 1175 1176 #define CFG_DP_TX_DEVICE_LIMIT \ 1177 CFG_INI_UINT("dp_tx_device_limit", \ 1178 WLAN_CFG_TX_DEVICE_LIMIT_MIN, \ 1179 WLAN_CFG_TX_DEVICE_LIMIT_MAX, \ 1180 WLAN_CFG_TX_DEVICE_LIMIT, \ 1181 CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit") 1182 1183 #define CFG_DP_TX_SPL_DEVICE_LIMIT \ 1184 CFG_INI_UINT("dp_tx_spl_device_limit", \ 1185 WLAN_CFG_TX_SPL_DEVICE_LIMIT_MIN, \ 1186 WLAN_CFG_TX_SPL_DEVICE_LIMIT_MAX, \ 1187 WLAN_CFG_TX_SPL_DEVICE_LIMIT, \ 1188 CFG_VALUE_OR_DEFAULT, "DP TX Special DEVICE limit") 1189 1190 #define CFG_DP_TX_SW_INTERNODE_QUEUE \ 1191 CFG_INI_UINT("dp_tx_sw_internode_queue", \ 1192 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \ 1193 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \ 1194 WLAN_CFG_TX_SW_INTERNODE_QUEUE, \ 1195 CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue") 1196 1197 #define CFG_DP_RXDMA_MONITOR_BUF_RING \ 1198 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \ 1199 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \ 1200 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \ 1201 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \ 1202 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring") 1203 1204 #define CFG_DP_TX_MONITOR_BUF_RING \ 1205 CFG_INI_UINT("dp_tx_monitor_buf_ring", \ 1206 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN, \ 1207 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX, \ 1208 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE, \ 1209 CFG_VALUE_OR_DEFAULT, "DP TX monitor buffer ring") 1210 1211 #define CFG_DP_RXDMA_MONITOR_DST_RING \ 1212 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \ 1213 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \ 1214 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \ 1215 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \ 1216 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 1217 1218 #define CFG_DP_TX_MONITOR_DST_RING \ 1219 CFG_INI_UINT("dp_tx_monitor_dst_ring", \ 1220 WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN, \ 1221 WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX, \ 1222 WLAN_CFG_TX_MONITOR_DST_RING_SIZE, \ 1223 CFG_VALUE_OR_DEFAULT, "DP TX monitor destination ring") 1224 1225 #define CFG_DP_RXDMA_MONITOR_STATUS_RING \ 1226 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \ 1227 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \ 1228 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \ 1229 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \ 1230 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring") 1231 1232 #define CFG_DP_RXDMA_MONITOR_DESC_RING \ 1233 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \ 1234 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \ 1235 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \ 1236 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \ 1237 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 1238 1239 #define CFG_DP_RXDMA_ERR_DST_RING \ 1240 CFG_INI_UINT("dp_rxdma_err_dst_ring", \ 1241 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \ 1242 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \ 1243 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \ 1244 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring") 1245 1246 #define CFG_DP_PER_PKT_LOGGING \ 1247 CFG_INI_UINT("enable_verbose_debug", \ 1248 0, 0xffff, 0, \ 1249 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging") 1250 1251 #define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \ 1252 CFG_INI_UINT("TxFlowStartQueueOffset", \ 1253 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \ 1254 CFG_VALUE_OR_DEFAULT, "Start queue offset") 1255 1256 #define CFG_DP_TX_FLOW_STOP_QUEUE_TH \ 1257 CFG_INI_UINT("TxFlowStopQueueThreshold", \ 1258 0, 50, 15, \ 1259 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold") 1260 1261 #define CFG_DP_IPA_UC_TX_BUF_SIZE \ 1262 CFG_INI_UINT("IpaUcTxBufSize", \ 1263 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \ 1264 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size") 1265 1266 #define CFG_DP_IPA_UC_TX_PARTITION_BASE \ 1267 CFG_INI_UINT("IpaUcTxPartitionBase", \ 1268 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \ 1269 CFG_VALUE_OR_DEFAULT, "IPA tx partition base") 1270 1271 #define CFG_DP_IPA_UC_RX_IND_RING_COUNT \ 1272 CFG_INI_UINT("IpaUcRxIndRingCount", \ 1273 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \ 1274 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count") 1275 1276 #define CFG_DP_AP_STA_SECURITY_SEPERATION \ 1277 CFG_INI_BOOL("gDisableIntraBssFwd", \ 1278 false, "Disable intrs BSS Rx packets") 1279 1280 #define CFG_DP_ENABLE_DATA_STALL_DETECTION \ 1281 CFG_INI_UINT("gEnableDataStallDetection", \ 1282 0, 0xFFFFFFFF, 0x1, \ 1283 CFG_VALUE_OR_DEFAULT, "Enable/Disable Data stall detection") 1284 1285 #define CFG_DP_RX_SW_DESC_WEIGHT \ 1286 CFG_INI_UINT("dp_rx_sw_desc_weight", \ 1287 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN, \ 1288 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX, \ 1289 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE, \ 1290 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC weight") 1291 1292 #define CFG_DP_RX_SW_DESC_NUM \ 1293 CFG_INI_UINT("dp_rx_sw_desc_num", \ 1294 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN, \ 1295 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX, \ 1296 WLAN_CFG_RX_SW_DESC_NUM_SIZE, \ 1297 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC num") 1298 1299 #define CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE \ 1300 CFG_INI_UINT("dp_rx_flow_search_table_size", \ 1301 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN, \ 1302 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX, \ 1303 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT, \ 1304 CFG_VALUE_OR_DEFAULT, \ 1305 "DP Rx Flow Search Table Size in number of entries") 1306 1307 #define CFG_DP_RX_FLOW_TAG_ENABLE \ 1308 CFG_INI_BOOL("dp_rx_flow_tag_enable", false, \ 1309 "Enable/Disable DP Rx Flow Tag") 1310 1311 #define CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV \ 1312 CFG_INI_BOOL("dp_rx_per_pdev_flow_search", false, \ 1313 "DP Rx Flow Search Table Is Per PDev") 1314 1315 #define CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE \ 1316 CFG_INI_BOOL("dp_rx_monitor_protocol_flow_tag_enable", true, \ 1317 "Enable/Disable Rx Protocol & Flow tags in Monitor mode") 1318 1319 #define CFG_DP_TX_PER_PKT_VDEV_ID_CHECK \ 1320 CFG_INI_BOOL("dp_tx_allow_per_pkt_vdev_id_check", false, \ 1321 "Enable/Disable tx Per Pkt vdev id check") 1322 1323 #define CFG_DP_HANDLE_INVALID_DECAP_TYPE_DISABLE \ 1324 CFG_INI_BOOL("dp_handle_invalid_decap_type_disable", false, \ 1325 "Enable/Disable DP TLV out of order WAR") 1326 1327 #define CFG_DP_TXMON_SW_PEER_FILTERING \ 1328 CFG_INI_BOOL("tx_litemon_sw_peer_filtering", false, \ 1329 "Enable SW based tx monitor peer fitlering") 1330 1331 /* 1332 * <ini> 1333 * dp_rx_fisa_enable - Control Rx datapath FISA 1334 * @Min: 0 1335 * @Max: 1 1336 * @Default: 1 1337 * 1338 * This ini is used to enable DP Rx FISA feature 1339 * 1340 * Related: dp_rx_flow_search_table_size 1341 * 1342 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1343 * 1344 * Usage: Internal 1345 * 1346 * </ini> 1347 */ 1348 #define CFG_DP_RX_FISA_ENABLE \ 1349 CFG_INI_BOOL("dp_rx_fisa_enable", true, \ 1350 "Enable/Disable DP Rx FISA") 1351 1352 /* 1353 * <ini> 1354 * dp_rx_fisa_lru_del_enable - Control Rx datapath FISA 1355 * @Min: 0 1356 * @Max: 1 1357 * @Default: 1 1358 * 1359 * This ini is used to enable DP Rx FISA lru deletion feature 1360 * 1361 * Related: dp_rx_fisa_enable 1362 * 1363 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1364 * 1365 * Usage: Internal 1366 * 1367 * </ini> 1368 */ 1369 #define CFG_DP_RX_FISA_LRU_DEL_ENABLE \ 1370 CFG_INI_BOOL("dp_rx_fisa_lru_del_enable", true, \ 1371 "Enable/Disable DP Rx FISA LRU deletion") 1372 1373 #define CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD \ 1374 CFG_INI_UINT("mon_drop_thresh", \ 1375 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN, \ 1376 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX, \ 1377 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE, \ 1378 CFG_VALUE_OR_DEFAULT, "RXDMA monitor rx drop threshold") 1379 1380 #define CFG_DP_PKTLOG_BUFFER_SIZE \ 1381 CFG_INI_UINT("PktlogBufSize", \ 1382 WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE, \ 1383 WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE, \ 1384 WLAN_CFG_PKTLOG_BUFFER_SIZE, \ 1385 CFG_VALUE_OR_DEFAULT, "Packet Log buffer size") 1386 1387 #define CFG_DP_FULL_MON_MODE \ 1388 CFG_INI_BOOL("full_mon_mode", \ 1389 false, "Full Monitor mode support") 1390 1391 #define CFG_DP_REO_RINGS_MAP \ 1392 CFG_INI_UINT("dp_reo_rings_map", \ 1393 WLAN_CFG_NUM_REO_RINGS_MAP_MIN, \ 1394 WLAN_CFG_NUM_REO_RINGS_MAP_MAX, \ 1395 WLAN_CFG_NUM_REO_RINGS_MAP, \ 1396 CFG_VALUE_OR_DEFAULT, "REO Destination Rings Mapping") 1397 1398 #define CFG_DP_RX_RADIO_0_DEFAULT_REO \ 1399 CFG_INI_UINT("dp_rx_radio0_default_reo", \ 1400 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1401 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1402 WLAN_CFG_RADIO_0_DEFAULT_REO, \ 1403 CFG_VALUE_OR_DEFAULT, "Radio0 to REO destination default mapping") 1404 1405 #define CFG_DP_RX_RADIO_1_DEFAULT_REO \ 1406 CFG_INI_UINT("dp_rx_radio1_default_reo", \ 1407 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1408 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1409 WLAN_CFG_RADIO_1_DEFAULT_REO, \ 1410 CFG_VALUE_OR_DEFAULT, "Radio1 to REO destination default mapping") 1411 1412 #define CFG_DP_RX_RADIO_2_DEFAULT_REO \ 1413 CFG_INI_UINT("dp_rx_radio2_default_reo", \ 1414 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1415 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1416 WLAN_CFG_RADIO_2_DEFAULT_REO, \ 1417 CFG_VALUE_OR_DEFAULT, "Radio2 to REO destination default mapping") 1418 1419 #define CFG_DP_PEER_EXT_STATS \ 1420 CFG_INI_BOOL("peer_ext_stats", \ 1421 false, "Peer extended stats") 1422 1423 #define CFG_DP_PEER_JITTER_STATS \ 1424 CFG_INI_BOOL("peer_jitter_stats", \ 1425 false, "Peer Jitter stats") 1426 1427 #define CFG_DP_NAPI_SCALE_FACTOR \ 1428 CFG_INI_UINT("dp_napi_scale_factor", \ 1429 WLAN_CFG_DP_NAPI_SCALE_FACTOR_MIN, \ 1430 WLAN_CFG_DP_NAPI_SCALE_FACTOR_MAX, \ 1431 WLAN_CFG_DP_NAPI_SCALE_FACTOR, \ 1432 CFG_VALUE_OR_DEFAULT, "NAPI scale factor for DP") 1433 1434 /* 1435 * <ini> 1436 * legacy_mode_csum_disable - Disable csum offload for legacy 802.11abg modes 1437 * @Min: 0 1438 * @Max: 1 1439 * @Default: Default value indicating if checksum should be disabled for 1440 * legacy WLAN modes 1441 * 1442 * This ini is used to disable HW checksum offload capability for legacy 1443 * connections 1444 * 1445 * Related: gEnableIpTcpUdpChecksumOffload should be enabled 1446 * 1447 * Usage: Internal 1448 * 1449 * </ini> 1450 */ 1451 #ifndef DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1452 #define DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1 1453 #endif 1454 1455 #define CFG_DP_LEGACY_MODE_CSUM_DISABLE \ 1456 CFG_INI_BOOL("legacy_mode_csum_disable", \ 1457 DP_LEGACY_MODE_CSM_DEFAULT_DISABLE, \ 1458 "Enable/Disable legacy mode checksum") 1459 1460 #define CFG_DP_RX_BUFF_POOL_ENABLE \ 1461 CFG_INI_BOOL("dp_rx_buff_prealloc_pool", false, \ 1462 "Enable/Disable DP RX emergency buffer pool support") 1463 1464 #define CFG_DP_RX_REFILL_BUFF_POOL_ENABLE \ 1465 CFG_INI_BOOL("dp_rx_refill_buff_pool", false, \ 1466 "Enable/Disable DP RX refill buffer pool support") 1467 1468 #define CFG_DP_POLL_MODE_ENABLE \ 1469 CFG_INI_BOOL("dp_poll_mode_enable", false, \ 1470 "Enable/Disable Polling mode for data path") 1471 1472 #define CFG_DP_RX_FST_IN_CMEM \ 1473 CFG_INI_BOOL("dp_rx_fst_in_cmem", false, \ 1474 "Enable/Disable flow search table in CMEM") 1475 /* 1476 * <ini> 1477 * gEnableSWLM - Control DP Software latency manager 1478 * @Min: 0 1479 * @Max: 1 1480 * @Default: 0 1481 * 1482 * This ini is used to enable DP Software latency Manager 1483 * 1484 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1485 * 1486 * Usage: Internal 1487 * 1488 * </ini> 1489 */ 1490 #define CFG_DP_SWLM_ENABLE \ 1491 CFG_INI_BOOL("gEnableSWLM", false, \ 1492 "Enable/Disable DP SWLM") 1493 /* 1494 * <ini> 1495 * wow_check_rx_pending_enable - control to check RX frames pending in Wow 1496 * @Min: 0 1497 * @Max: 1 1498 * @Default: 0 1499 * 1500 * This ini is used to control DP Software to perform RX pending check 1501 * before entering WoW mode 1502 * 1503 * Usage: Internal 1504 * 1505 * </ini> 1506 */ 1507 #define CFG_DP_WOW_CHECK_RX_PENDING \ 1508 CFG_INI_BOOL("wow_check_rx_pending_enable", \ 1509 false, \ 1510 "enable rx frame pending check in WoW mode") 1511 #define CFG_DP_DELAY_MON_REPLENISH \ 1512 CFG_INI_BOOL("delay_mon_replenish", \ 1513 true, "Delay Monitor Replenish") 1514 1515 #ifdef QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT 1516 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN 500 1517 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX 2000 1518 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER 500 1519 1520 #define CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG \ 1521 CFG_INI_BOOL("vdev_stats_hw_offload_config", \ 1522 false, "Offload vdev stats to HW") 1523 #define CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER \ 1524 CFG_INI_UINT("vdev_stats_hw_offload_timer", \ 1525 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN, \ 1526 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX, \ 1527 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER, \ 1528 CFG_VALUE_OR_DEFAULT, \ 1529 "vdev stats hw offload timer duration") 1530 #define CFG_DP_VDEV_STATS_HW_OFFLOAD \ 1531 CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG) \ 1532 CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER) 1533 #else 1534 #define CFG_DP_VDEV_STATS_HW_OFFLOAD 1535 #endif 1536 1537 /* 1538 * <ini> 1539 * ghw_cc_enable - enable HW cookie conversion by register 1540 * @Min: 0 1541 * @Max: 1 1542 * @Default: 1 1543 * 1544 * This ini is used to control HW based 20 bits cookie to 64 bits 1545 * Desc virtual address conversion 1546 * 1547 * Usage: Internal 1548 * 1549 * </ini> 1550 */ 1551 #define CFG_DP_HW_CC_ENABLE \ 1552 CFG_INI_BOOL("ghw_cc_enable", \ 1553 true, "Enable/Disable HW cookie conversion") 1554 1555 #ifdef IPA_OFFLOAD 1556 /* 1557 * <ini> 1558 * dp_ipa_tx_ring_size - Set tcl ring size for IPA 1559 * @Min: 1024 1560 * @Max: 8096 1561 * @Default: 1024 1562 * 1563 * This ini sets the tcl ring size for IPA 1564 * 1565 * Related: N/A 1566 * 1567 * Supported Feature: IPA 1568 * 1569 * Usage: Internal 1570 * 1571 * </ini> 1572 */ 1573 #define CFG_DP_IPA_TX_RING_SIZE \ 1574 CFG_INI_UINT("dp_ipa_tx_ring_size", \ 1575 WLAN_CFG_IPA_TX_RING_SIZE_MIN, \ 1576 WLAN_CFG_IPA_TX_RING_SIZE_MAX, \ 1577 WLAN_CFG_IPA_TX_RING_SIZE, \ 1578 CFG_VALUE_OR_DEFAULT, "IPA TCL ring size") 1579 1580 /* 1581 * <ini> 1582 * dp_ipa_tx_comp_ring_size - Set tx comp ring size for IPA 1583 * @Min: 1024 1584 * @Max: 8096 1585 * @Default: 1024 1586 * 1587 * This ini sets the tx comp ring size for IPA 1588 * 1589 * Related: N/A 1590 * 1591 * Supported Feature: IPA 1592 * 1593 * Usage: Internal 1594 * 1595 * </ini> 1596 */ 1597 #define CFG_DP_IPA_TX_COMP_RING_SIZE \ 1598 CFG_INI_UINT("dp_ipa_tx_comp_ring_size", \ 1599 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN, \ 1600 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX, \ 1601 WLAN_CFG_IPA_TX_COMP_RING_SIZE, \ 1602 CFG_VALUE_OR_DEFAULT, "IPA tx comp ring size") 1603 1604 #ifdef IPA_WDI3_TX_TWO_PIPES 1605 /* 1606 * <ini> 1607 * dp_ipa_tx_alt_ring_size - Set alt tcl ring size for IPA 1608 * @Min: 1024 1609 * @Max: 8096 1610 * @Default: 1024 1611 * 1612 * This ini sets the alt tcl ring size for IPA 1613 * 1614 * Related: N/A 1615 * 1616 * Supported Feature: IPA 1617 * 1618 * Usage: Internal 1619 * 1620 * </ini> 1621 */ 1622 #define CFG_DP_IPA_TX_ALT_RING_SIZE \ 1623 CFG_INI_UINT("dp_ipa_tx_alt_ring_size", \ 1624 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN, \ 1625 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX, \ 1626 WLAN_CFG_IPA_TX_ALT_RING_SIZE, \ 1627 CFG_VALUE_OR_DEFAULT, \ 1628 "DP IPA TX Alternative Ring Size") 1629 1630 /* 1631 * <ini> 1632 * dp_ipa_tx_alt_comp_ring_size - Set tx alt comp ring size for IPA 1633 * @Min: 1024 1634 * @Max: 8096 1635 * @Default: 1024 1636 * 1637 * This ini sets the tx alt comp ring size for IPA 1638 * 1639 * Related: N/A 1640 * 1641 * Supported Feature: IPA 1642 * 1643 * Usage: Internal 1644 * 1645 * </ini> 1646 */ 1647 #define CFG_DP_IPA_TX_ALT_COMP_RING_SIZE \ 1648 CFG_INI_UINT("dp_ipa_tx_alt_comp_ring_size", \ 1649 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN, \ 1650 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX, \ 1651 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE, \ 1652 CFG_VALUE_OR_DEFAULT, \ 1653 "DP IPA TX Alternative Completion Ring Size") 1654 1655 #define CFG_DP_IPA_TX_ALT_RING_CFG \ 1656 CFG(CFG_DP_IPA_TX_ALT_RING_SIZE) \ 1657 CFG(CFG_DP_IPA_TX_ALT_COMP_RING_SIZE) 1658 1659 #else 1660 #define CFG_DP_IPA_TX_ALT_RING_CFG 1661 #endif 1662 1663 #define CFG_DP_IPA_TX_RING_CFG \ 1664 CFG(CFG_DP_IPA_TX_RING_SIZE) \ 1665 CFG(CFG_DP_IPA_TX_COMP_RING_SIZE) 1666 #else 1667 #define CFG_DP_IPA_TX_RING_CFG 1668 #define CFG_DP_IPA_TX_ALT_RING_CFG 1669 #endif 1670 1671 #ifdef WLAN_SUPPORT_PPEDS 1672 #define WLAN_CFG_NUM_PPEDS_TX_DESC_MIN 16 1673 #define WLAN_CFG_NUM_PPEDS_TX_DESC_MAX 0x8000 1674 #define WLAN_CFG_NUM_PPEDS_TX_DESC 0x8000 1675 1676 #define WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MIN 8 1677 #define WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MAX 256 1678 #define WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI 64 1679 1680 #define CFG_DP_PPEDS_TX_DESC \ 1681 CFG_INI_UINT("dp_ppeds_tx_desc", \ 1682 WLAN_CFG_NUM_PPEDS_TX_DESC_MIN, \ 1683 WLAN_CFG_NUM_PPEDS_TX_DESC_MAX, \ 1684 WLAN_CFG_NUM_PPEDS_TX_DESC, \ 1685 CFG_VALUE_OR_DEFAULT, "DP PPEDS Tx Descriptors") 1686 1687 #define CFG_DP_PPEDS_TX_CMP_NAPI_BUDGET \ 1688 CFG_INI_UINT("dp_ppeds_tx_cmp_napi_budget", \ 1689 WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MIN, \ 1690 WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MAX, \ 1691 WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI, \ 1692 CFG_VALUE_OR_DEFAULT, "DP PPEDS Tx Comp handler napi budget") 1693 1694 #define CFG_DP_PPEDS_ENABLE \ 1695 CFG_INI_BOOL("ppe_ds_enable", true, \ 1696 "DP ppe enable flag") 1697 1698 #define CFG_DP_REO2PPE_RING \ 1699 CFG_INI_UINT("dp_reo2ppe_ring", \ 1700 WLAN_CFG_REO2PPE_RING_SIZE_MIN, \ 1701 WLAN_CFG_REO2PPE_RING_SIZE_MAX, \ 1702 WLAN_CFG_REO2PPE_RING_SIZE, \ 1703 CFG_VALUE_OR_DEFAULT, "DP REO2PPE ring") 1704 1705 #define CFG_DP_PPE2TCL_RING \ 1706 CFG_INI_UINT("dp_ppe2tcl_ring", \ 1707 WLAN_CFG_PPE2TCL_RING_SIZE_MIN, \ 1708 WLAN_CFG_PPE2TCL_RING_SIZE_MAX, \ 1709 WLAN_CFG_PPE2TCL_RING_SIZE, \ 1710 CFG_VALUE_OR_DEFAULT, "DP PPE2TCL rings") 1711 1712 #define CFG_DP_PPEDS_CONFIG \ 1713 CFG(CFG_DP_PPEDS_TX_CMP_NAPI_BUDGET) \ 1714 CFG(CFG_DP_PPEDS_TX_DESC) \ 1715 CFG(CFG_DP_PPEDS_ENABLE) \ 1716 CFG(CFG_DP_REO2PPE_RING) \ 1717 CFG(CFG_DP_PPE2TCL_RING) 1718 #else 1719 #define CFG_DP_PPEDS_CONFIG 1720 #define WLAN_CFG_NUM_PPEDS_TX_DESC_MAX 0 1721 #endif 1722 1723 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 1724 /* 1725 * <ini> 1726 * dp_chip0_rx_ring_map - Set Rx ring map for CHIP 0 1727 * @Min: 0x0 1728 * @Max: 0xFF 1729 * @Default: 0xF 1730 * 1731 * This ini sets Rx ring map for CHIP 0 1732 * 1733 * Usage: Internal 1734 * 1735 * </ini> 1736 */ 1737 #define CFG_DP_MLO_RX_RING_MAP \ 1738 CFG_INI_UINT("dp_mlo_reo_rings_map", \ 1739 WLAN_CFG_MLO_RX_RING_MAP_MIN, \ 1740 WLAN_CFG_MLO_RX_RING_MAP_MAX, \ 1741 WLAN_CFG_MLO_RX_RING_MAP, \ 1742 CFG_VALUE_OR_DEFAULT, "DP MLO Rx ring map") 1743 1744 1745 #define CFG_DP_MLO_CONFIG \ 1746 CFG(CFG_DP_MLO_RX_RING_MAP) 1747 #else 1748 #define CFG_DP_MLO_CONFIG 1749 #endif 1750 1751 /* 1752 * <ini> 1753 * dp_mpdu_retry_threshold_1 - threshold to increment mpdu success with retries 1754 * @Min: 0 1755 * @Max: 255 1756 * @Default: 0 1757 * 1758 * This ini entry is used to set first threshold to increment the value of 1759 * mpdu_success_with_retries 1760 * 1761 * Usage: Internal 1762 * 1763 * </ini> 1764 */ 1765 #define CFG_DP_MPDU_RETRY_THRESHOLD_1 \ 1766 CFG_INI_UINT("dp_mpdu_retry_threshold_1", \ 1767 CFG_DP_MPDU_RETRY_THRESHOLD_MIN, \ 1768 CFG_DP_MPDU_RETRY_THRESHOLD_MAX, \ 1769 CFG_DP_MPDU_RETRY_THRESHOLD, \ 1770 CFG_VALUE_OR_DEFAULT, "DP mpdu retry threshold 1") 1771 1772 /* 1773 * <ini> 1774 * dp_mpdu_retry_threshold_2 - threshold to increment mpdu success with retries 1775 * @Min: 0 1776 * @Max: 255 1777 * @Default: 0 1778 * 1779 * This ini entry is used to set second threshold to increment the value of 1780 * mpdu_success_with_retries 1781 * 1782 * Usage: Internal 1783 * 1784 * </ini> 1785 */ 1786 #define CFG_DP_MPDU_RETRY_THRESHOLD_2 \ 1787 CFG_INI_UINT("dp_mpdu_retry_threshold_2", \ 1788 CFG_DP_MPDU_RETRY_THRESHOLD_MIN, \ 1789 CFG_DP_MPDU_RETRY_THRESHOLD_MAX, \ 1790 CFG_DP_MPDU_RETRY_THRESHOLD, \ 1791 CFG_VALUE_OR_DEFAULT, "DP mpdu retry threshold 2") 1792 1793 #ifdef QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES 1794 /* Macro enabling support marking of notify frames by host */ 1795 #define DP_MARK_NOTIFY_FRAME_SUPPORT 1 1796 #else 1797 #define DP_MARK_NOTIFY_FRAME_SUPPORT 0 1798 #endif /* QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES */ 1799 1800 /* 1801 * <ini> 1802 * Host DP AST entries database - Enable/Disable 1803 * 1804 * @Default: 0 1805 * 1806 * This ini enables/disables AST entries database on host 1807 * 1808 * Usage: Internal 1809 * 1810 * </ini> 1811 */ 1812 #define CFG_DP_HOST_AST_DB_ENABLE \ 1813 CFG_INI_BOOL("host_ast_db_enable", false, \ 1814 "Host AST entries database Enable/Disable") 1815 1816 #define CFG_DP \ 1817 CFG(CFG_DP_HTT_PACKET_TYPE) \ 1818 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \ 1819 CFG(CFG_DP_INT_BATCH_THRESHOLD_PPE2TCL) \ 1820 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \ 1821 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \ 1822 CFG(CFG_DP_INT_TIMER_THRESHOLD_PPE2TCL) \ 1823 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \ 1824 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \ 1825 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \ 1826 CFG(CFG_DP_MAX_ALLOC_SIZE) \ 1827 CFG(CFG_DP_MAX_CLIENTS) \ 1828 CFG(CFG_DP_MAX_PEER_ID) \ 1829 CFG(CFG_DP_REO_DEST_RINGS) \ 1830 CFG(CFG_DP_TX_COMP_RINGS) \ 1831 CFG(CFG_DP_TCL_DATA_RINGS) \ 1832 CFG(CFG_DP_NSS_REO_DEST_RINGS) \ 1833 CFG(CFG_DP_NSS_TCL_DATA_RINGS) \ 1834 CFG(CFG_DP_TX_DESC) \ 1835 CFG(CFG_DP_TX_SPL_DESC) \ 1836 CFG(CFG_DP_TX_EXT_DESC) \ 1837 CFG(CFG_DP_TX_EXT_DESC_POOLS) \ 1838 CFG(CFG_DP_PDEV_RX_RING) \ 1839 CFG(CFG_DP_PDEV_TX_RING) \ 1840 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \ 1841 CFG(CFG_DP_TX_COMPL_RING_SIZE) \ 1842 CFG(CFG_DP_TX_RING_SIZE) \ 1843 CFG(CFG_DP_NSS_COMP_RING_SIZE) \ 1844 CFG(CFG_DP_PDEV_LMAC_RING) \ 1845 CFG(CFG_DP_TIME_CONTROL_BP) \ 1846 CFG(CFG_DP_BASE_HW_MAC_ID) \ 1847 CFG(CFG_DP_RX_HASH) \ 1848 CFG(CFG_DP_TSO) \ 1849 CFG(CFG_DP_LRO) \ 1850 CFG(CFG_DP_SG) \ 1851 CFG(CFG_DP_GRO) \ 1852 CFG(CFG_DP_TC_INGRESS_PRIO) \ 1853 CFG(CFG_DP_OL_TX_CSUM) \ 1854 CFG(CFG_DP_OL_RX_CSUM) \ 1855 CFG(CFG_DP_RAWMODE) \ 1856 CFG(CFG_DP_PEER_FLOW_CTRL) \ 1857 CFG(CFG_DP_NAPI) \ 1858 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \ 1859 CFG(CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD) \ 1860 CFG(CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD) \ 1861 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \ 1862 CFG(CFG_DP_WBM_RELEASE_RING) \ 1863 CFG(CFG_DP_TCL_CMD_CREDIT_RING) \ 1864 CFG(CFG_DP_TCL_STATUS_RING) \ 1865 CFG(CFG_DP_REO_REINJECT_RING) \ 1866 CFG(CFG_DP_RX_RELEASE_RING) \ 1867 CFG(CFG_DP_REO_EXCEPTION_RING) \ 1868 CFG(CFG_DP_RX_DESTINATION_RING) \ 1869 CFG(CFG_DP_REO_CMD_RING) \ 1870 CFG(CFG_DP_REO_STATUS_RING) \ 1871 CFG(CFG_DP_RXDMA_BUF_RING) \ 1872 CFG(CFG_DP_RXDMA_REFILL_RING) \ 1873 CFG(CFG_DP_RXDMA_REFILL_LT_DISABLE) \ 1874 CFG(CFG_DP_TX_DESC_LIMIT_0) \ 1875 CFG(CFG_DP_TX_DESC_LIMIT_1) \ 1876 CFG(CFG_DP_TX_DESC_LIMIT_2) \ 1877 CFG(CFG_DP_TX_DEVICE_LIMIT) \ 1878 CFG(CFG_DP_TX_SPL_DEVICE_LIMIT) \ 1879 CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \ 1880 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \ 1881 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \ 1882 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \ 1883 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \ 1884 CFG(CFG_DP_RXDMA_ERR_DST_RING) \ 1885 CFG(CFG_DP_PER_PKT_LOGGING) \ 1886 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \ 1887 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \ 1888 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \ 1889 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \ 1890 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \ 1891 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \ 1892 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) \ 1893 CFG(CFG_DP_RX_SW_DESC_WEIGHT) \ 1894 CFG(CFG_DP_RX_SW_DESC_NUM) \ 1895 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE) \ 1896 CFG(CFG_DP_RX_FLOW_TAG_ENABLE) \ 1897 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV) \ 1898 CFG(CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE) \ 1899 CFG(CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD) \ 1900 CFG(CFG_DP_PKTLOG_BUFFER_SIZE) \ 1901 CFG(CFG_DP_RX_FISA_ENABLE) \ 1902 CFG(CFG_DP_RX_FISA_LRU_DEL_ENABLE) \ 1903 CFG(CFG_DP_FULL_MON_MODE) \ 1904 CFG(CFG_DP_REO_RINGS_MAP) \ 1905 CFG(CFG_DP_PEER_EXT_STATS) \ 1906 CFG(CFG_DP_PEER_JITTER_STATS) \ 1907 CFG(CFG_DP_RX_BUFF_POOL_ENABLE) \ 1908 CFG(CFG_DP_RX_REFILL_BUFF_POOL_ENABLE) \ 1909 CFG(CFG_DP_RX_PENDING_HL_THRESHOLD) \ 1910 CFG(CFG_DP_RX_PENDING_LO_THRESHOLD) \ 1911 CFG(CFG_DP_LEGACY_MODE_CSUM_DISABLE) \ 1912 CFG(CFG_DP_POLL_MODE_ENABLE) \ 1913 CFG(CFG_DP_SWLM_ENABLE) \ 1914 CFG(CFG_DP_TX_PER_PKT_VDEV_ID_CHECK) \ 1915 CFG(CFG_DP_RX_FST_IN_CMEM) \ 1916 CFG(CFG_DP_RX_RADIO_0_DEFAULT_REO) \ 1917 CFG(CFG_DP_RX_RADIO_1_DEFAULT_REO) \ 1918 CFG(CFG_DP_RX_RADIO_2_DEFAULT_REO) \ 1919 CFG(CFG_DP_WOW_CHECK_RX_PENDING) \ 1920 CFG(CFG_DP_HW_CC_ENABLE) \ 1921 CFG(CFG_DP_DELAY_MON_REPLENISH) \ 1922 CFG(CFG_DP_TX_MONITOR_BUF_RING) \ 1923 CFG(CFG_DP_TX_MONITOR_DST_RING) \ 1924 CFG(CFG_DP_MPDU_RETRY_THRESHOLD_1) \ 1925 CFG(CFG_DP_MPDU_RETRY_THRESHOLD_2) \ 1926 CFG_DP_IPA_TX_RING_CFG \ 1927 CFG_DP_PPEDS_CONFIG \ 1928 CFG_DP_IPA_TX_ALT_RING_CFG \ 1929 CFG_DP_MLO_CONFIG \ 1930 CFG_DP_INI_SECTION_PARAMS \ 1931 CFG_DP_VDEV_STATS_HW_OFFLOAD \ 1932 CFG(CFG_DP_TX_CAPT_MAX_MEM_MB) \ 1933 CFG(CFG_DP_NAPI_SCALE_FACTOR) \ 1934 CFG(CFG_DP_HOST_AST_DB_ENABLE) \ 1935 CFG_DP_SAWF_STATS_CONFIG \ 1936 CFG(CFG_DP_HANDLE_INVALID_DECAP_TYPE_DISABLE) \ 1937 CFG(CFG_DP_TXMON_SW_PEER_FILTERING) 1938 #endif /* _CFG_DP_H_ */ 1939