1 /* 2 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /** 20 * DOC: This file contains definitions of Data Path configuration. 21 */ 22 23 #ifndef _CFG_DP_H_ 24 #define _CFG_DP_H_ 25 26 #include "cfg_define.h" 27 28 #define WLAN_CFG_MAX_CLIENTS 64 29 #define WLAN_CFG_MAX_CLIENTS_MIN 8 30 #define WLAN_CFG_MAX_CLIENTS_MAX 64 31 32 /* Change this to a lower value to enforce scattered idle list mode */ 33 #define WLAN_CFG_MAX_ALLOC_SIZE 0x200000 34 #define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x200000 35 #define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000 36 37 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 38 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3 39 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3 40 41 #ifdef CONFIG_MCL 42 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 43 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10 44 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15 45 #else 46 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 47 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 48 #endif 49 #else 50 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 51 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 52 #endif 53 54 #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0 55 #define WLAN_CFG_PER_PDEV_TX_RING_MAX 1 56 57 #ifdef CONFIG_MCL 58 #define WLAN_CFG_PER_PDEV_RX_RING 0 59 #define WLAN_CFG_PER_PDEV_LMAC_RING 0 60 #define WLAN_LRO_ENABLE 0 61 #ifdef IPA_OFFLOAD 62 /* Size of TCL TX Ring */ 63 #define WLAN_CFG_TX_RING_SIZE 1024 64 #define WLAN_CFG_PER_PDEV_TX_RING 0 65 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048 66 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000 67 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024 68 #else 69 #define WLAN_CFG_TX_RING_SIZE 512 70 #define WLAN_CFG_PER_PDEV_TX_RING 1 71 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 72 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 73 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 74 #endif 75 #define WLAN_CFG_TX_COMP_RING_SIZE 1024 76 77 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 78 #define WLAN_CFG_NUM_TX_DESC 1024 79 #define WLAN_CFG_NUM_TX_EXT_DESC 1024 80 81 /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 82 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1 83 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1 84 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 85 86 /* Interrupt Mitigation - Timer threshold in us */ 87 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8 88 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8 89 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8 90 #else 91 #define WLAN_CFG_PER_PDEV_TX_RING 0 92 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 93 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 94 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 95 #endif 96 97 #ifdef CONFIG_WIN 98 #define WLAN_CFG_PER_PDEV_RX_RING 0 99 #define WLAN_CFG_PER_PDEV_LMAC_RING 1 100 #define WLAN_LRO_ENABLE 0 101 102 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 103 #ifndef QCA_WIFI_QCA8074_VP 104 #define WLAN_CFG_NUM_TX_DESC 0x320000 105 #else 106 #define WLAN_CFG_NUM_TX_DESC (8 << 10) 107 #endif 108 #define WLAN_CFG_NUM_TX_EXT_DESC 0x80000 109 110 /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 111 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 256 112 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 128 113 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 114 115 /* Interrupt Mitigation - Timer threshold in us */ 116 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 1000 117 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 500 118 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 1000 119 120 #define WLAN_CFG_TX_RING_SIZE 512 121 122 /* Size the completion ring using following 2 parameters 123 * - NAPI schedule latency (assuming 1 netdev competing for CPU) 124 * = 20 ms (2 jiffies) 125 * - Worst case PPS requirement = 400K PPS 126 * 127 * Ring size = 20 * 400 = 8000 128 * 8192 is nearest power of 2 129 */ 130 #define WLAN_CFG_TX_COMP_RING_SIZE 0x80000 131 #endif 132 133 #define WLAN_CFG_PER_PDEV_RX_RING_MIN 0 134 #define WLAN_CFG_PER_PDEV_RX_RING_MAX 0 135 136 #define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0 137 #define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1 138 139 #define WLAN_CFG_TX_RING_SIZE_MIN 512 140 #define WLAN_CFG_TX_RING_SIZE_MAX 2048 141 142 #define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512 143 #define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000 144 145 #define WLAN_CFG_NUM_TX_DESC_MIN 1024 146 #define WLAN_CFG_NUM_TX_DESC_MAX 0x320000 147 148 #define WLAN_CFG_NUM_TX_EXT_DESC_MIN 1024 149 #define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000 150 151 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1 152 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256 153 154 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 1 155 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128 156 157 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1 158 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1 159 160 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8 161 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 100 162 163 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8 164 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500 165 166 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8 167 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000 168 169 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000 170 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000 171 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0x2000 172 173 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 174 175 /* Per vdev pools */ 176 #define WLAN_CFG_NUM_TX_DESC_POOL 3 177 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 178 179 #else /* QCA_LL_TX_FLOW_CONTROL_V2 */ 180 181 #ifdef TX_PER_PDEV_DESC_POOL 182 #define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT 183 #define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT 184 185 #else /* TX_PER_PDEV_DESC_POOL */ 186 187 #define WLAN_CFG_NUM_TX_DESC_POOL 3 188 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 189 190 #endif /* TX_PER_PDEV_DESC_POOL */ 191 #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */ 192 193 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1 194 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4 195 196 #define WLAN_CFG_HTT_PKT_TYPE 2 197 #define WLAN_CFG_HTT_PKT_TYPE_MIN 2 198 #define WLAN_CFG_HTT_PKT_TYPE_MAX 2 199 200 #define WLAN_CFG_MAX_PEER_ID 64 201 #define WLAN_CFG_MAX_PEER_ID_MIN 64 202 #define WLAN_CFG_MAX_PEER_ID_MAX 64 203 204 #define WLAN_CFG_RX_DEFRAG_TIMEOUT 100 205 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100 206 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100 207 208 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 209 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3 210 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3 211 212 #define WLAN_CFG_NUM_REO_DEST_RING 4 213 #define WLAN_CFG_NUM_REO_DEST_RING_MIN 4 214 #define WLAN_CFG_NUM_REO_DEST_RING_MAX 4 215 216 #define WLAN_CFG_WBM_RELEASE_RING_SIZE 64 217 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64 218 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 64 219 220 #define WLAN_CFG_TCL_CMD_RING_SIZE 32 221 #define WLAN_CFG_TCL_CMD_RING_SIZE_MIN 32 222 #define WLAN_CFG_TCL_CMD_RING_SIZE_MAX 32 223 224 #define WLAN_CFG_TCL_STATUS_RING_SIZE 32 225 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32 226 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32 227 228 #if defined(QCA_WIFI_QCA6290) 229 #define WLAN_CFG_REO_DST_RING_SIZE 1024 230 #else 231 #define WLAN_CFG_REO_DST_RING_SIZE 2048 232 #endif 233 234 #define WLAN_CFG_REO_DST_RING_SIZE_MIN 1024 235 #define WLAN_CFG_REO_DST_RING_SIZE_MAX 2048 236 237 #define WLAN_CFG_REO_REINJECT_RING_SIZE 32 238 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32 239 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 32 240 241 #define WLAN_CFG_RX_RELEASE_RING_SIZE 1024 242 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8 243 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024 244 245 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE 128 246 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128 247 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 128 248 249 #define WLAN_CFG_REO_CMD_RING_SIZE 128 250 #define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64 251 #define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128 252 253 #define WLAN_CFG_REO_STATUS_RING_SIZE 256 254 #define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128 255 #define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048 256 257 #define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024 258 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024 259 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 1024 260 261 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096 262 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16 263 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 4096 264 265 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096 266 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16 267 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192 268 269 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048 270 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48 271 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192 272 273 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024 274 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16 275 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192 276 277 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096 278 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096 279 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384 280 281 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024 282 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024 283 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192 284 285 /* DP INI Declerations */ 286 #define CFG_DP_HTT_PACKET_TYPE \ 287 CFG_INI_UINT("dp_htt_packet_type", \ 288 WLAN_CFG_HTT_PKT_TYPE_MIN, \ 289 WLAN_CFG_HTT_PKT_TYPE_MAX, \ 290 WLAN_CFG_HTT_PKT_TYPE, \ 291 CFG_VALUE_OR_DEFAULT, "DP HTT packet type") 292 293 #define CFG_DP_INT_BATCH_THRESHOLD_OTHER \ 294 CFG_INI_UINT("dp_int_batch_threshold_other", \ 295 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \ 296 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \ 297 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \ 298 CFG_VALUE_OR_DEFAULT, "DP INT threshold Other") 299 300 #define CFG_DP_INT_BATCH_THRESHOLD_RX \ 301 CFG_INI_UINT("dp_int_batch_threshold_rx", \ 302 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \ 303 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \ 304 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \ 305 CFG_VALUE_OR_DEFAULT, "DP INT threshold Rx") 306 307 #define CFG_DP_INT_BATCH_THRESHOLD_TX \ 308 CFG_INI_UINT("dp_int_batch_threshold_tx", \ 309 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \ 310 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \ 311 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \ 312 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx") 313 314 #define CFG_DP_INT_TIMER_THRESHOLD_OTHER \ 315 CFG_INI_UINT("dp_int_timer_threshold_other", \ 316 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \ 317 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \ 318 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \ 319 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other") 320 321 #define CFG_DP_INT_TIMER_THRESHOLD_RX \ 322 CFG_INI_UINT("dp_int_timer_threshold_rx", \ 323 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \ 324 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \ 325 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \ 326 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx") 327 328 #define CFG_DP_INT_TIMER_THRESHOLD_TX \ 329 CFG_INI_UINT("dp_int_timer_threshold_tx", \ 330 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \ 331 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \ 332 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \ 333 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx") 334 335 #define CFG_DP_MAX_ALLOC_SIZE \ 336 CFG_INI_UINT("dp_max_alloc_size", \ 337 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \ 338 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \ 339 WLAN_CFG_MAX_ALLOC_SIZE, \ 340 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size") 341 342 #define CFG_DP_MAX_CLIENTS \ 343 CFG_INI_UINT("dp_max_clients", \ 344 WLAN_CFG_MAX_CLIENTS_MIN, \ 345 WLAN_CFG_MAX_CLIENTS_MAX, \ 346 WLAN_CFG_MAX_CLIENTS, \ 347 CFG_VALUE_OR_DEFAULT, "DP Max Clients") 348 349 #define CFG_DP_MAX_PEER_ID \ 350 CFG_INI_UINT("dp_max_peer_id", \ 351 WLAN_CFG_MAX_PEER_ID_MIN, \ 352 WLAN_CFG_MAX_PEER_ID_MAX, \ 353 WLAN_CFG_MAX_PEER_ID, \ 354 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID") 355 356 #define CFG_DP_REO_DEST_RINGS \ 357 CFG_INI_UINT("dp_reo_dest_rings", \ 358 WLAN_CFG_NUM_REO_DEST_RING_MIN, \ 359 WLAN_CFG_NUM_REO_DEST_RING_MAX, \ 360 WLAN_CFG_NUM_REO_DEST_RING, \ 361 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings") 362 363 #define CFG_DP_TCL_DATA_RINGS \ 364 CFG_INI_UINT("dp_tcl_data_rings", \ 365 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \ 366 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \ 367 WLAN_CFG_NUM_TCL_DATA_RINGS, \ 368 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings") 369 370 #define CFG_DP_TX_DESC \ 371 CFG_INI_UINT("dp_tx_desc", \ 372 WLAN_CFG_NUM_TX_DESC_MIN, \ 373 WLAN_CFG_NUM_TX_DESC_MAX, \ 374 WLAN_CFG_NUM_TX_DESC, \ 375 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors") 376 377 #define CFG_DP_TX_EXT_DESC \ 378 CFG_INI_UINT("dp_tx_ext_desc", \ 379 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \ 380 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \ 381 WLAN_CFG_NUM_TX_EXT_DESC, \ 382 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors") 383 384 #define CFG_DP_TX_EXT_DESC_POOLS \ 385 CFG_INI_UINT("dp_tx_ext_desc_pool", \ 386 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \ 387 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \ 388 WLAN_CFG_NUM_TXEXT_DESC_POOL, \ 389 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool") 390 391 #define CFG_DP_PDEV_RX_RING \ 392 CFG_INI_UINT("dp_pdev_rx_ring", \ 393 WLAN_CFG_PER_PDEV_RX_RING_MIN, \ 394 WLAN_CFG_PER_PDEV_RX_RING_MAX, \ 395 WLAN_CFG_PER_PDEV_RX_RING, \ 396 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring") 397 398 #define CFG_DP_PDEV_TX_RING \ 399 CFG_INI_UINT("dp_pdev_tx_ring", \ 400 WLAN_CFG_PER_PDEV_TX_RING_MIN, \ 401 WLAN_CFG_PER_PDEV_TX_RING_MAX, \ 402 WLAN_CFG_PER_PDEV_TX_RING, \ 403 CFG_VALUE_OR_DEFAULT, \ 404 "DP PDEV Tx Ring") 405 406 #define CFG_DP_RX_DEFRAG_TIMEOUT \ 407 CFG_INI_UINT("dp_rx_defrag_timeout", \ 408 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \ 409 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \ 410 WLAN_CFG_RX_DEFRAG_TIMEOUT, \ 411 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout") 412 413 #define CFG_DP_TX_COMPL_RING_SIZE \ 414 CFG_INI_UINT("dp_tx_compl_ring_size", \ 415 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \ 416 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \ 417 WLAN_CFG_TX_COMP_RING_SIZE, \ 418 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size") 419 420 #define CFG_DP_TX_RING_SIZE \ 421 CFG_INI_UINT("dp_tx_ring_size", \ 422 WLAN_CFG_TX_RING_SIZE_MIN,\ 423 WLAN_CFG_TX_RING_SIZE_MAX,\ 424 WLAN_CFG_TX_RING_SIZE,\ 425 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size") 426 427 #define CFG_DP_NSS_COMP_RING_SIZE \ 428 CFG_INI_UINT("dp_nss_comp_ring_size", \ 429 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \ 430 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \ 431 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \ 432 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size") 433 434 #define CFG_DP_PDEV_LMAC_RING \ 435 CFG_INI_UINT("dp_pdev_lmac_ring", \ 436 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \ 437 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \ 438 WLAN_CFG_PER_PDEV_LMAC_RING, \ 439 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring") 440 441 #define CFG_DP_BASE_HW_MAC_ID \ 442 CFG_INI_UINT("dp_base_hw_macid", \ 443 0, 1, 1, \ 444 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID") 445 446 #define CFG_DP_RX_HASH \ 447 CFG_INI_BOOL("dp_rx_hash", true, \ 448 "DP Rx Hash") 449 450 #define CFG_DP_TSO \ 451 CFG_INI_BOOL("TSOEnable", false, \ 452 "DP TSO Enabled") 453 454 #define CFG_DP_LRO \ 455 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \ 456 "DP LRO Enable") 457 458 #define CFG_DP_SG \ 459 CFG_INI_BOOL("dp_sg_support", false, \ 460 "DP SG Enable") 461 462 #define CFG_DP_GRO \ 463 CFG_INI_BOOL("GROEnable", false, \ 464 "DP GRO Enable") 465 466 #define CFG_DP_OL_TX_CSUM \ 467 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \ 468 "DP tx csum Enable") 469 470 #define CFG_DP_OL_RX_CSUM \ 471 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \ 472 "DP rx csum Enable") 473 474 #define CFG_DP_RAWMODE \ 475 CFG_INI_BOOL("dp_rawmode_support", false, \ 476 "DP rawmode Enable") 477 478 #define CFG_DP_PEER_FLOW_CTRL \ 479 CFG_INI_BOOL("dp_peer_flow_control_support", false, \ 480 "DP peer flow ctrl Enable") 481 482 #define CFG_DP_NAPI \ 483 CFG_INI_BOOL("dp_napi_enabled", MCL_OR_WIN_VALUE(true, false), \ 484 "DP Napi Enabled") 485 486 #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \ 487 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \ 488 "DP TCP UDP Checksum Offload") 489 490 #define CFG_DP_DEFRAG_TIMEOUT_CHECK \ 491 CFG_INI_BOOL("dp_defrag_timeout_check", true, \ 492 "DP Defrag Timeout Check") 493 494 #define CFG_DP_WBM_RELEASE_RING \ 495 CFG_INI_UINT("dp_wbm_release_ring", \ 496 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \ 497 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \ 498 WLAN_CFG_WBM_RELEASE_RING_SIZE, \ 499 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring") 500 501 #define CFG_DP_TCL_CMD_RING \ 502 CFG_INI_UINT("dp_tcl_cmd_ring", \ 503 WLAN_CFG_TCL_CMD_RING_SIZE_MIN, \ 504 WLAN_CFG_TCL_CMD_RING_SIZE_MAX, \ 505 WLAN_CFG_TCL_CMD_RING_SIZE, \ 506 CFG_VALUE_OR_DEFAULT, "DP TCL command ring") 507 508 #define CFG_DP_TCL_STATUS_RING \ 509 CFG_INI_UINT("dp_tcl_status_ring",\ 510 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \ 511 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \ 512 WLAN_CFG_TCL_STATUS_RING_SIZE, \ 513 CFG_VALUE_OR_DEFAULT, "DP TCL status ring") 514 515 #define CFG_DP_REO_REINJECT_RING \ 516 CFG_INI_UINT("dp_reo_reinject_ring", \ 517 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \ 518 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \ 519 WLAN_CFG_REO_REINJECT_RING_SIZE, \ 520 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring") 521 522 #define CFG_DP_RX_RELEASE_RING \ 523 CFG_INI_UINT("dp_rx_release_ring", \ 524 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \ 525 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \ 526 WLAN_CFG_RX_RELEASE_RING_SIZE, \ 527 CFG_VALUE_OR_DEFAULT, "DP Rx release ring") 528 529 #define CFG_DP_REO_EXCEPTION_RING \ 530 CFG_INI_UINT("dp_reo_exception_ring", \ 531 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \ 532 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \ 533 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \ 534 CFG_VALUE_OR_DEFAULT, "DP REO exception ring") 535 536 #define CFG_DP_REO_CMD_RING \ 537 CFG_INI_UINT("dp_reo_cmd_ring", \ 538 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \ 539 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \ 540 WLAN_CFG_REO_CMD_RING_SIZE, \ 541 CFG_VALUE_OR_DEFAULT, "DP REO command ring") 542 543 #define CFG_DP_REO_STATUS_RING \ 544 CFG_INI_UINT("dp_reo_status_ring", \ 545 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \ 546 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \ 547 WLAN_CFG_REO_STATUS_RING_SIZE, \ 548 CFG_VALUE_OR_DEFAULT, "DP REO status ring") 549 550 #define CFG_DP_RXDMA_BUF_RING \ 551 CFG_INI_UINT("dp_rxdma_buf_ring", \ 552 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \ 553 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \ 554 WLAN_CFG_RXDMA_BUF_RING_SIZE, \ 555 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring") 556 557 #define CFG_DP_RXDMA_REFILL_RING \ 558 CFG_INI_UINT("dp_rxdma_refill_ring", \ 559 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \ 560 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \ 561 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \ 562 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring") 563 564 #define CFG_DP_RXDMA_MONITOR_BUF_RING \ 565 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \ 566 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \ 567 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \ 568 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \ 569 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring") 570 571 #define CFG_DP_RXDMA_MONITOR_DST_RING \ 572 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \ 573 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \ 574 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \ 575 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \ 576 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 577 578 #define CFG_DP_RXDMA_MONITOR_STATUS_RING \ 579 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \ 580 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \ 581 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \ 582 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \ 583 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring") 584 585 #define CFG_DP_RXDMA_MONITOR_DESC_RING \ 586 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \ 587 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \ 588 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \ 589 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \ 590 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 591 592 #define CFG_DP_RXDMA_ERR_DST_RING \ 593 CFG_INI_UINT("dp_rxdma_err_dst_ring", \ 594 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \ 595 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \ 596 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \ 597 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring") 598 599 #define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \ 600 CFG_INI_UINT("TxFlowStartQueueOffset", \ 601 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \ 602 CFG_VALUE_OR_DEFAULT, "Start queue offset") 603 604 #define CFG_DP_TX_FLOW_STOP_QUEUE_TH \ 605 CFG_INI_UINT("TxFlowStopQueueThreshold", \ 606 0, 50, 15, \ 607 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold") 608 609 #define CFG_DP_IPA_UC_TX_BUF_SIZE \ 610 CFG_INI_UINT("IpaUcTxBufSize", \ 611 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \ 612 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size") 613 614 #define CFG_DP_IPA_UC_TX_PARTITION_BASE \ 615 CFG_INI_UINT("IpaUcTxPartitionBase", \ 616 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \ 617 CFG_VALUE_OR_DEFAULT, "IPA tx partition base") 618 619 #define CFG_DP_IPA_UC_RX_IND_RING_COUNT \ 620 CFG_INI_UINT("IpaUcRxIndRingCount", \ 621 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \ 622 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count") 623 624 #define CFG_DP_REORDER_OFFLOAD_SUPPORT \ 625 CFG_INI_UINT("gReorderOffloadSupported", \ 626 0, 1, 1, \ 627 CFG_VALUE_OR_DEFAULT, "Packet reordering offload to firmware") 628 629 #define CFG_DP_AP_STA_SECURITY_SEPERATION \ 630 CFG_INI_BOOL("gDisableIntraBssFwd", \ 631 false, "Disable intrs BSS Rx packets") 632 633 #define CFG_DP_ENABLE_DATA_STALL_DETECTION \ 634 CFG_INI_BOOL("gEnableDataStallDetection", \ 635 true, "Enable/Disable Data stall detection") 636 637 #define CFG_DP \ 638 CFG(CFG_DP_HTT_PACKET_TYPE) \ 639 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \ 640 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \ 641 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \ 642 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \ 643 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \ 644 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \ 645 CFG(CFG_DP_MAX_ALLOC_SIZE) \ 646 CFG(CFG_DP_MAX_CLIENTS) \ 647 CFG(CFG_DP_MAX_PEER_ID) \ 648 CFG(CFG_DP_REO_DEST_RINGS) \ 649 CFG(CFG_DP_TCL_DATA_RINGS) \ 650 CFG(CFG_DP_TX_DESC) \ 651 CFG(CFG_DP_TX_EXT_DESC) \ 652 CFG(CFG_DP_TX_EXT_DESC_POOLS) \ 653 CFG(CFG_DP_PDEV_RX_RING) \ 654 CFG(CFG_DP_PDEV_TX_RING) \ 655 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \ 656 CFG(CFG_DP_TX_COMPL_RING_SIZE) \ 657 CFG(CFG_DP_TX_RING_SIZE) \ 658 CFG(CFG_DP_NSS_COMP_RING_SIZE) \ 659 CFG(CFG_DP_PDEV_LMAC_RING) \ 660 CFG(CFG_DP_BASE_HW_MAC_ID) \ 661 CFG(CFG_DP_RX_HASH) \ 662 CFG(CFG_DP_TSO) \ 663 CFG(CFG_DP_LRO) \ 664 CFG(CFG_DP_SG) \ 665 CFG(CFG_DP_GRO) \ 666 CFG(CFG_DP_OL_TX_CSUM) \ 667 CFG(CFG_DP_OL_RX_CSUM) \ 668 CFG(CFG_DP_RAWMODE) \ 669 CFG(CFG_DP_PEER_FLOW_CTRL) \ 670 CFG(CFG_DP_NAPI) \ 671 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \ 672 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \ 673 CFG(CFG_DP_WBM_RELEASE_RING) \ 674 CFG(CFG_DP_TCL_CMD_RING) \ 675 CFG(CFG_DP_TCL_STATUS_RING) \ 676 CFG(CFG_DP_REO_REINJECT_RING) \ 677 CFG(CFG_DP_RX_RELEASE_RING) \ 678 CFG(CFG_DP_REO_EXCEPTION_RING) \ 679 CFG(CFG_DP_REO_CMD_RING) \ 680 CFG(CFG_DP_REO_STATUS_RING) \ 681 CFG(CFG_DP_RXDMA_BUF_RING) \ 682 CFG(CFG_DP_RXDMA_REFILL_RING) \ 683 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \ 684 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \ 685 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \ 686 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \ 687 CFG(CFG_DP_RXDMA_ERR_DST_RING) \ 688 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \ 689 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \ 690 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \ 691 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \ 692 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \ 693 CFG(CFG_DP_REORDER_OFFLOAD_SUPPORT) \ 694 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \ 695 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) 696 697 #endif /* _CFG_DP_H_ */ 698