1126db5dbSVivek /* 247b1fe64SKarthik Kantamneni * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 3afe07d8aSNanda Krishnan * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4126db5dbSVivek * 5126db5dbSVivek * Permission to use, copy, modify, and/or distribute this software for 6126db5dbSVivek * any purpose with or without fee is hereby granted, provided that the 7126db5dbSVivek * above copyright notice and this permission notice appear in all 8126db5dbSVivek * copies. 9126db5dbSVivek * 10126db5dbSVivek * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11126db5dbSVivek * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12126db5dbSVivek * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13126db5dbSVivek * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14126db5dbSVivek * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15126db5dbSVivek * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16126db5dbSVivek * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17126db5dbSVivek * PERFORMANCE OF THIS SOFTWARE. 18126db5dbSVivek */ 19126db5dbSVivek 20126db5dbSVivek /** 21126db5dbSVivek * DOC: This file contains definitions of Data Path configuration. 22126db5dbSVivek */ 23126db5dbSVivek 24126db5dbSVivek #ifndef _CFG_DP_H_ 25126db5dbSVivek #define _CFG_DP_H_ 26126db5dbSVivek 27126db5dbSVivek #include "cfg_define.h" 28af887c11SMohit Khanna #include "wlan_init_cfg.h" 29126db5dbSVivek 30126db5dbSVivek #define WLAN_CFG_MAX_CLIENTS 64 314cce3e03SPratik Gandhi #define WLAN_CFG_MAX_CLIENTS_MIN 8 32126db5dbSVivek #define WLAN_CFG_MAX_CLIENTS_MAX 64 33126db5dbSVivek 34126db5dbSVivek /* Change this to a lower value to enforce scattered idle list mode */ 35126db5dbSVivek #define WLAN_CFG_MAX_ALLOC_SIZE 0x200000 363c05f972Ssumedh baikady #define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000 37126db5dbSVivek #define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000 38126db5dbSVivek 3904f0ad49Shangtian #if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \ 4004f0ad49Shangtian defined(QCA_LL_PDEV_TX_FLOW_CONTROL) 4160ac9aa0Sjitiphil #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10 4260ac9aa0Sjitiphil #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15 43126db5dbSVivek #else 4460ac9aa0Sjitiphil #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 4560ac9aa0Sjitiphil #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 46126db5dbSVivek #endif 47126db5dbSVivek 48126db5dbSVivek #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0 49126db5dbSVivek #define WLAN_CFG_PER_PDEV_TX_RING_MAX 1 50126db5dbSVivek 51126db5dbSVivek #ifdef IPA_OFFLOAD 5281179cb7SMohit Khanna /* Size of TCL TX Ring */ 5328b4573dSManjunathappa Prakash #if defined(TX_TO_NPEERS_INC_TX_DESCS) 5428b4573dSManjunathappa Prakash #define WLAN_CFG_TX_RING_SIZE 2048 5528b4573dSManjunathappa Prakash #else 5681179cb7SMohit Khanna #define WLAN_CFG_TX_RING_SIZE 1024 5728b4573dSManjunathappa Prakash #endif 587de632a4SManjunathappa Prakash 594d49e53cSJia Ding #define WLAN_CFG_IPA_TX_RING_SIZE_MIN 512 607de632a4SManjunathappa Prakash #define WLAN_CFG_IPA_TX_RING_SIZE 1024 614d49e53cSJia Ding #define WLAN_CFG_IPA_TX_RING_SIZE_MAX 0x80000 62b5a3efabSYeshwanth Sriram Guntuka 634d49e53cSJia Ding #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN 512 647de632a4SManjunathappa Prakash #define WLAN_CFG_IPA_TX_COMP_RING_SIZE 1024 654d49e53cSJia Ding #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX 0x80000 667de632a4SManjunathappa Prakash 6714d9d6d6Schunquan #ifdef IPA_WDI3_TX_TWO_PIPES 68e41f2e05Schunquan #ifdef WLAN_MEMORY_OPT 69e41f2e05Schunquan #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN 128 70e41f2e05Schunquan #else 714d49e53cSJia Ding #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN 512 72e41f2e05Schunquan #endif 7314d9d6d6Schunquan #define WLAN_CFG_IPA_TX_ALT_RING_SIZE 1024 744d49e53cSJia Ding #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX 0x80000 7514d9d6d6Schunquan 76e41f2e05Schunquan #ifdef WLAN_MEMORY_OPT 77e41f2e05Schunquan #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN 128 78e41f2e05Schunquan #else 794d49e53cSJia Ding #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN 512 80e41f2e05Schunquan #endif 8114d9d6d6Schunquan #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE 1024 824d49e53cSJia Ding #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX 0x80000 8314d9d6d6Schunquan #endif 8414d9d6d6Schunquan 8560ac9aa0Sjitiphil #define WLAN_CFG_PER_PDEV_TX_RING 0 8660ac9aa0Sjitiphil #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048 8760ac9aa0Sjitiphil #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000 8860ac9aa0Sjitiphil #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024 89126db5dbSVivek #else 90126db5dbSVivek #define WLAN_CFG_TX_RING_SIZE 512 91f49b3a17SHimanshu Batra #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 9260ac9aa0Sjitiphil #define WLAN_CFG_PER_PDEV_TX_RING 1 93f49b3a17SHimanshu Batra #else 94f49b3a17SHimanshu Batra #define WLAN_CFG_PER_PDEV_TX_RING 0 95f49b3a17SHimanshu Batra #endif 9660ac9aa0Sjitiphil #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 9760ac9aa0Sjitiphil #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 9860ac9aa0Sjitiphil #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 99f49b3a17SHimanshu Batra #endif /* IPA_OFFLOAD */ 100f49b3a17SHimanshu Batra 10173465714SRuben Columbus #define WLAN_CFG_TIME_CONTROL_BP 3000 10273465714SRuben Columbus 103ecf3b36aSAbhishek Suryawanshi #if defined(RX_DATA_BUFFER_SIZE) 104ecf3b36aSAbhishek Suryawanshi #define WLAN_CFG_RX_BUFFER_SIZE RX_DATA_BUFFER_SIZE 105ecf3b36aSAbhishek Suryawanshi #else 10670b5c653SRuben Columbus #define WLAN_CFG_RX_BUFFER_SIZE 2048 107ecf3b36aSAbhishek Suryawanshi #endif 10870b5c653SRuben Columbus 109d8334769SRuben Columbus #define WLAN_CFG_QREF_CONTROL_SIZE 0 110d8334769SRuben Columbus 111f49b3a17SHimanshu Batra #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 112f49b3a17SHimanshu Batra #define WLAN_CFG_PER_PDEV_RX_RING 0 113f49b3a17SHimanshu Batra #define WLAN_CFG_PER_PDEV_LMAC_RING 0 114f49b3a17SHimanshu Batra #define WLAN_LRO_ENABLE 0 1150562ed7aSKarthik Kantamneni #if defined(QCA_WIFI_QCA6750) || defined(QCA_WIFI_WCN6450) 116f49b3a17SHimanshu Batra #define WLAN_CFG_MAC_PER_TARGET 1 117f49b3a17SHimanshu Batra #else 118f49b3a17SHimanshu Batra #define WLAN_CFG_MAC_PER_TARGET 2 119126db5dbSVivek #endif 12028b4573dSManjunathappa Prakash 12128b4573dSManjunathappa Prakash #if defined(TX_TO_NPEERS_INC_TX_DESCS) 12228b4573dSManjunathappa Prakash #define WLAN_CFG_TX_COMP_RING_SIZE 4096 12328b4573dSManjunathappa Prakash 12428b4573dSManjunathappa Prakash /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 12528b4573dSManjunathappa Prakash #define WLAN_CFG_NUM_TX_DESC 4096 12628b4573dSManjunathappa Prakash #define WLAN_CFG_NUM_TX_EXT_DESC 4096 12728b4573dSManjunathappa Prakash #else 128126db5dbSVivek #define WLAN_CFG_TX_COMP_RING_SIZE 1024 129126db5dbSVivek 130126db5dbSVivek /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 131126db5dbSVivek #define WLAN_CFG_NUM_TX_DESC 1024 132126db5dbSVivek #define WLAN_CFG_NUM_TX_EXT_DESC 1024 13328b4573dSManjunathappa Prakash #endif 134126db5dbSVivek 135126db5dbSVivek /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 136126db5dbSVivek #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1 137126db5dbSVivek #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 138126db5dbSVivek 139126db5dbSVivek /* Interrupt Mitigation - Timer threshold in us */ 140126db5dbSVivek #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8 141126db5dbSVivek #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8 1420fb35416SNirav Shah 1430fb35416SNirav Shah #ifdef WLAN_DP_PER_RING_TYPE_CONFIG 1440fb35416SNirav Shah #define WLAN_CFG_INT_BATCH_THRESHOLD_RX \ 1450fb35416SNirav Shah WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 1460fb35416SNirav Shah #define WLAN_CFG_INT_TIMER_THRESHOLD_RX \ 1470fb35416SNirav Shah WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 1480fb35416SNirav Shah #else 1490fb35416SNirav Shah #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1 1500fb35416SNirav Shah #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8 1510fb35416SNirav Shah #endif 152f49b3a17SHimanshu Batra #endif /* WLAN_MAX_PDEVS */ 153126db5dbSVivek 154ba59a82eSSantosh Anbu #define WLAN_CFG_INT_BATCH_THRESHOLD_MON_DEST 1 155ba59a82eSSantosh Anbu #define WLAN_CFG_INT_TIMER_THRESHOLD_MON_DEST 256 156ba59a82eSSantosh Anbu 157e5534b19SPavankumar Nandeshwar #define WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL 0 158e5534b19SPavankumar Nandeshwar #define WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL 30 159e5534b19SPavankumar Nandeshwar 1604bb0d61aSJinwei Chen #ifdef NBUF_MEMORY_DEBUG 161f9f324f1SManikanta Pubbisetty #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0xFFFF 1624bb0d61aSJinwei Chen #else 163f9f324f1SManikanta Pubbisetty #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0x1FFFF 1644bb0d61aSJinwei Chen #endif 165db5374f0SYu Tian 1664bb0d61aSJinwei Chen #define WLAN_CFG_RX_PENDING_HL_THRESHOLD \ 1674bb0d61aSJinwei Chen WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 1684bb0d61aSJinwei Chen #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN 0 1694bb0d61aSJinwei Chen #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX 0x200000 1704bb0d61aSJinwei Chen 1714bb0d61aSJinwei Chen #define WLAN_CFG_RX_PENDING_LO_THRESHOLD \ 1724bb0d61aSJinwei Chen WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 173db5374f0SYu Tian #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN 100 1744bb0d61aSJinwei Chen #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX 0x200000 175db5374f0SYu Tian 176cb6d0c07SVenkata Sharath Chandra Manchala #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256 177664e64c1SMohit Khanna #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 512 1780fb35416SNirav Shah #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 0 179cb6d0c07SVenkata Sharath Chandra Manchala 180126db5dbSVivek #define WLAN_CFG_PER_PDEV_RX_RING_MIN 0 181126db5dbSVivek #define WLAN_CFG_PER_PDEV_RX_RING_MAX 0 182126db5dbSVivek 183126db5dbSVivek #define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0 184126db5dbSVivek #define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1 185126db5dbSVivek 186126db5dbSVivek #define WLAN_CFG_TX_RING_SIZE_MIN 512 18725390a01SManjunathappa Prakash #define WLAN_CFG_TX_RING_SIZE_MAX 0x80000 188126db5dbSVivek 18973465714SRuben Columbus #define WLAN_CFG_TIME_CONTROL_BP_MIN 3000 19073465714SRuben Columbus #define WLAN_CFG_TIME_CONTROL_BP_MAX 1800000 191ecf3b36aSAbhishek Suryawanshi /*MTU size of ethernet is 1500*/ 192ecf3b36aSAbhishek Suryawanshi #define WLAN_CFG_RX_BUFFER_SIZE_MIN 1536 19370b5c653SRuben Columbus #define WLAN_CFG_RX_BUFFER_SIZE_MAX 4096 19470b5c653SRuben Columbus 195d8334769SRuben Columbus #define WLAN_CFG_QREF_CONTROL_SIZE_MIN 0 196d8334769SRuben Columbus #define WLAN_CFG_QREF_CONTROL_SIZE_MAX 4000 197d8334769SRuben Columbus 1984cce3e03SPratik Gandhi #define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512 199126db5dbSVivek #define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000 200126db5dbSVivek 20176013e10SYu Tian #define WLAN_CFG_NUM_TX_DESC_MIN 16 202cf103046SNandha Kishore Easwaran #define WLAN_CFG_NUM_TX_DESC_MAX 0x10000 203126db5dbSVivek 20488124ec9SSreeramya Soratkal #define WLAN_CFG_NUM_TX_SPL_DESC 1024 20588124ec9SSreeramya Soratkal #define WLAN_CFG_NUM_TX_SPL_DESC_MIN 0 20688124ec9SSreeramya Soratkal #define WLAN_CFG_NUM_TX_SPL_DESC_MAX 0x1000 20788124ec9SSreeramya Soratkal 20876013e10SYu Tian #define WLAN_CFG_NUM_TX_EXT_DESC_MIN 16 209126db5dbSVivek #define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000 210126db5dbSVivek 211126db5dbSVivek #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1 212126db5dbSVivek #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256 213126db5dbSVivek 214e5534b19SPavankumar Nandeshwar #define WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MIN 0 215e5534b19SPavankumar Nandeshwar #define WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MAX 1024 216e5534b19SPavankumar Nandeshwar 2170fb35416SNirav Shah #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 0 218126db5dbSVivek #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128 219126db5dbSVivek 220cb6d0c07SVenkata Sharath Chandra Manchala #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1 221cb6d0c07SVenkata Sharath Chandra Manchala #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128 222cb6d0c07SVenkata Sharath Chandra Manchala 223cb6d0c07SVenkata Sharath Chandra Manchala #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1 224cb6d0c07SVenkata Sharath Chandra Manchala #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128 225cb6d0c07SVenkata Sharath Chandra Manchala 226126db5dbSVivek #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1 227126db5dbSVivek #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1 228126db5dbSVivek 229ba59a82eSSantosh Anbu #define WLAN_CFG_INT_BATCH_THRESHOLD_MON_DEST_MIN 1 230ba59a82eSSantosh Anbu #define WLAN_CFG_INT_BATCH_THRESHOLD_MON_DEST_MAX 64 231ba59a82eSSantosh Anbu 232126db5dbSVivek #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8 233d1bd5ce9SVivek #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 1000 234126db5dbSVivek 235e5534b19SPavankumar Nandeshwar #define WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MIN 8 236e5534b19SPavankumar Nandeshwar #define WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MAX 1000 237e5534b19SPavankumar Nandeshwar 238126db5dbSVivek #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8 239126db5dbSVivek #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500 240126db5dbSVivek 241126db5dbSVivek #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8 242126db5dbSVivek #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000 243126db5dbSVivek 244ba59a82eSSantosh Anbu #define WLAN_CFG_INT_TIMER_THRESHOLD_MON_DEST_MIN 256 245ba59a82eSSantosh Anbu #define WLAN_CFG_INT_TIMER_THRESHOLD_MON_DEST_MAX 1000 246ba59a82eSSantosh Anbu 247cb6d0c07SVenkata Sharath Chandra Manchala #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8 24855299c2bSVenkata Sharath Chandra Manchala #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 512 249cb6d0c07SVenkata Sharath Chandra Manchala 250cb6d0c07SVenkata Sharath Chandra Manchala #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8 251cb6d0c07SVenkata Sharath Chandra Manchala #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500 252cb6d0c07SVenkata Sharath Chandra Manchala 2537d991b3fSAniruddha Paul #define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000 2547d991b3fSAniruddha Paul #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000 2551b267242SAniruddha Paul #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000 256126db5dbSVivek 257126db5dbSVivek #ifdef QCA_LL_TX_FLOW_CONTROL_V2 258126db5dbSVivek 259126db5dbSVivek /* Per vdev pools */ 260126db5dbSVivek #define WLAN_CFG_NUM_TX_DESC_POOL 3 261126db5dbSVivek #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 262126db5dbSVivek 263126db5dbSVivek #else /* QCA_LL_TX_FLOW_CONTROL_V2 */ 264126db5dbSVivek 265126db5dbSVivek #ifdef TX_PER_PDEV_DESC_POOL 266126db5dbSVivek #define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT 267126db5dbSVivek #define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT 268126db5dbSVivek 269126db5dbSVivek #else /* TX_PER_PDEV_DESC_POOL */ 270126db5dbSVivek 271126db5dbSVivek #define WLAN_CFG_NUM_TX_DESC_POOL 3 272126db5dbSVivek #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 273126db5dbSVivek 274126db5dbSVivek #endif /* TX_PER_PDEV_DESC_POOL */ 275126db5dbSVivek #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */ 276126db5dbSVivek 277126db5dbSVivek #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1 278126db5dbSVivek #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4 279126db5dbSVivek 280126db5dbSVivek #define WLAN_CFG_HTT_PKT_TYPE 2 281126db5dbSVivek #define WLAN_CFG_HTT_PKT_TYPE_MIN 2 282126db5dbSVivek #define WLAN_CFG_HTT_PKT_TYPE_MAX 2 283126db5dbSVivek 284126db5dbSVivek #define WLAN_CFG_MAX_PEER_ID 64 285126db5dbSVivek #define WLAN_CFG_MAX_PEER_ID_MIN 64 286126db5dbSVivek #define WLAN_CFG_MAX_PEER_ID_MAX 64 287126db5dbSVivek 288126db5dbSVivek #define WLAN_CFG_RX_DEFRAG_TIMEOUT 100 289126db5dbSVivek #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100 290126db5dbSVivek #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100 291126db5dbSVivek 292126db5dbSVivek #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 2936c7d7a2bSYeshwanth Sriram Guntuka #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 1 294af887c11SMohit Khanna #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX MAX_TCL_DATA_RINGS 295126db5dbSVivek 2965f8681ffSNeha Bisht #define WLAN_CFG_NUM_TX_COMP_RINGS WLAN_CFG_NUM_TCL_DATA_RINGS 2975f8681ffSNeha Bisht #define WLAN_CFG_NUM_TX_COMP_RINGS_MIN WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 2985f8681ffSNeha Bisht #define WLAN_CFG_NUM_TX_COMP_RINGS_MAX WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 2995f8681ffSNeha Bisht 300cebffa80SManjunathappa Prakash #if defined(CONFIG_BERYLLIUM) 301cebffa80SManjunathappa Prakash #define WLAN_CFG_NUM_REO_DEST_RING 8 302cebffa80SManjunathappa Prakash #else 303126db5dbSVivek #define WLAN_CFG_NUM_REO_DEST_RING 4 304cebffa80SManjunathappa Prakash #endif 305126db5dbSVivek #define WLAN_CFG_NUM_REO_DEST_RING_MIN 4 306af887c11SMohit Khanna #define WLAN_CFG_NUM_REO_DEST_RING_MAX MAX_REO_DEST_RINGS 307126db5dbSVivek 30895b9a6e6Sphadiman #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS 2 30995b9a6e6Sphadiman #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN 1 31095b9a6e6Sphadiman #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX 3 31195b9a6e6Sphadiman 31295b9a6e6Sphadiman #define WLAN_CFG_NSS_NUM_REO_DEST_RING 2 31395b9a6e6Sphadiman #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN 1 31495b9a6e6Sphadiman #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX 3 31595b9a6e6Sphadiman 316018b298dSRakesh Pillai #define WLAN_CFG_WBM_RELEASE_RING_SIZE 1024 317126db5dbSVivek #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64 318018b298dSRakesh Pillai #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 1024 319126db5dbSVivek 320737949c6SRuben Columbus #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE 512 321f63aaef3SAnkit Kumar #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN 32 322737949c6SRuben Columbus #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX 512 323126db5dbSVivek 324126db5dbSVivek #define WLAN_CFG_TCL_STATUS_RING_SIZE 32 325126db5dbSVivek #define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32 326126db5dbSVivek #define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32 327126db5dbSVivek 328126db5dbSVivek #if defined(QCA_WIFI_QCA6290) 329126db5dbSVivek #define WLAN_CFG_REO_DST_RING_SIZE 1024 330126db5dbSVivek #else 331126db5dbSVivek #define WLAN_CFG_REO_DST_RING_SIZE 2048 332126db5dbSVivek #endif 333126db5dbSVivek 3344fa2c22cSChaithanya Garrepalli #define WLAN_CFG_REO_DST_RING_SIZE_MIN 8 3354fa2c22cSChaithanya Garrepalli #define WLAN_CFG_REO_DST_RING_SIZE_MAX 8192 336126db5dbSVivek 3377bad5a8cSRakesh Pillai #define WLAN_CFG_REO_REINJECT_RING_SIZE 128 338126db5dbSVivek #define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32 3397bad5a8cSRakesh Pillai #define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 128 340126db5dbSVivek 341126db5dbSVivek #define WLAN_CFG_RX_RELEASE_RING_SIZE 1024 3424cce3e03SPratik Gandhi #define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8 34374bbfc8aSAlok Kumar #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 344ad282971Ssandhu defined(QCA_WIFI_QCA6750) || defined(QCA_WIFI_KIWI) 345126db5dbSVivek #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024 3460ef58eecSTallapragada Kalyan #else 3473ed8f4daSChaithanya Garrepalli #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 32768 3480ef58eecSTallapragada Kalyan #endif 349126db5dbSVivek 350f2c65a9bSYeshwanth Sriram Guntuka #define WLAN_CFG_REO_EXCEPTION_RING_SIZE 256 351126db5dbSVivek #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128 352f2c65a9bSYeshwanth Sriram Guntuka #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 512 353126db5dbSVivek 35426ebbe44SKarunakar Dasineni #define WLAN_CFG_REO_CMD_RING_SIZE 128 355126db5dbSVivek #define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64 35626ebbe44SKarunakar Dasineni #define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128 357126db5dbSVivek 35826ebbe44SKarunakar Dasineni #define WLAN_CFG_REO_STATUS_RING_SIZE 256 359126db5dbSVivek #define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128 3601f1acf59SKarunakar Dasineni #define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048 361126db5dbSVivek 362126db5dbSVivek #define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024 363e41f2e05Schunquan #ifdef WLAN_MEMORY_OPT 364e41f2e05Schunquan #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 128 365e41f2e05Schunquan #else 366126db5dbSVivek #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024 367e41f2e05Schunquan #endif 36897b39750SDevender Kumar #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 8192 369126db5dbSVivek 370126db5dbSVivek #define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096 3714cce3e03SPratik Gandhi #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16 37206c5d971SRakesh Pillai #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 16384 373126db5dbSVivek 37436ce817bSPrathyusha Guduri #define WLAN_CFG_TX_DESC_LIMIT_0 0 37536ce817bSPrathyusha Guduri #define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096 37636ce817bSPrathyusha Guduri #define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768 37736ce817bSPrathyusha Guduri 37836ce817bSPrathyusha Guduri #define WLAN_CFG_TX_DESC_LIMIT_1 0 37936ce817bSPrathyusha Guduri #define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096 38036ce817bSPrathyusha Guduri #define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768 38136ce817bSPrathyusha Guduri 38236ce817bSPrathyusha Guduri #define WLAN_CFG_TX_DESC_LIMIT_2 0 38336ce817bSPrathyusha Guduri #define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096 38436ce817bSPrathyusha Guduri #define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768 38536ce817bSPrathyusha Guduri 386aed67e19SPrathyusha Guduri #define WLAN_CFG_TX_DEVICE_LIMIT 65536 387aed67e19SPrathyusha Guduri #define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384 388aed67e19SPrathyusha Guduri #define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536 389aed67e19SPrathyusha Guduri 3906eba2a44SSreeramya Soratkal #define WLAN_CFG_TX_SPL_DEVICE_LIMIT 1024 3916eba2a44SSreeramya Soratkal #define WLAN_CFG_TX_SPL_DEVICE_LIMIT_MIN 0 3926eba2a44SSreeramya Soratkal #define WLAN_CFG_TX_SPL_DEVICE_LIMIT_MAX 4096 3936eba2a44SSreeramya Soratkal 394abac9eedSPrathyusha Guduri #define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024 395abac9eedSPrathyusha Guduri #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128 396abac9eedSPrathyusha Guduri #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024 397abac9eedSPrathyusha Guduri 39830bc8285SNeha Bisht #define WLAN_CFG_TX_DESC_GLOBAL_COUNT 0xC000 39930bc8285SNeha Bisht #define WLAN_CFG_TX_DESC_GLOBAL_COUNT_MIN 0x8000 40030bc8285SNeha Bisht #define WLAN_CFG_TX_DESC_GLOBAL_COUNT_MAX 0x60000 40130bc8285SNeha Bisht 40230bc8285SNeha Bisht #define WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT 0x400 40330bc8285SNeha Bisht #define WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT_MIN 0x400 40430bc8285SNeha Bisht #define WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT_MAX 0x1000 40530bc8285SNeha Bisht 406126db5dbSVivek #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096 4074cce3e03SPratik Gandhi #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16 408692850bdSKai Chen #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192 409126db5dbSVivek 41077f30290SNandha Kishore Easwaran #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE 4096 411df329ebbSNaga #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN 16 412df329ebbSNaga #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX 8192 413df329ebbSNaga 414126db5dbSVivek #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048 4154cce3e03SPratik Gandhi #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48 416692850bdSKai Chen #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192 417126db5dbSVivek 418df329ebbSNaga #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE 2048 419df329ebbSNaga #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN 48 42077f30290SNandha Kishore Easwaran #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX 8192 421df329ebbSNaga 422126db5dbSVivek #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024 4234cce3e03SPratik Gandhi #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16 424692850bdSKai Chen #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192 425126db5dbSVivek 426126db5dbSVivek #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096 427126db5dbSVivek #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096 428692850bdSKai Chen #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384 429126db5dbSVivek 430748fe0b6SVenkateswara Naralasetty #define WLAN_CFG_SW2RXDMA_LINK_RING_SIZE 1024 431748fe0b6SVenkateswara Naralasetty #define WLAN_CFG_SW2RXDMA_LINK_RING_SIZE_MIN 256 432748fe0b6SVenkateswara Naralasetty #define WLAN_CFG_SW2RXDMA_LINK_RING_SIZE_MAX 4096 433748fe0b6SVenkateswara Naralasetty 434126db5dbSVivek #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024 435126db5dbSVivek #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024 43679768452SKarunakar Dasineni #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192 437126db5dbSVivek 438b7a1c578SRuben Columbus #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE 32 439b7a1c578SRuben Columbus #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN 0 440b7a1c578SRuben Columbus #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX 256 441b7a1c578SRuben Columbus 442776f11b0SNanda Krishnan /* 4439550273eSMainak Sen * Allocate as many RX descriptors as buffers in the SW2RXDMA 4449550273eSMainak Sen * ring. This value may need to be tuned later. 4459550273eSMainak Sen */ 44630482aa5SDevender Kumar #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 4479550273eSMainak Sen #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 4489550273eSMainak Sen #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 4499550273eSMainak Sen #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 1 450eeaa5b74SMainak Sen #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 4512dab6c75SChunquan Luo #ifdef WLAN_MEMORY_OPT 4522dab6c75SChunquan Luo #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 128 4532dab6c75SChunquan Luo #else 454b06c25eeSGuisen Yang #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 4552dab6c75SChunquan Luo #endif 45606c5d971SRakesh Pillai #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 4579550273eSMainak Sen 458776f11b0SNanda Krishnan /* 4599550273eSMainak Sen * For low memory AP cases using 1 will reduce the rx descriptors memory req 4609550273eSMainak Sen */ 4619550273eSMainak Sen #elif defined(QCA_LOWMEM_CONFIG) || defined(QCA_512M_CONFIG) 4629550273eSMainak Sen #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 4639550273eSMainak Sen #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 4649550273eSMainak Sen #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 465eeaa5b74SMainak Sen #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 4662dab6c75SChunquan Luo #ifdef WLAN_MEMORY_OPT 4672dab6c75SChunquan Luo #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 128 4682dab6c75SChunquan Luo #else 469eeaa5b74SMainak Sen #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 4702dab6c75SChunquan Luo #endif 471cd40aa85SChaithanya Garrepalli #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 4729550273eSMainak Sen 473776f11b0SNanda Krishnan /* 4749550273eSMainak Sen * AP use cases need to allocate more RX Descriptors than the number of 47529f3ca24SJeff Johnson * entries available in the SW2RXDMA buffer replenish ring. This is to account 4769550273eSMainak Sen * for frames sitting in REO queues, HW-HW DMA rings etc. Hence using a 4779550273eSMainak Sen * multiplication factor of 3, to allocate three times as many RX descriptors 4789550273eSMainak Sen * as RX buffers. 4799550273eSMainak Sen */ 4809550273eSMainak Sen #else 4819550273eSMainak Sen #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 3 4829550273eSMainak Sen #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 4839550273eSMainak Sen #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 484eeaa5b74SMainak Sen #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 12288 4852dab6c75SChunquan Luo #ifdef WLAN_MEMORY_OPT 4862dab6c75SChunquan Luo #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 128 4872dab6c75SChunquan Luo #else 488eeaa5b74SMainak Sen #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 4096 4892dab6c75SChunquan Luo #endif 490cd40aa85SChaithanya Garrepalli #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 49130482aa5SDevender Kumar #endif 4929550273eSMainak Sen 49376aa8d51SSumeet Rao #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE 16384 49476aa8d51SSumeet Rao #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN 1 49576aa8d51SSumeet Rao #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX 16384 4961370e032SAlan Chen #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT 128 49776aa8d51SSumeet Rao 4980265d791SAlok Kumar #define WLAN_CFG_PKTLOG_BUFFER_SIZE 10 4990265d791SAlok Kumar #define WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE 1 5000265d791SAlok Kumar #define WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE 10 5010265d791SAlok Kumar 50261178a76SPrakash Manjunathappa #ifdef IPA_OFFLOAD 5038cdc1875SJinwei Chen #define WLAN_CFG_NUM_REO_RINGS_MAP 0x7 5048cdc1875SJinwei Chen #else 505e3876720SNeha Bisht #define WLAN_CFG_NUM_REO_RINGS_MAP 0xF 5068cdc1875SJinwei Chen #endif 507e3876720SNeha Bisht #define WLAN_CFG_NUM_REO_RINGS_MAP_MIN 0x1 50861178a76SPrakash Manjunathappa #if defined(CONFIG_BERYLLIUM) 50961178a76SPrakash Manjunathappa #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xFF 51061178a76SPrakash Manjunathappa #else 511e3876720SNeha Bisht #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xF 51261178a76SPrakash Manjunathappa #endif 513e3876720SNeha Bisht 5143048f538SRadha Krishna Simha Jiguru #define WLAN_CFG_RADIO_0_DEFAULT_REO 0x1 5153048f538SRadha Krishna Simha Jiguru #define WLAN_CFG_RADIO_1_DEFAULT_REO 0x2 5163048f538SRadha Krishna Simha Jiguru #define WLAN_CFG_RADIO_2_DEFAULT_REO 0x3 5173048f538SRadha Krishna Simha Jiguru 5183048f538SRadha Krishna Simha Jiguru #define WLAN_CFG_RADIO_DEFAULT_REO_MIN 0x1 5193048f538SRadha Krishna Simha Jiguru #define WLAN_CFG_RADIO_DEFAULT_REO_MAX 0x4 5203048f538SRadha Krishna Simha Jiguru 521cfe92008Ssyed touqeer pasha #define WLAN_CFG_REO2PPE_RING_SIZE 16384 5220702aaf4SChaithanya Garrepalli #define WLAN_CFG_REO2PPE_RING_SIZE_MIN 64 523bc05063eSManish Verma #define WLAN_CFG_REO2PPE_RING_SIZE_MAX 16384 5240702aaf4SChaithanya Garrepalli 525689990d5SSachin Kohli #define WLAN_CFG_PPE2TCL_RING_SIZE 8192 5260702aaf4SChaithanya Garrepalli #define WLAN_CFG_PPE2TCL_RING_SIZE_MIN 64 527776f11b0SNanda Krishnan #define WLAN_CFG_PPE2TCL_RING_SIZE_MAX 32768 5280702aaf4SChaithanya Garrepalli 5290702aaf4SChaithanya Garrepalli #define WLAN_CFG_PPE_RELEASE_RING_SIZE 1024 5300702aaf4SChaithanya Garrepalli #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MIN 64 5310702aaf4SChaithanya Garrepalli #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MAX 1024 5320702aaf4SChaithanya Garrepalli 533c42af1f6SChaithanya Garrepalli #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 534adbb7700SChaithanya Garrepalli #define WLAN_CFG_MLO_RX_RING_MAP 0x7 535c42af1f6SChaithanya Garrepalli #define WLAN_CFG_MLO_RX_RING_MAP_MIN 0x0 536c42af1f6SChaithanya Garrepalli #define WLAN_CFG_MLO_RX_RING_MAP_MAX 0xFF 537c42af1f6SChaithanya Garrepalli #endif 538c42af1f6SChaithanya Garrepalli 539986121ccSManoj Ekbote #define WLAN_CFG_TX_CAPT_MAX_MEM_MIN 0 540986121ccSManoj Ekbote #define WLAN_CFG_TX_CAPT_MAX_MEM_MAX 512 541986121ccSManoj Ekbote #define WLAN_CFG_TX_CAPT_MAX_MEM_DEFAULT 0 542986121ccSManoj Ekbote 5431507b1cdSAmit Mehta #define CFG_DP_MPDU_RETRY_THRESHOLD_MIN 0 5441507b1cdSAmit Mehta #define CFG_DP_MPDU_RETRY_THRESHOLD_MAX 255 5451507b1cdSAmit Mehta #define CFG_DP_MPDU_RETRY_THRESHOLD 0 5461507b1cdSAmit Mehta 547204b7653STallapragada Kalyan #define WLAN_CFG_DP_NAPI_SCALE_FACTOR 0 548204b7653STallapragada Kalyan #define WLAN_CFG_DP_NAPI_SCALE_FACTOR_MIN 0 549204b7653STallapragada Kalyan #define WLAN_CFG_DP_NAPI_SCALE_FACTOR_MAX 4 550204b7653STallapragada Kalyan 5510be3bb02SNitin Shetty #define CFG_DP_PPEDS_WIFI_SOC_CFG_NONE 0 5520be3bb02SNitin Shetty #define CFG_DP_PPEDS_WIFI_SOC_CFG_ALL 0xFF 5530be3bb02SNitin Shetty #define CFG_DP_PPEDS_WIFI_SOC_CFG_DEFAULT 0xFF 5540be3bb02SNitin Shetty 5553b1f7cedSVivek #ifdef CONFIG_SAWF_STATS 5563b1f7cedSVivek #define WLAN_CFG_SAWF_STATS 0x0 5573b1f7cedSVivek #define WLAN_CFG_SAWF_STATS_MIN 0x0 5583b1f7cedSVivek #define WLAN_CFG_SAWF_STATS_MAX 0x7 5593b1f7cedSVivek #endif 5603c62dfa3SSrinivas Girigowda 5616f8e9cffSnobelj #define WLAN_CFG_TX_CAPT_RBM_ID_MIN 0 5626f8e9cffSnobelj #define WLAN_CFG_TX_CAPT_RBM_ID_MAX 3 5636f8e9cffSnobelj #define WLAN_CFG_TX_CAPT_0_RBM_DEFAULT 0 5646f8e9cffSnobelj #define WLAN_CFG_TX_CAPT_1_RBM_DEFAULT 1 5656f8e9cffSnobelj #define WLAN_CFG_TX_CAPT_2_RBM_DEFAULT 2 5666f8e9cffSnobelj #define WLAN_CFG_TX_CAPT_3_RBM_DEFAULT 3 5676f8e9cffSnobelj 568*37e5a76cSAman Mehta #define WLAN_CFG_DP_AVG_RATE_FILTER_MIN 0 569*37e5a76cSAman Mehta #define WLAN_CFG_DP_AVG_RATE_FILTER_MAX 11000 570*37e5a76cSAman Mehta #define WLAN_CFG_DP_AVG_RATE_FILTER_DEFAULT 0 571*37e5a76cSAman Mehta 572986121ccSManoj Ekbote /* 573986121ccSManoj Ekbote * <ini> 574986121ccSManoj Ekbote * "dp_tx_capt_max_mem_mb"- maximum memory used by Tx capture 575986121ccSManoj Ekbote * @Min: 0 576986121ccSManoj Ekbote * @Max: 512 MB 577986121ccSManoj Ekbote * @Default: 0 (disabled) 578986121ccSManoj Ekbote * 579986121ccSManoj Ekbote * This ini entry is used to set a max limit beyond which frames 580986121ccSManoj Ekbote * are dropped by Tx capture. User needs to set a non-zero value 581986121ccSManoj Ekbote * to enable it. 582986121ccSManoj Ekbote * 583986121ccSManoj Ekbote * Usage: External 584986121ccSManoj Ekbote * 585986121ccSManoj Ekbote * </ini> 586986121ccSManoj Ekbote */ 587986121ccSManoj Ekbote #define CFG_DP_TX_CAPT_MAX_MEM_MB \ 588986121ccSManoj Ekbote CFG_INI_UINT("dp_tx_capt_max_mem_mb", \ 589986121ccSManoj Ekbote WLAN_CFG_TX_CAPT_MAX_MEM_MIN, \ 590986121ccSManoj Ekbote WLAN_CFG_TX_CAPT_MAX_MEM_MAX, \ 591986121ccSManoj Ekbote WLAN_CFG_TX_CAPT_MAX_MEM_DEFAULT, \ 592986121ccSManoj Ekbote CFG_VALUE_OR_DEFAULT, "Max Memory (in MB) used by Tx Capture") 593986121ccSManoj Ekbote 5946f8e9cffSnobelj #define CFG_DP_TX_CAPT_RADIO_0_RBM_ID \ 5956f8e9cffSnobelj CFG_INI_UINT("dp_tx_capt_pdev_0_rbm_id", \ 5966f8e9cffSnobelj WLAN_CFG_TX_CAPT_RBM_ID_MIN, \ 5976f8e9cffSnobelj WLAN_CFG_TX_CAPT_RBM_ID_MAX, \ 5986f8e9cffSnobelj WLAN_CFG_TX_CAPT_0_RBM_DEFAULT, \ 5996f8e9cffSnobelj CFG_VALUE_OR_DEFAULT, "RBM_ID used by pdev 0 Tx capture") 6006f8e9cffSnobelj 6016f8e9cffSnobelj #define CFG_DP_TX_CAPT_RADIO_1_RBM_ID \ 6026f8e9cffSnobelj CFG_INI_UINT("dp_tx_capt_pdev_1_rbm_id", \ 6036f8e9cffSnobelj WLAN_CFG_TX_CAPT_RBM_ID_MIN, \ 6046f8e9cffSnobelj WLAN_CFG_TX_CAPT_RBM_ID_MAX, \ 6056f8e9cffSnobelj WLAN_CFG_TX_CAPT_1_RBM_DEFAULT, \ 6066f8e9cffSnobelj CFG_VALUE_OR_DEFAULT, "RBM_ID used by pdev 1 Tx capture") 6076f8e9cffSnobelj 6086f8e9cffSnobelj #define CFG_DP_TX_CAPT_RADIO_2_RBM_ID \ 6096f8e9cffSnobelj CFG_INI_UINT("dp_tx_capt_pdev_2_rbm_id", \ 6106f8e9cffSnobelj WLAN_CFG_TX_CAPT_RBM_ID_MIN, \ 6116f8e9cffSnobelj WLAN_CFG_TX_CAPT_RBM_ID_MAX, \ 6126f8e9cffSnobelj WLAN_CFG_TX_CAPT_2_RBM_DEFAULT, \ 6136f8e9cffSnobelj CFG_VALUE_OR_DEFAULT, "RBM_ID used by pdev 2 Tx capture") 6146f8e9cffSnobelj 6156f8e9cffSnobelj #define CFG_DP_TX_CAPT_RADIO_3_RBM_ID \ 6166f8e9cffSnobelj CFG_INI_UINT("dp_tx_capt_pdev_3_rbm_id", \ 6176f8e9cffSnobelj WLAN_CFG_TX_CAPT_RBM_ID_MIN, \ 6186f8e9cffSnobelj WLAN_CFG_TX_CAPT_RBM_ID_MAX, \ 6196f8e9cffSnobelj WLAN_CFG_TX_CAPT_3_RBM_DEFAULT, \ 6206f8e9cffSnobelj CFG_VALUE_OR_DEFAULT, "RBM_ID used by pdev 3 Tx capture") 6216f8e9cffSnobelj 622986121ccSManoj Ekbote /* DP INI Declarations */ 623126db5dbSVivek #define CFG_DP_HTT_PACKET_TYPE \ 624126db5dbSVivek CFG_INI_UINT("dp_htt_packet_type", \ 625126db5dbSVivek WLAN_CFG_HTT_PKT_TYPE_MIN, \ 626126db5dbSVivek WLAN_CFG_HTT_PKT_TYPE_MAX, \ 627126db5dbSVivek WLAN_CFG_HTT_PKT_TYPE, \ 628126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP HTT packet type") 629126db5dbSVivek 630126db5dbSVivek #define CFG_DP_INT_BATCH_THRESHOLD_OTHER \ 631126db5dbSVivek CFG_INI_UINT("dp_int_batch_threshold_other", \ 6322b7628c8SKarunakar Dasineni WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \ 6332b7628c8SKarunakar Dasineni WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \ 6342b7628c8SKarunakar Dasineni WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \ 635cb6d0c07SVenkata Sharath Chandra Manchala CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other") 636126db5dbSVivek 637ba59a82eSSantosh Anbu #define CFG_DP_INT_BATCH_THRESHOLD_MON_DEST \ 638ba59a82eSSantosh Anbu CFG_INI_UINT("dp_int_batch_threshold_mon_dest", \ 639ba59a82eSSantosh Anbu WLAN_CFG_INT_BATCH_THRESHOLD_MON_DEST_MIN, \ 640ba59a82eSSantosh Anbu WLAN_CFG_INT_BATCH_THRESHOLD_MON_DEST_MAX, \ 641ba59a82eSSantosh Anbu WLAN_CFG_INT_BATCH_THRESHOLD_MON_DEST, \ 642ba59a82eSSantosh Anbu CFG_VALUE_OR_DEFAULT, "DP INT batch threshold mon_dest") 643ba59a82eSSantosh Anbu 644126db5dbSVivek #define CFG_DP_INT_BATCH_THRESHOLD_RX \ 645126db5dbSVivek CFG_INI_UINT("dp_int_batch_threshold_rx", \ 646126db5dbSVivek WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \ 647126db5dbSVivek WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \ 648126db5dbSVivek WLAN_CFG_INT_BATCH_THRESHOLD_RX, \ 649cb6d0c07SVenkata Sharath Chandra Manchala CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx") 650126db5dbSVivek 651126db5dbSVivek #define CFG_DP_INT_BATCH_THRESHOLD_TX \ 652126db5dbSVivek CFG_INI_UINT("dp_int_batch_threshold_tx", \ 653126db5dbSVivek WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \ 654126db5dbSVivek WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \ 655126db5dbSVivek WLAN_CFG_INT_BATCH_THRESHOLD_TX, \ 656126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx") 657126db5dbSVivek 658e5534b19SPavankumar Nandeshwar #define CFG_DP_INT_BATCH_THRESHOLD_PPE2TCL \ 659e5534b19SPavankumar Nandeshwar CFG_INI_UINT("dp_int_batch_threshold_ppe2tcl", \ 660e5534b19SPavankumar Nandeshwar WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MIN, \ 661e5534b19SPavankumar Nandeshwar WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MAX, \ 662e5534b19SPavankumar Nandeshwar WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL, \ 663e5534b19SPavankumar Nandeshwar CFG_VALUE_OR_DEFAULT, "DP INT batch threshold ppe2tcl") 664e5534b19SPavankumar Nandeshwar 665e5534b19SPavankumar Nandeshwar #define CFG_DP_INT_TIMER_THRESHOLD_PPE2TCL \ 666e5534b19SPavankumar Nandeshwar CFG_INI_UINT("dp_int_timer_threshold_ppe2tcl", \ 667e5534b19SPavankumar Nandeshwar WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MIN, \ 668e5534b19SPavankumar Nandeshwar WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MAX, \ 669e5534b19SPavankumar Nandeshwar WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL, \ 670e5534b19SPavankumar Nandeshwar CFG_VALUE_OR_DEFAULT, "DP INT timer threshold ppe2tcl") 671e5534b19SPavankumar Nandeshwar 672126db5dbSVivek #define CFG_DP_INT_TIMER_THRESHOLD_OTHER \ 673126db5dbSVivek CFG_INI_UINT("dp_int_timer_threshold_other", \ 674126db5dbSVivek WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \ 675126db5dbSVivek WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \ 676126db5dbSVivek WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \ 677126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other") 678126db5dbSVivek 679ba59a82eSSantosh Anbu #define CFG_DP_INT_TIMER_THRESHOLD_MON_DEST \ 680ba59a82eSSantosh Anbu CFG_INI_UINT("dp_int_timer_threshold_mon_dest", \ 681ba59a82eSSantosh Anbu WLAN_CFG_INT_TIMER_THRESHOLD_MON_DEST_MIN, \ 682ba59a82eSSantosh Anbu WLAN_CFG_INT_TIMER_THRESHOLD_MON_DEST_MAX, \ 683ba59a82eSSantosh Anbu WLAN_CFG_INT_TIMER_THRESHOLD_MON_DEST, \ 684ba59a82eSSantosh Anbu CFG_VALUE_OR_DEFAULT, "DP INT timer threshold mon dest") 685ba59a82eSSantosh Anbu 686126db5dbSVivek #define CFG_DP_INT_TIMER_THRESHOLD_RX \ 687126db5dbSVivek CFG_INI_UINT("dp_int_timer_threshold_rx", \ 688126db5dbSVivek WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \ 689126db5dbSVivek WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \ 690126db5dbSVivek WLAN_CFG_INT_TIMER_THRESHOLD_RX, \ 691126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx") 692126db5dbSVivek 693cb6d0c07SVenkata Sharath Chandra Manchala #define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \ 694cb6d0c07SVenkata Sharath Chandra Manchala CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \ 695cb6d0c07SVenkata Sharath Chandra Manchala WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \ 696cb6d0c07SVenkata Sharath Chandra Manchala WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \ 697cb6d0c07SVenkata Sharath Chandra Manchala WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \ 698cb6d0c07SVenkata Sharath Chandra Manchala CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring") 699cb6d0c07SVenkata Sharath Chandra Manchala 700cb6d0c07SVenkata Sharath Chandra Manchala #define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \ 701cb6d0c07SVenkata Sharath Chandra Manchala CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \ 702cb6d0c07SVenkata Sharath Chandra Manchala WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \ 703cb6d0c07SVenkata Sharath Chandra Manchala WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \ 704cb6d0c07SVenkata Sharath Chandra Manchala WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \ 705cb6d0c07SVenkata Sharath Chandra Manchala CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring") 706cb6d0c07SVenkata Sharath Chandra Manchala 707126db5dbSVivek #define CFG_DP_INT_TIMER_THRESHOLD_TX \ 708126db5dbSVivek CFG_INI_UINT("dp_int_timer_threshold_tx", \ 709126db5dbSVivek WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \ 710126db5dbSVivek WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \ 711126db5dbSVivek WLAN_CFG_INT_TIMER_THRESHOLD_TX, \ 712126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx") 713126db5dbSVivek 714126db5dbSVivek #define CFG_DP_MAX_ALLOC_SIZE \ 715126db5dbSVivek CFG_INI_UINT("dp_max_alloc_size", \ 716126db5dbSVivek WLAN_CFG_MAX_ALLOC_SIZE_MIN, \ 717126db5dbSVivek WLAN_CFG_MAX_ALLOC_SIZE_MAX, \ 718126db5dbSVivek WLAN_CFG_MAX_ALLOC_SIZE, \ 719126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size") 720126db5dbSVivek 721126db5dbSVivek #define CFG_DP_MAX_CLIENTS \ 722126db5dbSVivek CFG_INI_UINT("dp_max_clients", \ 723126db5dbSVivek WLAN_CFG_MAX_CLIENTS_MIN, \ 724126db5dbSVivek WLAN_CFG_MAX_CLIENTS_MAX, \ 725126db5dbSVivek WLAN_CFG_MAX_CLIENTS, \ 726126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP Max Clients") 727126db5dbSVivek 728126db5dbSVivek #define CFG_DP_MAX_PEER_ID \ 729126db5dbSVivek CFG_INI_UINT("dp_max_peer_id", \ 730126db5dbSVivek WLAN_CFG_MAX_PEER_ID_MIN, \ 731126db5dbSVivek WLAN_CFG_MAX_PEER_ID_MAX, \ 732126db5dbSVivek WLAN_CFG_MAX_PEER_ID, \ 733126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP Max Peer ID") 734126db5dbSVivek 735126db5dbSVivek #define CFG_DP_REO_DEST_RINGS \ 736126db5dbSVivek CFG_INI_UINT("dp_reo_dest_rings", \ 737126db5dbSVivek WLAN_CFG_NUM_REO_DEST_RING_MIN, \ 738126db5dbSVivek WLAN_CFG_NUM_REO_DEST_RING_MAX, \ 739126db5dbSVivek WLAN_CFG_NUM_REO_DEST_RING, \ 740126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings") 741126db5dbSVivek 7425f8681ffSNeha Bisht #define CFG_DP_TX_COMP_RINGS \ 7435f8681ffSNeha Bisht CFG_INI_UINT("dp_tx_comp_rings", \ 7445f8681ffSNeha Bisht WLAN_CFG_NUM_TX_COMP_RINGS_MIN, \ 7455f8681ffSNeha Bisht WLAN_CFG_NUM_TX_COMP_RINGS_MAX, \ 7465f8681ffSNeha Bisht WLAN_CFG_NUM_TX_COMP_RINGS, \ 7475f8681ffSNeha Bisht CFG_VALUE_OR_DEFAULT, "DP Tx Comp Rings") 7485f8681ffSNeha Bisht 749126db5dbSVivek #define CFG_DP_TCL_DATA_RINGS \ 750126db5dbSVivek CFG_INI_UINT("dp_tcl_data_rings", \ 751126db5dbSVivek WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \ 752126db5dbSVivek WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \ 753126db5dbSVivek WLAN_CFG_NUM_TCL_DATA_RINGS, \ 754126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings") 755126db5dbSVivek 75695b9a6e6Sphadiman #define CFG_DP_NSS_REO_DEST_RINGS \ 75795b9a6e6Sphadiman CFG_INI_UINT("dp_nss_reo_dest_rings", \ 75895b9a6e6Sphadiman WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN, \ 75995b9a6e6Sphadiman WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX, \ 76095b9a6e6Sphadiman WLAN_CFG_NSS_NUM_REO_DEST_RING, \ 76195b9a6e6Sphadiman CFG_VALUE_OR_DEFAULT, "DP NSS REO Destination Rings") 76295b9a6e6Sphadiman 76395b9a6e6Sphadiman #define CFG_DP_NSS_TCL_DATA_RINGS \ 76495b9a6e6Sphadiman CFG_INI_UINT("dp_nss_tcl_data_rings", \ 76595b9a6e6Sphadiman WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN, \ 76695b9a6e6Sphadiman WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX, \ 76795b9a6e6Sphadiman WLAN_CFG_NSS_NUM_TCL_DATA_RINGS, \ 76895b9a6e6Sphadiman CFG_VALUE_OR_DEFAULT, "DP NSS TCL Data Rings") 76995b9a6e6Sphadiman 770126db5dbSVivek #define CFG_DP_TX_DESC \ 771126db5dbSVivek CFG_INI_UINT("dp_tx_desc", \ 772126db5dbSVivek WLAN_CFG_NUM_TX_DESC_MIN, \ 773126db5dbSVivek WLAN_CFG_NUM_TX_DESC_MAX, \ 774126db5dbSVivek WLAN_CFG_NUM_TX_DESC, \ 775126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors") 776126db5dbSVivek 777ab649e06SHariharan Ramanathan #define CFG_DP_TX_DESC_POOL_3 \ 778ab649e06SHariharan Ramanathan CFG_INI_UINT("dp_tx_desc_pool_3", \ 779ab649e06SHariharan Ramanathan WLAN_CFG_NUM_TX_DESC_MIN, \ 780ab649e06SHariharan Ramanathan WLAN_CFG_NUM_TX_DESC_MAX, \ 781ab649e06SHariharan Ramanathan WLAN_CFG_NUM_TX_DESC, \ 782ab649e06SHariharan Ramanathan CFG_VALUE_OR_DEFAULT, "DP Tx Descriptor of 3rd pool") 783ab649e06SHariharan Ramanathan 78488124ec9SSreeramya Soratkal #define CFG_DP_TX_SPL_DESC \ 78588124ec9SSreeramya Soratkal CFG_INI_UINT("dp_tx_spl_desc", \ 78688124ec9SSreeramya Soratkal WLAN_CFG_NUM_TX_SPL_DESC_MIN, \ 78788124ec9SSreeramya Soratkal WLAN_CFG_NUM_TX_SPL_DESC_MAX, \ 78888124ec9SSreeramya Soratkal WLAN_CFG_NUM_TX_SPL_DESC, \ 78988124ec9SSreeramya Soratkal CFG_VALUE_OR_DEFAULT, "DP Tx Special Descriptors") 79088124ec9SSreeramya Soratkal 791126db5dbSVivek #define CFG_DP_TX_EXT_DESC \ 792126db5dbSVivek CFG_INI_UINT("dp_tx_ext_desc", \ 793126db5dbSVivek WLAN_CFG_NUM_TX_EXT_DESC_MIN, \ 794126db5dbSVivek WLAN_CFG_NUM_TX_EXT_DESC_MAX, \ 795126db5dbSVivek WLAN_CFG_NUM_TX_EXT_DESC, \ 796126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors") 797126db5dbSVivek 798126db5dbSVivek #define CFG_DP_TX_EXT_DESC_POOLS \ 799126db5dbSVivek CFG_INI_UINT("dp_tx_ext_desc_pool", \ 800126db5dbSVivek WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \ 801126db5dbSVivek WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \ 802126db5dbSVivek WLAN_CFG_NUM_TXEXT_DESC_POOL, \ 803126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool") 804126db5dbSVivek 805126db5dbSVivek #define CFG_DP_PDEV_RX_RING \ 806126db5dbSVivek CFG_INI_UINT("dp_pdev_rx_ring", \ 807126db5dbSVivek WLAN_CFG_PER_PDEV_RX_RING_MIN, \ 808126db5dbSVivek WLAN_CFG_PER_PDEV_RX_RING_MAX, \ 809126db5dbSVivek WLAN_CFG_PER_PDEV_RX_RING, \ 810126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring") 811126db5dbSVivek 812126db5dbSVivek #define CFG_DP_PDEV_TX_RING \ 813126db5dbSVivek CFG_INI_UINT("dp_pdev_tx_ring", \ 814126db5dbSVivek WLAN_CFG_PER_PDEV_TX_RING_MIN, \ 815126db5dbSVivek WLAN_CFG_PER_PDEV_TX_RING_MAX, \ 816126db5dbSVivek WLAN_CFG_PER_PDEV_TX_RING, \ 817126db5dbSVivek CFG_VALUE_OR_DEFAULT, \ 818126db5dbSVivek "DP PDEV Tx Ring") 819126db5dbSVivek 820126db5dbSVivek #define CFG_DP_RX_DEFRAG_TIMEOUT \ 821126db5dbSVivek CFG_INI_UINT("dp_rx_defrag_timeout", \ 822126db5dbSVivek WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \ 823126db5dbSVivek WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \ 824126db5dbSVivek WLAN_CFG_RX_DEFRAG_TIMEOUT, \ 825126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout") 826126db5dbSVivek 827126db5dbSVivek #define CFG_DP_TX_COMPL_RING_SIZE \ 828126db5dbSVivek CFG_INI_UINT("dp_tx_compl_ring_size", \ 829126db5dbSVivek WLAN_CFG_TX_COMP_RING_SIZE_MIN, \ 830126db5dbSVivek WLAN_CFG_TX_COMP_RING_SIZE_MAX, \ 831126db5dbSVivek WLAN_CFG_TX_COMP_RING_SIZE, \ 832126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size") 833126db5dbSVivek 834126db5dbSVivek #define CFG_DP_TX_RING_SIZE \ 835126db5dbSVivek CFG_INI_UINT("dp_tx_ring_size", \ 836126db5dbSVivek WLAN_CFG_TX_RING_SIZE_MIN,\ 837126db5dbSVivek WLAN_CFG_TX_RING_SIZE_MAX,\ 838126db5dbSVivek WLAN_CFG_TX_RING_SIZE,\ 839126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size") 840126db5dbSVivek 841126db5dbSVivek #define CFG_DP_NSS_COMP_RING_SIZE \ 842126db5dbSVivek CFG_INI_UINT("dp_nss_comp_ring_size", \ 843126db5dbSVivek WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \ 844126db5dbSVivek WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \ 845126db5dbSVivek WLAN_CFG_NSS_TX_COMP_RING_SIZE, \ 846126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size") 847126db5dbSVivek 848126db5dbSVivek #define CFG_DP_PDEV_LMAC_RING \ 849126db5dbSVivek CFG_INI_UINT("dp_pdev_lmac_ring", \ 850126db5dbSVivek WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \ 851126db5dbSVivek WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \ 852126db5dbSVivek WLAN_CFG_PER_PDEV_LMAC_RING, \ 853126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring") 85473465714SRuben Columbus 85573465714SRuben Columbus #define CFG_DP_TIME_CONTROL_BP \ 85673465714SRuben Columbus CFG_INI_UINT("dp_time_control_bp", \ 85773465714SRuben Columbus WLAN_CFG_TIME_CONTROL_BP_MIN,\ 85873465714SRuben Columbus WLAN_CFG_TIME_CONTROL_BP_MAX,\ 85973465714SRuben Columbus WLAN_CFG_TIME_CONTROL_BP,\ 86073465714SRuben Columbus CFG_VALUE_OR_DEFAULT, "DP time control back pressure") 8613b1f7cedSVivek 86270b5c653SRuben Columbus #define CFG_DP_RX_BUFFER_SIZE \ 86370b5c653SRuben Columbus CFG_INI_UINT("dp_rx_buffer_size", \ 86470b5c653SRuben Columbus WLAN_CFG_RX_BUFFER_SIZE_MIN,\ 86570b5c653SRuben Columbus WLAN_CFG_RX_BUFFER_SIZE_MAX,\ 86670b5c653SRuben Columbus WLAN_CFG_RX_BUFFER_SIZE,\ 86770b5c653SRuben Columbus CFG_VALUE_OR_DEFAULT, "DP rx buffer size") 86870b5c653SRuben Columbus 869d8334769SRuben Columbus #define CFG_DP_QREF_CONTROL_SIZE \ 870d8334769SRuben Columbus CFG_INI_UINT("dp_qref_control_size", \ 871d8334769SRuben Columbus WLAN_CFG_QREF_CONTROL_SIZE_MIN,\ 872d8334769SRuben Columbus WLAN_CFG_QREF_CONTROL_SIZE_MAX,\ 873d8334769SRuben Columbus WLAN_CFG_QREF_CONTROL_SIZE,\ 874d8334769SRuben Columbus CFG_VALUE_OR_DEFAULT, "DP array size for qref debug") 875d8334769SRuben Columbus 8763b1f7cedSVivek #ifdef CONFIG_SAWF_STATS 8773b1f7cedSVivek #define CFG_DP_SAWF_STATS \ 8783b1f7cedSVivek CFG_INI_UINT("dp_sawf_stats", \ 8793b1f7cedSVivek WLAN_CFG_SAWF_STATS_MIN,\ 8803b1f7cedSVivek WLAN_CFG_SAWF_STATS_MAX,\ 8813b1f7cedSVivek WLAN_CFG_SAWF_STATS,\ 8823b1f7cedSVivek CFG_VALUE_OR_DEFAULT, "DP sawf stats config") 8833b1f7cedSVivek #define CFG_DP_SAWF_STATS_CONFIG CFG(CFG_DP_SAWF_STATS) 8843b1f7cedSVivek #else 8853b1f7cedSVivek #define CFG_DP_SAWF_STATS_CONFIG 8863b1f7cedSVivek #endif 8873b1f7cedSVivek 8889de0de3fSSrinivas Girigowda #ifdef WLAN_FEATURE_LOCAL_PKT_CAPTURE 8899de0de3fSSrinivas Girigowda /* 8909de0de3fSSrinivas Girigowda * <ini> 8919de0de3fSSrinivas Girigowda * local_pkt_capture - Enable/Disable Local packet capture 8929de0de3fSSrinivas Girigowda * @Default: false 8939de0de3fSSrinivas Girigowda * 8949de0de3fSSrinivas Girigowda * This ini is used to enable/disable local packet capture. 8959de0de3fSSrinivas Girigowda * 8969de0de3fSSrinivas Girigowda * Related: None 8979de0de3fSSrinivas Girigowda * 8989de0de3fSSrinivas Girigowda * Usage: External 8999de0de3fSSrinivas Girigowda * 9009de0de3fSSrinivas Girigowda * </ini> 9019de0de3fSSrinivas Girigowda */ 9029de0de3fSSrinivas Girigowda #define CFG_DP_LOCAL_PKT_CAPTURE \ 9039de0de3fSSrinivas Girigowda CFG_INI_BOOL( \ 9049de0de3fSSrinivas Girigowda "local_packet_capture", \ 9053c62dfa3SSrinivas Girigowda true, \ 9069de0de3fSSrinivas Girigowda "Local packet capture") 9079de0de3fSSrinivas Girigowda 9089de0de3fSSrinivas Girigowda #define CFG_DP_LOCAL_PKT_CAPTURE_CONFIG CFG(CFG_DP_LOCAL_PKT_CAPTURE) 9099de0de3fSSrinivas Girigowda #else 9109de0de3fSSrinivas Girigowda #define CFG_DP_LOCAL_PKT_CAPTURE_CONFIG 9119de0de3fSSrinivas Girigowda #endif 9129de0de3fSSrinivas Girigowda 913db5374f0SYu Tian /* 914db5374f0SYu Tian * <ini> 915db5374f0SYu Tian * dp_rx_pending_hl_threshold - High threshold of frame number to start 916db5374f0SYu Tian * frame dropping scheme 917db5374f0SYu Tian * @Min: 0 918db5374f0SYu Tian * @Max: 524288 919db5374f0SYu Tian * @Default: 393216 920db5374f0SYu Tian * 921db5374f0SYu Tian * This ini entry is used to set a high limit threshold to start frame 922db5374f0SYu Tian * dropping scheme 923db5374f0SYu Tian * 924db5374f0SYu Tian * Usage: External 925db5374f0SYu Tian * 926db5374f0SYu Tian * </ini> 927db5374f0SYu Tian */ 928db5374f0SYu Tian #define CFG_DP_RX_PENDING_HL_THRESHOLD \ 929db5374f0SYu Tian CFG_INI_UINT("dp_rx_pending_hl_threshold", \ 930db5374f0SYu Tian WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN, \ 931db5374f0SYu Tian WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX, \ 932db5374f0SYu Tian WLAN_CFG_RX_PENDING_HL_THRESHOLD, \ 933db5374f0SYu Tian CFG_VALUE_OR_DEFAULT, "DP rx pending hl threshold") 934db5374f0SYu Tian 935db5374f0SYu Tian /* 936db5374f0SYu Tian * <ini> 937db5374f0SYu Tian * dp_rx_pending_lo_threshold - Low threshold of frame number to stop 938db5374f0SYu Tian * frame dropping scheme 939db5374f0SYu Tian * @Min: 100 940db5374f0SYu Tian * @Max: 524288 941db5374f0SYu Tian * @Default: 393216 942db5374f0SYu Tian * 943db5374f0SYu Tian * This ini entry is used to set a low limit threshold to stop frame 944db5374f0SYu Tian * dropping scheme 945db5374f0SYu Tian * 946db5374f0SYu Tian * Usage: External 947db5374f0SYu Tian * 948db5374f0SYu Tian * </ini> 949db5374f0SYu Tian */ 950db5374f0SYu Tian #define CFG_DP_RX_PENDING_LO_THRESHOLD \ 951db5374f0SYu Tian CFG_INI_UINT("dp_rx_pending_lo_threshold", \ 952db5374f0SYu Tian WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN, \ 953db5374f0SYu Tian WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX, \ 954db5374f0SYu Tian WLAN_CFG_RX_PENDING_LO_THRESHOLD, \ 955db5374f0SYu Tian CFG_VALUE_OR_DEFAULT, "DP rx pending lo threshold") 956126db5dbSVivek 957126db5dbSVivek #define CFG_DP_BASE_HW_MAC_ID \ 958126db5dbSVivek CFG_INI_UINT("dp_base_hw_macid", \ 959126db5dbSVivek 0, 1, 1, \ 960126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID") 961126db5dbSVivek 962126db5dbSVivek #define CFG_DP_RX_HASH \ 963126db5dbSVivek CFG_INI_BOOL("dp_rx_hash", true, \ 964126db5dbSVivek "DP Rx Hash") 965126db5dbSVivek 9663b770cc5SParikshit Gune #define CFG_DP_RX_RR \ 9673b770cc5SParikshit Gune CFG_INI_BOOL("dp_rx_rr", true, \ 9683b770cc5SParikshit Gune "DP Rx Round Robin") 9693b770cc5SParikshit Gune 970126db5dbSVivek #define CFG_DP_TSO \ 971126db5dbSVivek CFG_INI_BOOL("TSOEnable", false, \ 972126db5dbSVivek "DP TSO Enabled") 973126db5dbSVivek 974a4f6e173SAkshay Kosigi #define CFG_DP_LRO \ 975a4f6e173SAkshay Kosigi CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \ 976a4f6e173SAkshay Kosigi "DP LRO Enable") 977a4f6e173SAkshay Kosigi 978e7074b08SSurya Prakash Raajen #ifdef WLAN_USE_CONFIG_PARAMS 979e7074b08SSurya Prakash Raajen /* 980e7074b08SSurya Prakash Raajen * <ini> 981e7074b08SSurya Prakash Raajen * dp_tx_desc_use_512p - Use 512M tx descriptor size 982e7074b08SSurya Prakash Raajen * @Min: 0 983e7074b08SSurya Prakash Raajen * @Max: 1 984e7074b08SSurya Prakash Raajen * @Default: 0 985e7074b08SSurya Prakash Raajen * 986e7074b08SSurya Prakash Raajen * This ini entry is used as flag to use 512M tx descriptor size or not 987e7074b08SSurya Prakash Raajen * 988e7074b08SSurya Prakash Raajen * Usage: Internal 989e7074b08SSurya Prakash Raajen * 990e7074b08SSurya Prakash Raajen * </ini> 991e7074b08SSurya Prakash Raajen */ 992e7074b08SSurya Prakash Raajen #define CFG_DP_TX_DESC_512P \ 993e7074b08SSurya Prakash Raajen CFG_INI_BOOL("dp_tx_desc_use_512p", false, \ 994e7074b08SSurya Prakash Raajen "DP TX DESC PINE SPECIFIC") 995e7074b08SSurya Prakash Raajen 996e7074b08SSurya Prakash Raajen /* 997e7074b08SSurya Prakash Raajen * <ini> 998e7074b08SSurya Prakash Raajen * dp_nss_3radio_ring - Use 3 Radio NSS comp ring size 999e7074b08SSurya Prakash Raajen * @Min: 0 1000e7074b08SSurya Prakash Raajen * @Max: 1 1001e7074b08SSurya Prakash Raajen * @Default: 0 1002e7074b08SSurya Prakash Raajen * 1003e7074b08SSurya Prakash Raajen * This ini entry is used as flag to use 3 Radio NSS com ring size or not 1004e7074b08SSurya Prakash Raajen * 1005e7074b08SSurya Prakash Raajen * Usage: Internal 1006e7074b08SSurya Prakash Raajen * 1007e7074b08SSurya Prakash Raajen * </ini> 1008e7074b08SSurya Prakash Raajen */ 1009e7074b08SSurya Prakash Raajen #define CFG_DP_NSS_3RADIO_RING \ 1010e7074b08SSurya Prakash Raajen CFG_INI_BOOL("dp_nss_3radio_ring", false, \ 1011e7074b08SSurya Prakash Raajen "DP NSS 3 RADIO RING SIZE") 1012e7074b08SSurya Prakash Raajen 1013e7074b08SSurya Prakash Raajen /* 1014e7074b08SSurya Prakash Raajen * <ini> 1015e7074b08SSurya Prakash Raajen * dp_mon_ring_per_512M - Update monitor status ring as 512M profile 1016e7074b08SSurya Prakash Raajen * @Min: 0 1017e7074b08SSurya Prakash Raajen * @Max: 1 1018e7074b08SSurya Prakash Raajen * @Default: 0 1019e7074b08SSurya Prakash Raajen * 1020e7074b08SSurya Prakash Raajen * This ini entry is used as flag to update monitor status ring as 512M profile 1021e7074b08SSurya Prakash Raajen * 1022e7074b08SSurya Prakash Raajen * Usage: Internal 1023e7074b08SSurya Prakash Raajen * 1024e7074b08SSurya Prakash Raajen * </ini> 1025e7074b08SSurya Prakash Raajen */ 1026e7074b08SSurya Prakash Raajen #define CFG_DP_MON_STATUS_512M \ 1027e7074b08SSurya Prakash Raajen CFG_INI_BOOL("dp_mon_ring_per_512M", false, \ 1028e7074b08SSurya Prakash Raajen "DP MON STATUS RING SIZE PER 512M PROFILE") 1029e7074b08SSurya Prakash Raajen 1030e7074b08SSurya Prakash Raajen /* 1031e7074b08SSurya Prakash Raajen * <ini> 1032e7074b08SSurya Prakash Raajen * dp_mon_2chain_ring - Reduce monitor rings size as for 2 Chains case 1033e7074b08SSurya Prakash Raajen * @Min: 0 1034e7074b08SSurya Prakash Raajen * @Max: 1 1035e7074b08SSurya Prakash Raajen * @Default: 0 1036e7074b08SSurya Prakash Raajen * 1037e7074b08SSurya Prakash Raajen * This ini entry is used as flag to reduce monitor rings size as those used 1038e7074b08SSurya Prakash Raajen * in case of 2 Tx/RxChains 1039e7074b08SSurya Prakash Raajen * 1040e7074b08SSurya Prakash Raajen * Usage: Internal 1041e7074b08SSurya Prakash Raajen * 1042e7074b08SSurya Prakash Raajen * </ini> 1043e7074b08SSurya Prakash Raajen */ 1044e7074b08SSurya Prakash Raajen #define CFG_DP_MON_2CHAIN_RING \ 1045e7074b08SSurya Prakash Raajen CFG_INI_BOOL("dp_mon_2chain_ring", false, \ 1046e7074b08SSurya Prakash Raajen "DP MON UPDATE RINGS FOR 2CHAIN") 1047e7074b08SSurya Prakash Raajen 1048e7074b08SSurya Prakash Raajen /* 1049e7074b08SSurya Prakash Raajen * <ini> 1050e7074b08SSurya Prakash Raajen * dp_mon_4chain_ring - Update monitor rings size for 4 Chains case 1051e7074b08SSurya Prakash Raajen * @Min: 0 1052e7074b08SSurya Prakash Raajen * @Max: 1 1053e7074b08SSurya Prakash Raajen * @Default: 0 1054e7074b08SSurya Prakash Raajen * 1055e7074b08SSurya Prakash Raajen * This ini entry is used as flag to reduce monitor rings size as those used 1056e7074b08SSurya Prakash Raajen * in case of 4 Tx/RxChains 1057e7074b08SSurya Prakash Raajen * 1058e7074b08SSurya Prakash Raajen * Usage: Internal 1059e7074b08SSurya Prakash Raajen * 1060e7074b08SSurya Prakash Raajen * </ini> 1061e7074b08SSurya Prakash Raajen */ 1062e7074b08SSurya Prakash Raajen #define CFG_DP_MON_4CHAIN_RING \ 1063e7074b08SSurya Prakash Raajen CFG_INI_BOOL("dp_mon_4chain_ring", false, \ 1064e7074b08SSurya Prakash Raajen "DP MON UPDATE RINGS FOR 4CHAIN") 1065e7074b08SSurya Prakash Raajen 1066e7074b08SSurya Prakash Raajen /* 1067e7074b08SSurya Prakash Raajen * <ini> 1068e7074b08SSurya Prakash Raajen * dp_4radip_rdp_reo - Update RDP REO map based on 4 radio config 1069e7074b08SSurya Prakash Raajen * @Min: 0 1070e7074b08SSurya Prakash Raajen * @Max: 1 1071e7074b08SSurya Prakash Raajen * @Default: 0 1072e7074b08SSurya Prakash Raajen * 1073e7074b08SSurya Prakash Raajen * This ini entry is used as flag to update RDP reo map based on 4 Radio config 1074e7074b08SSurya Prakash Raajen * 1075e7074b08SSurya Prakash Raajen * Usage: Internal 1076e7074b08SSurya Prakash Raajen * 1077e7074b08SSurya Prakash Raajen * </ini> 1078e7074b08SSurya Prakash Raajen */ 1079e7074b08SSurya Prakash Raajen #define CFG_DP_4RADIO_RDP_REO \ 1080e7074b08SSurya Prakash Raajen CFG_INI_BOOL("dp_nss_4radio_rdp_reo", \ 1081e7074b08SSurya Prakash Raajen false, "Update REO destination mapping for 4radio") 1082e7074b08SSurya Prakash Raajen 1083e7074b08SSurya Prakash Raajen #define CFG_DP_INI_SECTION_PARAMS \ 1084e7074b08SSurya Prakash Raajen CFG(CFG_DP_NSS_3RADIO_RING) \ 1085e7074b08SSurya Prakash Raajen CFG(CFG_DP_TX_DESC_512P) \ 1086e7074b08SSurya Prakash Raajen CFG(CFG_DP_MON_STATUS_512M) \ 1087e7074b08SSurya Prakash Raajen CFG(CFG_DP_MON_2CHAIN_RING) \ 1088e7074b08SSurya Prakash Raajen CFG(CFG_DP_MON_4CHAIN_RING) \ 1089e7074b08SSurya Prakash Raajen CFG(CFG_DP_4RADIO_RDP_REO) 1090e7074b08SSurya Prakash Raajen #else 1091e7074b08SSurya Prakash Raajen #define CFG_DP_INI_SECTION_PARAMS 1092e7074b08SSurya Prakash Raajen #endif 1093e7074b08SSurya Prakash Raajen 10949fc47f76STiger Yu /* 10959fc47f76STiger Yu * <ini> 10969fc47f76STiger Yu * CFG_DP_SG - Enable the SG feature standalonely 10979fc47f76STiger Yu * @Min: 0 10989fc47f76STiger Yu * @Max: 1 10999fc47f76STiger Yu * @Default: 1 11009fc47f76STiger Yu * 11019fc47f76STiger Yu * This ini entry is used to enable/disable SG feature standalonely. 11029fc47f76STiger Yu * Also does Rome support SG on TX, lithium does not. 11039fc47f76STiger Yu * For example the lithium does not support SG on UDP frames. 11049fc47f76STiger Yu * Which is able to handle SG only for TSO frames(in case TSO is enabled). 11059fc47f76STiger Yu * 11069fc47f76STiger Yu * Usage: External 11079fc47f76STiger Yu * 11089fc47f76STiger Yu * </ini> 11099fc47f76STiger Yu */ 1110a4f6e173SAkshay Kosigi #define CFG_DP_SG \ 1111a4f6e173SAkshay Kosigi CFG_INI_BOOL("dp_sg_support", false, \ 1112a4f6e173SAkshay Kosigi "DP SG Enable") 1113a4f6e173SAkshay Kosigi 1114ac211076SYu Tian #define WLAN_CFG_GRO_ENABLE_MIN 0 1115ac211076SYu Tian #define WLAN_CFG_GRO_ENABLE_MAX 3 1116ac211076SYu Tian #define WLAN_CFG_GRO_ENABLE_DEFAULT 0 1117ac211076SYu Tian #define DP_GRO_ENABLE_BIT_SET BIT(0) 1118f2ee56b2SYeshwanth Sriram Guntuka #define DP_TC_BASED_DYNAMIC_GRO BIT(1) 1119f2ee56b2SYeshwanth Sriram Guntuka 1120ac211076SYu Tian /* 1121ac211076SYu Tian * <ini> 1122ac211076SYu Tian * CFG_DP_GRO - Enable the GRO feature standalonely 1123ac211076SYu Tian * @Min: 0 1124ac211076SYu Tian * @Max: 3 1125ac211076SYu Tian * @Default: 0 1126ac211076SYu Tian * 1127ac211076SYu Tian * This ini entry is used to enable/disable GRO feature standalonely. 1128ac211076SYu Tian * Value 0: Disable GRO feature 1129f2ee56b2SYeshwanth Sriram Guntuka * Value 1: Enable GRO feature always 1130f2ee56b2SYeshwanth Sriram Guntuka * Value 3: Enable GRO dynamic feature where TC rule can control GRO 1131f2ee56b2SYeshwanth Sriram Guntuka * behavior 1132ac211076SYu Tian * 1133ac211076SYu Tian * Usage: External 1134ac211076SYu Tian * 1135ac211076SYu Tian * </ini> 1136ac211076SYu Tian */ 1137a4f6e173SAkshay Kosigi #define CFG_DP_GRO \ 1138ac211076SYu Tian CFG_INI_UINT("GROEnable", \ 1139ac211076SYu Tian WLAN_CFG_GRO_ENABLE_MIN, \ 1140ac211076SYu Tian WLAN_CFG_GRO_ENABLE_MAX, \ 1141ac211076SYu Tian WLAN_CFG_GRO_ENABLE_DEFAULT, \ 1142ac211076SYu Tian CFG_VALUE_OR_DEFAULT, "DP GRO Enable") 1143a4f6e173SAkshay Kosigi 1144f2ee56b2SYeshwanth Sriram Guntuka #define WLAN_CFG_TC_INGRESS_PRIO_MIN 0 1145f2ee56b2SYeshwanth Sriram Guntuka #define WLAN_CFG_TC_INGRESS_PRIO_MAX 0xFFFF 1146f2ee56b2SYeshwanth Sriram Guntuka #define WLAN_CFG_TC_INGRESS_PRIO_DEFAULT 0 1147f2ee56b2SYeshwanth Sriram Guntuka 1148f2ee56b2SYeshwanth Sriram Guntuka #define CFG_DP_TC_INGRESS_PRIO \ 1149f2ee56b2SYeshwanth Sriram Guntuka CFG_INI_UINT("tc_ingress_prio", \ 1150f2ee56b2SYeshwanth Sriram Guntuka WLAN_CFG_TC_INGRESS_PRIO_MIN, \ 1151f2ee56b2SYeshwanth Sriram Guntuka WLAN_CFG_TC_INGRESS_PRIO_MAX, \ 1152f2ee56b2SYeshwanth Sriram Guntuka WLAN_CFG_TC_INGRESS_PRIO_DEFAULT, \ 1153f2ee56b2SYeshwanth Sriram Guntuka CFG_VALUE_OR_DEFAULT, "DP tc ingress prio") 1154f2ee56b2SYeshwanth Sriram Guntuka 1155a4f6e173SAkshay Kosigi #define CFG_DP_OL_TX_CSUM \ 1156a4f6e173SAkshay Kosigi CFG_INI_BOOL("dp_offload_tx_csum_support", false, \ 1157a4f6e173SAkshay Kosigi "DP tx csum Enable") 1158a4f6e173SAkshay Kosigi 1159a4f6e173SAkshay Kosigi #define CFG_DP_OL_RX_CSUM \ 1160a4f6e173SAkshay Kosigi CFG_INI_BOOL("dp_offload_rx_csum_support", false, \ 1161a4f6e173SAkshay Kosigi "DP rx csum Enable") 1162a4f6e173SAkshay Kosigi 1163a4f6e173SAkshay Kosigi #define CFG_DP_RAWMODE \ 1164a4f6e173SAkshay Kosigi CFG_INI_BOOL("dp_rawmode_support", false, \ 1165a4f6e173SAkshay Kosigi "DP rawmode Enable") 1166a4f6e173SAkshay Kosigi 1167a4f6e173SAkshay Kosigi #define CFG_DP_PEER_FLOW_CTRL \ 1168a4f6e173SAkshay Kosigi CFG_INI_BOOL("dp_peer_flow_control_support", false, \ 1169a4f6e173SAkshay Kosigi "DP peer flow ctrl Enable") 1170a4f6e173SAkshay Kosigi 1171126db5dbSVivek #define CFG_DP_NAPI \ 11727047d0d1SVivek CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \ 1173126db5dbSVivek "DP Napi Enabled") 117442a8d7efSMohit Khanna /* 117542a8d7efSMohit Khanna * <ini> 117642a8d7efSMohit Khanna * gEnableP2pIpTcpUdpChecksumOffload - Enable checksum offload for P2P mode 117742a8d7efSMohit Khanna * @Min: 0 117842a8d7efSMohit Khanna * @Max: 1 117942a8d7efSMohit Khanna * @Default: 1 118042a8d7efSMohit Khanna * 118142a8d7efSMohit Khanna * This ini entry is used to enable/disable TX checksum(UDP/TCP) for P2P modes. 118242a8d7efSMohit Khanna * This includes P2P device mode, P2P client mode and P2P GO mode. 118342a8d7efSMohit Khanna * The feature is enabled by default. To disable TX checksum for P2P, add the 118442a8d7efSMohit Khanna * following entry in ini file: 118542a8d7efSMohit Khanna * gEnableP2pIpTcpUdpChecksumOffload=0 118642a8d7efSMohit Khanna * 118742a8d7efSMohit Khanna * Usage: External 118842a8d7efSMohit Khanna * 118942a8d7efSMohit Khanna * </ini> 119042a8d7efSMohit Khanna */ 119142a8d7efSMohit Khanna #define CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD \ 119242a8d7efSMohit Khanna CFG_INI_BOOL("gEnableP2pIpTcpUdpChecksumOffload", true, \ 119342a8d7efSMohit Khanna "DP TCP UDP Checksum Offload for P2P mode (device/cli/go)") 1194126db5dbSVivek 119597200aabSMohit Khanna /* 119697200aabSMohit Khanna * <ini> 119797200aabSMohit Khanna * gEnableNanIpTcpUdpChecksumOffload - Enable checksum offload for NAN mode 119897200aabSMohit Khanna * @Min: 0 119997200aabSMohit Khanna * @Max: 1 120097200aabSMohit Khanna * @Default: 1 120197200aabSMohit Khanna * 120297200aabSMohit Khanna * Usage: External 120397200aabSMohit Khanna * 120497200aabSMohit Khanna * </ini> 120597200aabSMohit Khanna */ 120697200aabSMohit Khanna #define CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD \ 120797200aabSMohit Khanna CFG_INI_BOOL("gEnableNanIpTcpUdpChecksumOffload", true, \ 120897200aabSMohit Khanna "DP TCP UDP Checksum Offload for NAN mode") 120997200aabSMohit Khanna 121097200aabSMohit Khanna /* 121197200aabSMohit Khanna * <ini> 121297200aabSMohit Khanna * gEnableIpTcpUdpChecksumOffload - Enable checksum offload 121397200aabSMohit Khanna * @Min: 0 121497200aabSMohit Khanna * @Max: 1 121597200aabSMohit Khanna * @Default: 1 121697200aabSMohit Khanna * 121797200aabSMohit Khanna * Usage: External 121897200aabSMohit Khanna * 121997200aabSMohit Khanna * </ini> 122097200aabSMohit Khanna */ 1221126db5dbSVivek #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \ 122260ac9aa0Sjitiphil CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \ 1223126db5dbSVivek "DP TCP UDP Checksum Offload") 1224126db5dbSVivek 1225126db5dbSVivek #define CFG_DP_DEFRAG_TIMEOUT_CHECK \ 1226126db5dbSVivek CFG_INI_BOOL("dp_defrag_timeout_check", true, \ 1227126db5dbSVivek "DP Defrag Timeout Check") 1228126db5dbSVivek 1229126db5dbSVivek #define CFG_DP_WBM_RELEASE_RING \ 1230126db5dbSVivek CFG_INI_UINT("dp_wbm_release_ring", \ 1231126db5dbSVivek WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \ 1232126db5dbSVivek WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \ 1233126db5dbSVivek WLAN_CFG_WBM_RELEASE_RING_SIZE, \ 1234126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring") 1235126db5dbSVivek 1236f63aaef3SAnkit Kumar #define CFG_DP_TCL_CMD_CREDIT_RING \ 1237f63aaef3SAnkit Kumar CFG_INI_UINT("dp_tcl_cmd_credit_ring", \ 1238f63aaef3SAnkit Kumar WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN, \ 1239f63aaef3SAnkit Kumar WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX, \ 1240f63aaef3SAnkit Kumar WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE, \ 1241f63aaef3SAnkit Kumar CFG_VALUE_OR_DEFAULT, "DP TCL Cmd_Credit ring") 1242126db5dbSVivek 1243126db5dbSVivek #define CFG_DP_TCL_STATUS_RING \ 1244126db5dbSVivek CFG_INI_UINT("dp_tcl_status_ring",\ 1245126db5dbSVivek WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \ 1246126db5dbSVivek WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \ 1247126db5dbSVivek WLAN_CFG_TCL_STATUS_RING_SIZE, \ 1248126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP TCL status ring") 1249126db5dbSVivek 1250126db5dbSVivek #define CFG_DP_REO_REINJECT_RING \ 1251126db5dbSVivek CFG_INI_UINT("dp_reo_reinject_ring", \ 1252126db5dbSVivek WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \ 1253126db5dbSVivek WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \ 1254126db5dbSVivek WLAN_CFG_REO_REINJECT_RING_SIZE, \ 1255126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP REO reinject ring") 1256126db5dbSVivek 1257126db5dbSVivek #define CFG_DP_RX_RELEASE_RING \ 1258126db5dbSVivek CFG_INI_UINT("dp_rx_release_ring", \ 1259126db5dbSVivek WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \ 1260126db5dbSVivek WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \ 1261126db5dbSVivek WLAN_CFG_RX_RELEASE_RING_SIZE, \ 1262126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP Rx release ring") 1263126db5dbSVivek 12644fa2c22cSChaithanya Garrepalli #define CFG_DP_RX_DESTINATION_RING \ 12654fa2c22cSChaithanya Garrepalli CFG_INI_UINT("dp_reo_dst_ring", \ 12664fa2c22cSChaithanya Garrepalli WLAN_CFG_REO_DST_RING_SIZE_MIN, \ 12674fa2c22cSChaithanya Garrepalli WLAN_CFG_REO_DST_RING_SIZE_MAX, \ 12684fa2c22cSChaithanya Garrepalli WLAN_CFG_REO_DST_RING_SIZE, \ 12694fa2c22cSChaithanya Garrepalli CFG_VALUE_OR_DEFAULT, "DP REO destination ring") 12704fa2c22cSChaithanya Garrepalli 1271126db5dbSVivek #define CFG_DP_REO_EXCEPTION_RING \ 1272126db5dbSVivek CFG_INI_UINT("dp_reo_exception_ring", \ 1273126db5dbSVivek WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \ 1274126db5dbSVivek WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \ 1275126db5dbSVivek WLAN_CFG_REO_EXCEPTION_RING_SIZE, \ 1276126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP REO exception ring") 1277126db5dbSVivek 1278126db5dbSVivek #define CFG_DP_REO_CMD_RING \ 1279126db5dbSVivek CFG_INI_UINT("dp_reo_cmd_ring", \ 1280126db5dbSVivek WLAN_CFG_REO_CMD_RING_SIZE_MIN, \ 1281126db5dbSVivek WLAN_CFG_REO_CMD_RING_SIZE_MAX, \ 1282126db5dbSVivek WLAN_CFG_REO_CMD_RING_SIZE, \ 1283126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP REO command ring") 1284126db5dbSVivek 1285126db5dbSVivek #define CFG_DP_REO_STATUS_RING \ 1286126db5dbSVivek CFG_INI_UINT("dp_reo_status_ring", \ 1287126db5dbSVivek WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \ 1288126db5dbSVivek WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \ 1289126db5dbSVivek WLAN_CFG_REO_STATUS_RING_SIZE, \ 1290126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP REO status ring") 1291126db5dbSVivek 1292126db5dbSVivek #define CFG_DP_RXDMA_BUF_RING \ 1293126db5dbSVivek CFG_INI_UINT("dp_rxdma_buf_ring", \ 1294126db5dbSVivek WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \ 1295126db5dbSVivek WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \ 1296126db5dbSVivek WLAN_CFG_RXDMA_BUF_RING_SIZE, \ 1297126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring") 1298126db5dbSVivek 1299126db5dbSVivek #define CFG_DP_RXDMA_REFILL_RING \ 1300126db5dbSVivek CFG_INI_UINT("dp_rxdma_refill_ring", \ 1301126db5dbSVivek WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \ 1302126db5dbSVivek WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \ 1303126db5dbSVivek WLAN_CFG_RXDMA_REFILL_RING_SIZE, \ 1304126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring") 1305126db5dbSVivek 130664c4cb35SChaithanya Garrepalli #define CFG_DP_RXDMA_REFILL_LT_DISABLE \ 130764c4cb35SChaithanya Garrepalli CFG_INI_BOOL("dp_disable_rx_buf_low_threshold", false, \ 130864c4cb35SChaithanya Garrepalli "Disable Low threshold interrupts for Rx Refill ring") 130964c4cb35SChaithanya Garrepalli 131036ce817bSPrathyusha Guduri #define CFG_DP_TX_DESC_LIMIT_0 \ 131136ce817bSPrathyusha Guduri CFG_INI_UINT("dp_tx_desc_limit_0", \ 131236ce817bSPrathyusha Guduri WLAN_CFG_TX_DESC_LIMIT_0_MIN, \ 131336ce817bSPrathyusha Guduri WLAN_CFG_TX_DESC_LIMIT_0_MAX, \ 131436ce817bSPrathyusha Guduri WLAN_CFG_TX_DESC_LIMIT_0, \ 131536ce817bSPrathyusha Guduri CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0") 131636ce817bSPrathyusha Guduri 131736ce817bSPrathyusha Guduri #define CFG_DP_TX_DESC_LIMIT_1 \ 131836ce817bSPrathyusha Guduri CFG_INI_UINT("dp_tx_desc_limit_1", \ 131936ce817bSPrathyusha Guduri WLAN_CFG_TX_DESC_LIMIT_1_MIN, \ 132036ce817bSPrathyusha Guduri WLAN_CFG_TX_DESC_LIMIT_1_MAX, \ 132136ce817bSPrathyusha Guduri WLAN_CFG_TX_DESC_LIMIT_1, \ 132236ce817bSPrathyusha Guduri CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1") 132336ce817bSPrathyusha Guduri 132436ce817bSPrathyusha Guduri #define CFG_DP_TX_DESC_LIMIT_2 \ 132536ce817bSPrathyusha Guduri CFG_INI_UINT("dp_tx_desc_limit_2", \ 132636ce817bSPrathyusha Guduri WLAN_CFG_TX_DESC_LIMIT_2_MIN, \ 132736ce817bSPrathyusha Guduri WLAN_CFG_TX_DESC_LIMIT_2_MAX, \ 132836ce817bSPrathyusha Guduri WLAN_CFG_TX_DESC_LIMIT_2, \ 132936ce817bSPrathyusha Guduri CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2") 133036ce817bSPrathyusha Guduri 1331aed67e19SPrathyusha Guduri #define CFG_DP_TX_DEVICE_LIMIT \ 1332aed67e19SPrathyusha Guduri CFG_INI_UINT("dp_tx_device_limit", \ 1333aed67e19SPrathyusha Guduri WLAN_CFG_TX_DEVICE_LIMIT_MIN, \ 1334aed67e19SPrathyusha Guduri WLAN_CFG_TX_DEVICE_LIMIT_MAX, \ 1335aed67e19SPrathyusha Guduri WLAN_CFG_TX_DEVICE_LIMIT, \ 1336aed67e19SPrathyusha Guduri CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit") 1337aed67e19SPrathyusha Guduri 13386eba2a44SSreeramya Soratkal #define CFG_DP_TX_SPL_DEVICE_LIMIT \ 13396eba2a44SSreeramya Soratkal CFG_INI_UINT("dp_tx_spl_device_limit", \ 13406eba2a44SSreeramya Soratkal WLAN_CFG_TX_SPL_DEVICE_LIMIT_MIN, \ 13416eba2a44SSreeramya Soratkal WLAN_CFG_TX_SPL_DEVICE_LIMIT_MAX, \ 13426eba2a44SSreeramya Soratkal WLAN_CFG_TX_SPL_DEVICE_LIMIT, \ 13436eba2a44SSreeramya Soratkal CFG_VALUE_OR_DEFAULT, "DP TX Special DEVICE limit") 13446eba2a44SSreeramya Soratkal 1345abac9eedSPrathyusha Guduri #define CFG_DP_TX_SW_INTERNODE_QUEUE \ 1346abac9eedSPrathyusha Guduri CFG_INI_UINT("dp_tx_sw_internode_queue", \ 1347abac9eedSPrathyusha Guduri WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \ 1348abac9eedSPrathyusha Guduri WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \ 1349abac9eedSPrathyusha Guduri WLAN_CFG_TX_SW_INTERNODE_QUEUE, \ 1350abac9eedSPrathyusha Guduri CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue") 1351abac9eedSPrathyusha Guduri 135230bc8285SNeha Bisht #define CFG_DP_TX_DESC_GLOBAL_COUNT \ 135330bc8285SNeha Bisht CFG_INI_UINT("dp_tx_desc_global", \ 135430bc8285SNeha Bisht WLAN_CFG_TX_DESC_GLOBAL_COUNT_MIN, \ 135530bc8285SNeha Bisht WLAN_CFG_TX_DESC_GLOBAL_COUNT_MAX, \ 135630bc8285SNeha Bisht WLAN_CFG_TX_DESC_GLOBAL_COUNT, \ 135730bc8285SNeha Bisht CFG_VALUE_OR_DEFAULT, "DP Global TX descriptor count") 135830bc8285SNeha Bisht 135930bc8285SNeha Bisht #define CFG_DP_SPCL_TX_DESC_GLOBAL_COUNT \ 136030bc8285SNeha Bisht CFG_INI_UINT("dp_spcl_tx_desc_global", \ 136130bc8285SNeha Bisht WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT_MIN, \ 136230bc8285SNeha Bisht WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT_MAX, \ 136330bc8285SNeha Bisht WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT, \ 136430bc8285SNeha Bisht CFG_VALUE_OR_DEFAULT, "DP Global special TX descriptor count") 136530bc8285SNeha Bisht 1366126db5dbSVivek #define CFG_DP_RXDMA_MONITOR_BUF_RING \ 1367126db5dbSVivek CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \ 1368126db5dbSVivek WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \ 1369126db5dbSVivek WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \ 1370126db5dbSVivek WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \ 1371126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring") 1372126db5dbSVivek 1373df329ebbSNaga #define CFG_DP_TX_MONITOR_BUF_RING \ 1374df329ebbSNaga CFG_INI_UINT("dp_tx_monitor_buf_ring", \ 1375df329ebbSNaga WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN, \ 1376df329ebbSNaga WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX, \ 1377df329ebbSNaga WLAN_CFG_TX_MONITOR_BUF_RING_SIZE, \ 1378df329ebbSNaga CFG_VALUE_OR_DEFAULT, "DP TX monitor buffer ring") 1379df329ebbSNaga 1380126db5dbSVivek #define CFG_DP_RXDMA_MONITOR_DST_RING \ 1381126db5dbSVivek CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \ 1382126db5dbSVivek WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \ 1383126db5dbSVivek WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \ 1384126db5dbSVivek WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \ 1385126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 1386126db5dbSVivek 1387df329ebbSNaga #define CFG_DP_TX_MONITOR_DST_RING \ 1388df329ebbSNaga CFG_INI_UINT("dp_tx_monitor_dst_ring", \ 1389df329ebbSNaga WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN, \ 1390df329ebbSNaga WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX, \ 1391df329ebbSNaga WLAN_CFG_TX_MONITOR_DST_RING_SIZE, \ 1392df329ebbSNaga CFG_VALUE_OR_DEFAULT, "DP TX monitor destination ring") 1393df329ebbSNaga 1394126db5dbSVivek #define CFG_DP_RXDMA_MONITOR_STATUS_RING \ 1395126db5dbSVivek CFG_INI_UINT("dp_rxdma_monitor_status_ring", \ 1396126db5dbSVivek WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \ 1397126db5dbSVivek WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \ 1398126db5dbSVivek WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \ 1399126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring") 1400126db5dbSVivek 1401126db5dbSVivek #define CFG_DP_RXDMA_MONITOR_DESC_RING \ 1402126db5dbSVivek CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \ 1403126db5dbSVivek WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \ 1404126db5dbSVivek WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \ 1405126db5dbSVivek WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \ 1406126db5dbSVivek CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 1407126db5dbSVivek 1408748fe0b6SVenkateswara Naralasetty #define CFG_DP_SW2RXDMA_LINK_RING \ 1409748fe0b6SVenkateswara Naralasetty CFG_INI_UINT("dp_sw2rxdma_link_ring", \ 1410748fe0b6SVenkateswara Naralasetty WLAN_CFG_SW2RXDMA_LINK_RING_SIZE_MIN, \ 1411748fe0b6SVenkateswara Naralasetty WLAN_CFG_SW2RXDMA_LINK_RING_SIZE_MAX, \ 1412748fe0b6SVenkateswara Naralasetty WLAN_CFG_SW2RXDMA_LINK_RING_SIZE, \ 1413748fe0b6SVenkateswara Naralasetty CFG_VALUE_OR_DEFAULT, "DP SW2RXDMA link ring") 1414748fe0b6SVenkateswara Naralasetty 1415126db5dbSVivek #define CFG_DP_RXDMA_ERR_DST_RING \ 1416126db5dbSVivek CFG_INI_UINT("dp_rxdma_err_dst_ring", \ 1417126db5dbSVivek WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \ 1418126db5dbSVivek WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \ 1419126db5dbSVivek WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \ 1420126db5dbSVivek CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring") 1421126db5dbSVivek 142203ba0f55SKrunal Soni #define CFG_DP_PER_PKT_LOGGING \ 142303ba0f55SKrunal Soni CFG_INI_UINT("enable_verbose_debug", \ 142403ba0f55SKrunal Soni 0, 0xffff, 0, \ 142503ba0f55SKrunal Soni CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging") 142603ba0f55SKrunal Soni 142760ac9aa0Sjitiphil #define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \ 142860ac9aa0Sjitiphil CFG_INI_UINT("TxFlowStartQueueOffset", \ 142960ac9aa0Sjitiphil 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \ 143060ac9aa0Sjitiphil CFG_VALUE_OR_DEFAULT, "Start queue offset") 143160ac9aa0Sjitiphil 143260ac9aa0Sjitiphil #define CFG_DP_TX_FLOW_STOP_QUEUE_TH \ 143360ac9aa0Sjitiphil CFG_INI_UINT("TxFlowStopQueueThreshold", \ 143460ac9aa0Sjitiphil 0, 50, 15, \ 143560ac9aa0Sjitiphil CFG_VALUE_OR_DEFAULT, "Stop queue Threshold") 143660ac9aa0Sjitiphil 143760ac9aa0Sjitiphil #define CFG_DP_IPA_UC_TX_BUF_SIZE \ 143860ac9aa0Sjitiphil CFG_INI_UINT("IpaUcTxBufSize", \ 143960ac9aa0Sjitiphil 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \ 144060ac9aa0Sjitiphil CFG_VALUE_OR_DEFAULT, "IPA tx buffer size") 144160ac9aa0Sjitiphil 144260ac9aa0Sjitiphil #define CFG_DP_IPA_UC_TX_PARTITION_BASE \ 144360ac9aa0Sjitiphil CFG_INI_UINT("IpaUcTxPartitionBase", \ 144460ac9aa0Sjitiphil 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \ 144560ac9aa0Sjitiphil CFG_VALUE_OR_DEFAULT, "IPA tx partition base") 144660ac9aa0Sjitiphil 144760ac9aa0Sjitiphil #define CFG_DP_IPA_UC_RX_IND_RING_COUNT \ 144860ac9aa0Sjitiphil CFG_INI_UINT("IpaUcRxIndRingCount", \ 144960ac9aa0Sjitiphil 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \ 145060ac9aa0Sjitiphil CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count") 145160ac9aa0Sjitiphil 145260ac9aa0Sjitiphil #define CFG_DP_AP_STA_SECURITY_SEPERATION \ 145360ac9aa0Sjitiphil CFG_INI_BOOL("gDisableIntraBssFwd", \ 145460ac9aa0Sjitiphil false, "Disable intrs BSS Rx packets") 145560ac9aa0Sjitiphil 145660ac9aa0Sjitiphil #define CFG_DP_ENABLE_DATA_STALL_DETECTION \ 1457bf41ccebSAnanya Gupta CFG_INI_UINT("gEnableDataStallDetection", \ 1458bf41ccebSAnanya Gupta 0, 0xFFFFFFFF, 0x1, \ 1459bf41ccebSAnanya Gupta CFG_VALUE_OR_DEFAULT, "Enable/Disable Data stall detection") 146060ac9aa0Sjitiphil 14619550273eSMainak Sen #define CFG_DP_RX_SW_DESC_WEIGHT \ 14629550273eSMainak Sen CFG_INI_UINT("dp_rx_sw_desc_weight", \ 14639550273eSMainak Sen WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN, \ 14649550273eSMainak Sen WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX, \ 14659550273eSMainak Sen WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE, \ 14669550273eSMainak Sen CFG_VALUE_OR_DEFAULT, "DP RX SW DESC weight") 14679550273eSMainak Sen 1468eeaa5b74SMainak Sen #define CFG_DP_RX_SW_DESC_NUM \ 1469eeaa5b74SMainak Sen CFG_INI_UINT("dp_rx_sw_desc_num", \ 1470eeaa5b74SMainak Sen WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN, \ 1471eeaa5b74SMainak Sen WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX, \ 1472eeaa5b74SMainak Sen WLAN_CFG_RX_SW_DESC_NUM_SIZE, \ 1473eeaa5b74SMainak Sen CFG_VALUE_OR_DEFAULT, "DP RX SW DESC num") 1474eeaa5b74SMainak Sen 147576aa8d51SSumeet Rao #define CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE \ 147676aa8d51SSumeet Rao CFG_INI_UINT("dp_rx_flow_search_table_size", \ 147776aa8d51SSumeet Rao WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN, \ 147876aa8d51SSumeet Rao WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX, \ 14791370e032SAlan Chen WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT, \ 148076aa8d51SSumeet Rao CFG_VALUE_OR_DEFAULT, \ 148176aa8d51SSumeet Rao "DP Rx Flow Search Table Size in number of entries") 148276aa8d51SSumeet Rao 148376aa8d51SSumeet Rao #define CFG_DP_RX_FLOW_TAG_ENABLE \ 148476aa8d51SSumeet Rao CFG_INI_BOOL("dp_rx_flow_tag_enable", false, \ 148576aa8d51SSumeet Rao "Enable/Disable DP Rx Flow Tag") 148676aa8d51SSumeet Rao 148776aa8d51SSumeet Rao #define CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV \ 148876aa8d51SSumeet Rao CFG_INI_BOOL("dp_rx_per_pdev_flow_search", false, \ 148976aa8d51SSumeet Rao "DP Rx Flow Search Table Is Per PDev") 149076aa8d51SSumeet Rao 149176aa8d51SSumeet Rao #define CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE \ 1492953a16bbSRuben Columbus CFG_INI_BOOL("dp_rx_monitor_protocol_flow_tag_enable", true, \ 149376aa8d51SSumeet Rao "Enable/Disable Rx Protocol & Flow tags in Monitor mode") 149476aa8d51SSumeet Rao 1495aae959eeSAnkit Kumar #define CFG_DP_TX_PER_PKT_VDEV_ID_CHECK \ 1496aae959eeSAnkit Kumar CFG_INI_BOOL("dp_tx_allow_per_pkt_vdev_id_check", false, \ 1497aae959eeSAnkit Kumar "Enable/Disable tx Per Pkt vdev id check") 1498aae959eeSAnkit Kumar 14993bc97480SJeevan Kukkalli #define CFG_DP_HANDLE_INVALID_DECAP_TYPE_DISABLE \ 15003bc97480SJeevan Kukkalli CFG_INI_BOOL("dp_handle_invalid_decap_type_disable", false, \ 15013bc97480SJeevan Kukkalli "Enable/Disable DP TLV out of order WAR") 15023bc97480SJeevan Kukkalli 15037432a2e2SNandha Kishore Easwaran #define CFG_DP_TXMON_SW_PEER_FILTERING \ 15047432a2e2SNandha Kishore Easwaran CFG_INI_BOOL("tx_litemon_sw_peer_filtering", false, \ 15057432a2e2SNandha Kishore Easwaran "Enable SW based tx monitor peer fitlering") 15067432a2e2SNandha Kishore Easwaran 1507c2c0f7f7SJinwei Chen #define CFG_DP_POINTER_TIMER_THRESHOLD_RX \ 1508c2c0f7f7SJinwei Chen CFG_INI_UINT("dp_rx_ptr_timer_threshold", \ 1509c2c0f7f7SJinwei Chen 0, 0xFFFF, 0, \ 1510c2c0f7f7SJinwei Chen CFG_VALUE_OR_DEFAULT, "RX pointer update timer threshold") 1511c2c0f7f7SJinwei Chen 1512c2c0f7f7SJinwei Chen #define CFG_DP_POINTER_NUM_THRESHOLD_RX \ 1513c2c0f7f7SJinwei Chen CFG_INI_UINT("dp_rx_ptr_num_threshold", \ 1514c2c0f7f7SJinwei Chen 0, 63, 0, \ 1515c2c0f7f7SJinwei Chen CFG_VALUE_OR_DEFAULT, "RX pointer update entries number threshold") 1516c2c0f7f7SJinwei Chen 1517b7a1c578SRuben Columbus #define CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD \ 1518b7a1c578SRuben Columbus CFG_INI_UINT("mon_drop_thresh", \ 1519b7a1c578SRuben Columbus WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN, \ 1520b7a1c578SRuben Columbus WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX, \ 1521b7a1c578SRuben Columbus WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE, \ 152229f3ca24SJeff Johnson CFG_VALUE_OR_DEFAULT, "RXDMA monitor rx drop threshold") 1523b7a1c578SRuben Columbus 15240265d791SAlok Kumar #define CFG_DP_PKTLOG_BUFFER_SIZE \ 15250265d791SAlok Kumar CFG_INI_UINT("PktlogBufSize", \ 15260265d791SAlok Kumar WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE, \ 15270265d791SAlok Kumar WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE, \ 15280265d791SAlok Kumar WLAN_CFG_PKTLOG_BUFFER_SIZE, \ 15290265d791SAlok Kumar CFG_VALUE_OR_DEFAULT, "Packet Log buffer size") 15300265d791SAlok Kumar 1531925a7d38SAmir Patel #define CFG_DP_FULL_MON_MODE \ 1532925a7d38SAmir Patel CFG_INI_BOOL("full_mon_mode", \ 1533925a7d38SAmir Patel false, "Full Monitor mode support") 1534925a7d38SAmir Patel 1535e3876720SNeha Bisht #define CFG_DP_REO_RINGS_MAP \ 1536e3876720SNeha Bisht CFG_INI_UINT("dp_reo_rings_map", \ 1537e3876720SNeha Bisht WLAN_CFG_NUM_REO_RINGS_MAP_MIN, \ 1538e3876720SNeha Bisht WLAN_CFG_NUM_REO_RINGS_MAP_MAX, \ 1539e3876720SNeha Bisht WLAN_CFG_NUM_REO_RINGS_MAP, \ 1540e3876720SNeha Bisht CFG_VALUE_OR_DEFAULT, "REO Destination Rings Mapping") 1541e3876720SNeha Bisht 15423048f538SRadha Krishna Simha Jiguru #define CFG_DP_RX_RADIO_0_DEFAULT_REO \ 15433048f538SRadha Krishna Simha Jiguru CFG_INI_UINT("dp_rx_radio0_default_reo", \ 15443048f538SRadha Krishna Simha Jiguru WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 15453048f538SRadha Krishna Simha Jiguru WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 15463048f538SRadha Krishna Simha Jiguru WLAN_CFG_RADIO_0_DEFAULT_REO, \ 15473048f538SRadha Krishna Simha Jiguru CFG_VALUE_OR_DEFAULT, "Radio0 to REO destination default mapping") 15483048f538SRadha Krishna Simha Jiguru 15493048f538SRadha Krishna Simha Jiguru #define CFG_DP_RX_RADIO_1_DEFAULT_REO \ 15503048f538SRadha Krishna Simha Jiguru CFG_INI_UINT("dp_rx_radio1_default_reo", \ 15513048f538SRadha Krishna Simha Jiguru WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 15523048f538SRadha Krishna Simha Jiguru WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 15533048f538SRadha Krishna Simha Jiguru WLAN_CFG_RADIO_1_DEFAULT_REO, \ 15543048f538SRadha Krishna Simha Jiguru CFG_VALUE_OR_DEFAULT, "Radio1 to REO destination default mapping") 15553048f538SRadha Krishna Simha Jiguru 15563048f538SRadha Krishna Simha Jiguru #define CFG_DP_RX_RADIO_2_DEFAULT_REO \ 15573048f538SRadha Krishna Simha Jiguru CFG_INI_UINT("dp_rx_radio2_default_reo", \ 15583048f538SRadha Krishna Simha Jiguru WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 15593048f538SRadha Krishna Simha Jiguru WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 15603048f538SRadha Krishna Simha Jiguru WLAN_CFG_RADIO_2_DEFAULT_REO, \ 15613048f538SRadha Krishna Simha Jiguru CFG_VALUE_OR_DEFAULT, "Radio2 to REO destination default mapping") 15623048f538SRadha Krishna Simha Jiguru 1563915f53b1SAniruddha Paul #define CFG_DP_PEER_EXT_STATS \ 1564915f53b1SAniruddha Paul CFG_INI_BOOL("peer_ext_stats", \ 1565915f53b1SAniruddha Paul false, "Peer extended stats") 1566204b7653STallapragada Kalyan 15676d5a37eeSAmit Mehta #if defined QCA_ENHANCED_STATS_SUPPORT || defined DP_MLO_LINK_STATS_SUPPORT 1568bad38983SKenvish Butani #define DEFAULT_PEER_LINK_STATS_VALUE true 1569bad38983SKenvish Butani #else 1570bad38983SKenvish Butani #define DEFAULT_PEER_LINK_STATS_VALUE false 1571bad38983SKenvish Butani #endif /* QCA_ENHANCED_STATS_SUPPORT */ 1572bad38983SKenvish Butani 1573bad38983SKenvish Butani #define CFG_DP_PEER_LINK_STATS \ 1574bad38983SKenvish Butani CFG_INI_BOOL("peer_link_stats", \ 1575bad38983SKenvish Butani DEFAULT_PEER_LINK_STATS_VALUE, "Peer Link stats") 1576bad38983SKenvish Butani 15779313b579SAmrit Sahai #define CFG_DP_PEER_JITTER_STATS \ 15789313b579SAmrit Sahai CFG_INI_BOOL("peer_jitter_stats", \ 15799313b579SAmrit Sahai false, "Peer Jitter stats") 15809313b579SAmrit Sahai 1581204b7653STallapragada Kalyan #define CFG_DP_NAPI_SCALE_FACTOR \ 1582204b7653STallapragada Kalyan CFG_INI_UINT("dp_napi_scale_factor", \ 1583204b7653STallapragada Kalyan WLAN_CFG_DP_NAPI_SCALE_FACTOR_MIN, \ 1584204b7653STallapragada Kalyan WLAN_CFG_DP_NAPI_SCALE_FACTOR_MAX, \ 1585204b7653STallapragada Kalyan WLAN_CFG_DP_NAPI_SCALE_FACTOR, \ 1586204b7653STallapragada Kalyan CFG_VALUE_OR_DEFAULT, "NAPI scale factor for DP") 1587204b7653STallapragada Kalyan 1588*37e5a76cSAman Mehta #define CFG_DP_STATS_AVG_RATE_FILTER \ 1589*37e5a76cSAman Mehta CFG_INI_UINT("dp_stats_avg_rate_filter_val", \ 1590*37e5a76cSAman Mehta WLAN_CFG_DP_AVG_RATE_FILTER_MIN,\ 1591*37e5a76cSAman Mehta WLAN_CFG_DP_AVG_RATE_FILTER_MAX, \ 1592*37e5a76cSAman Mehta WLAN_CFG_DP_AVG_RATE_FILTER_DEFAULT, \ 1593*37e5a76cSAman Mehta CFG_VALUE_OR_DEFAULT, \ 1594*37e5a76cSAman Mehta "Average Rate filter for stats") 1595*37e5a76cSAman Mehta 159693aff9eeSManjunathappa Prakash /* 159793aff9eeSManjunathappa Prakash * <ini> 159893aff9eeSManjunathappa Prakash * legacy_mode_csum_disable - Disable csum offload for legacy 802.11abg modes 159993aff9eeSManjunathappa Prakash * @Min: 0 160093aff9eeSManjunathappa Prakash * @Max: 1 16011370e032SAlan Chen * @Default: Default value indicating if checksum should be disabled for 16021370e032SAlan Chen * legacy WLAN modes 160393aff9eeSManjunathappa Prakash * 160493aff9eeSManjunathappa Prakash * This ini is used to disable HW checksum offload capability for legacy 160593aff9eeSManjunathappa Prakash * connections 160693aff9eeSManjunathappa Prakash * 160793aff9eeSManjunathappa Prakash * Related: gEnableIpTcpUdpChecksumOffload should be enabled 160893aff9eeSManjunathappa Prakash * 160993aff9eeSManjunathappa Prakash * Usage: Internal 161093aff9eeSManjunathappa Prakash * 161193aff9eeSManjunathappa Prakash * </ini> 161293aff9eeSManjunathappa Prakash */ 16131370e032SAlan Chen #ifndef DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 16141370e032SAlan Chen #define DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1 16151370e032SAlan Chen #endif 161693aff9eeSManjunathappa Prakash 161793aff9eeSManjunathappa Prakash #define CFG_DP_LEGACY_MODE_CSUM_DISABLE \ 16181370e032SAlan Chen CFG_INI_BOOL("legacy_mode_csum_disable", \ 16191370e032SAlan Chen DP_LEGACY_MODE_CSM_DEFAULT_DISABLE, \ 162093aff9eeSManjunathappa Prakash "Enable/Disable legacy mode checksum") 1621915f53b1SAniruddha Paul 1622d315e2d2SManikanta Pubbisetty #define CFG_DP_RX_BUFF_POOL_ENABLE \ 1623d315e2d2SManikanta Pubbisetty CFG_INI_BOOL("dp_rx_buff_prealloc_pool", false, \ 1624d315e2d2SManikanta Pubbisetty "Enable/Disable DP RX emergency buffer pool support") 1625d315e2d2SManikanta Pubbisetty 162647b1fe64SKarthik Kantamneni #define CFG_DP_RX_REFILL_BUFF_POOL_ENABLE \ 162747b1fe64SKarthik Kantamneni CFG_INI_BOOL("dp_rx_refill_buff_pool", false, \ 162847b1fe64SKarthik Kantamneni "Enable/Disable DP RX refill buffer pool support") 162947b1fe64SKarthik Kantamneni 1630fab64e0aSPrakash Manjunathappa #define CFG_DP_BUFS_PAGE_FRAG_ALLOCS \ 1631fab64e0aSPrakash Manjunathappa CFG_INI_BOOL("dp_bufs_page_frag_allocs", true, \ 1632fab64e0aSPrakash Manjunathappa "Enable/Disable forced DP page frage buffer allocations") 1633fab64e0aSPrakash Manjunathappa 1634b257b236SSridhar Selvaraj #define CFG_DP_POLL_MODE_ENABLE \ 1635b257b236SSridhar Selvaraj CFG_INI_BOOL("dp_poll_mode_enable", false, \ 1636b257b236SSridhar Selvaraj "Enable/Disable Polling mode for data path") 1637b257b236SSridhar Selvaraj 1638905d9e33SManikanta Pubbisetty #define CFG_DP_RX_FST_IN_CMEM \ 1639905d9e33SManikanta Pubbisetty CFG_INI_BOOL("dp_rx_fst_in_cmem", false, \ 1640905d9e33SManikanta Pubbisetty "Enable/Disable flow search table in CMEM") 164102723d3bSRakesh Pillai /* 164202723d3bSRakesh Pillai * <ini> 164302723d3bSRakesh Pillai * gEnableSWLM - Control DP Software latency manager 164402723d3bSRakesh Pillai * @Min: 0 164502723d3bSRakesh Pillai * @Max: 1 164602723d3bSRakesh Pillai * @Default: 0 164702723d3bSRakesh Pillai * 164802723d3bSRakesh Pillai * This ini is used to enable DP Software latency Manager 164902723d3bSRakesh Pillai * 165002723d3bSRakesh Pillai * Supported Feature: STA,P2P and SAP IPA disabled terminating 165102723d3bSRakesh Pillai * 165202723d3bSRakesh Pillai * Usage: Internal 165302723d3bSRakesh Pillai * 165402723d3bSRakesh Pillai * </ini> 165502723d3bSRakesh Pillai */ 165602723d3bSRakesh Pillai #define CFG_DP_SWLM_ENABLE \ 165702723d3bSRakesh Pillai CFG_INI_BOOL("gEnableSWLM", false, \ 165802723d3bSRakesh Pillai "Enable/Disable DP SWLM") 165976fdb54eSYu Tian /* 166076fdb54eSYu Tian * <ini> 166176fdb54eSYu Tian * wow_check_rx_pending_enable - control to check RX frames pending in Wow 166276fdb54eSYu Tian * @Min: 0 166376fdb54eSYu Tian * @Max: 1 166476fdb54eSYu Tian * @Default: 0 166576fdb54eSYu Tian * 166676fdb54eSYu Tian * This ini is used to control DP Software to perform RX pending check 166776fdb54eSYu Tian * before entering WoW mode 166876fdb54eSYu Tian * 166976fdb54eSYu Tian * Usage: Internal 167076fdb54eSYu Tian * 167176fdb54eSYu Tian * </ini> 167276fdb54eSYu Tian */ 167376fdb54eSYu Tian #define CFG_DP_WOW_CHECK_RX_PENDING \ 167476fdb54eSYu Tian CFG_INI_BOOL("wow_check_rx_pending_enable", \ 167576fdb54eSYu Tian false, \ 167676fdb54eSYu Tian "enable rx frame pending check in WoW mode") 167776b9febdSAmir Patel #define CFG_DP_DELAY_MON_REPLENISH \ 167876b9febdSAmir Patel CFG_INI_BOOL("delay_mon_replenish", \ 167976b9febdSAmir Patel true, "Delay Monitor Replenish") 168002723d3bSRakesh Pillai 1681f76548ddSHarsh Kumar Bijlani #ifdef QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT 1682f76548ddSHarsh Kumar Bijlani #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN 500 1683f76548ddSHarsh Kumar Bijlani #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX 2000 1684f76548ddSHarsh Kumar Bijlani #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER 500 1685f76548ddSHarsh Kumar Bijlani 1686f76548ddSHarsh Kumar Bijlani #define CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG \ 1687f76548ddSHarsh Kumar Bijlani CFG_INI_BOOL("vdev_stats_hw_offload_config", \ 1688f76548ddSHarsh Kumar Bijlani false, "Offload vdev stats to HW") 1689f76548ddSHarsh Kumar Bijlani #define CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER \ 1690f76548ddSHarsh Kumar Bijlani CFG_INI_UINT("vdev_stats_hw_offload_timer", \ 1691f76548ddSHarsh Kumar Bijlani WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN, \ 1692f76548ddSHarsh Kumar Bijlani WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX, \ 1693f76548ddSHarsh Kumar Bijlani WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER, \ 1694f76548ddSHarsh Kumar Bijlani CFG_VALUE_OR_DEFAULT, \ 1695f76548ddSHarsh Kumar Bijlani "vdev stats hw offload timer duration") 1696f76548ddSHarsh Kumar Bijlani #define CFG_DP_VDEV_STATS_HW_OFFLOAD \ 1697f76548ddSHarsh Kumar Bijlani CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG) \ 1698f76548ddSHarsh Kumar Bijlani CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER) 1699f76548ddSHarsh Kumar Bijlani #else 1700f76548ddSHarsh Kumar Bijlani #define CFG_DP_VDEV_STATS_HW_OFFLOAD 1701f76548ddSHarsh Kumar Bijlani #endif 1702f76548ddSHarsh Kumar Bijlani 1703abb64b56SYu Tian /* 1704abb64b56SYu Tian * <ini> 170540831551SJinwei Chen * ghw_cc_enable - enable HW cookie conversion by register 170640831551SJinwei Chen * @Min: 0 170740831551SJinwei Chen * @Max: 1 170840831551SJinwei Chen * @Default: 1 170940831551SJinwei Chen * 171040831551SJinwei Chen * This ini is used to control HW based 20 bits cookie to 64 bits 171140831551SJinwei Chen * Desc virtual address conversion 171240831551SJinwei Chen * 171340831551SJinwei Chen * Usage: Internal 171440831551SJinwei Chen * 171540831551SJinwei Chen * </ini> 171640831551SJinwei Chen */ 171740831551SJinwei Chen #define CFG_DP_HW_CC_ENABLE \ 171840831551SJinwei Chen CFG_INI_BOOL("ghw_cc_enable", \ 171940831551SJinwei Chen true, "Enable/Disable HW cookie conversion") 172040831551SJinwei Chen 1721b5a3efabSYeshwanth Sriram Guntuka #ifdef IPA_OFFLOAD 1722b5a3efabSYeshwanth Sriram Guntuka /* 1723b5a3efabSYeshwanth Sriram Guntuka * <ini> 1724b5a3efabSYeshwanth Sriram Guntuka * dp_ipa_tx_ring_size - Set tcl ring size for IPA 1725b5a3efabSYeshwanth Sriram Guntuka * @Min: 1024 1726b5a3efabSYeshwanth Sriram Guntuka * @Max: 8096 1727b5a3efabSYeshwanth Sriram Guntuka * @Default: 1024 1728b5a3efabSYeshwanth Sriram Guntuka * 1729b5a3efabSYeshwanth Sriram Guntuka * This ini sets the tcl ring size for IPA 1730b5a3efabSYeshwanth Sriram Guntuka * 1731b5a3efabSYeshwanth Sriram Guntuka * Related: N/A 1732b5a3efabSYeshwanth Sriram Guntuka * 1733b5a3efabSYeshwanth Sriram Guntuka * Supported Feature: IPA 1734b5a3efabSYeshwanth Sriram Guntuka * 1735b5a3efabSYeshwanth Sriram Guntuka * Usage: Internal 1736b5a3efabSYeshwanth Sriram Guntuka * 1737b5a3efabSYeshwanth Sriram Guntuka * </ini> 1738b5a3efabSYeshwanth Sriram Guntuka */ 1739b5a3efabSYeshwanth Sriram Guntuka #define CFG_DP_IPA_TX_RING_SIZE \ 1740b5a3efabSYeshwanth Sriram Guntuka CFG_INI_UINT("dp_ipa_tx_ring_size", \ 1741b5a3efabSYeshwanth Sriram Guntuka WLAN_CFG_IPA_TX_RING_SIZE_MIN, \ 1742b5a3efabSYeshwanth Sriram Guntuka WLAN_CFG_IPA_TX_RING_SIZE_MAX, \ 1743b5a3efabSYeshwanth Sriram Guntuka WLAN_CFG_IPA_TX_RING_SIZE, \ 1744b5a3efabSYeshwanth Sriram Guntuka CFG_VALUE_OR_DEFAULT, "IPA TCL ring size") 1745b5a3efabSYeshwanth Sriram Guntuka 1746b5a3efabSYeshwanth Sriram Guntuka /* 1747b5a3efabSYeshwanth Sriram Guntuka * <ini> 1748b5a3efabSYeshwanth Sriram Guntuka * dp_ipa_tx_comp_ring_size - Set tx comp ring size for IPA 1749b5a3efabSYeshwanth Sriram Guntuka * @Min: 1024 1750b5a3efabSYeshwanth Sriram Guntuka * @Max: 8096 1751b5a3efabSYeshwanth Sriram Guntuka * @Default: 1024 1752b5a3efabSYeshwanth Sriram Guntuka * 1753b5a3efabSYeshwanth Sriram Guntuka * This ini sets the tx comp ring size for IPA 1754b5a3efabSYeshwanth Sriram Guntuka * 1755b5a3efabSYeshwanth Sriram Guntuka * Related: N/A 1756b5a3efabSYeshwanth Sriram Guntuka * 1757b5a3efabSYeshwanth Sriram Guntuka * Supported Feature: IPA 1758b5a3efabSYeshwanth Sriram Guntuka * 1759b5a3efabSYeshwanth Sriram Guntuka * Usage: Internal 1760b5a3efabSYeshwanth Sriram Guntuka * 1761b5a3efabSYeshwanth Sriram Guntuka * </ini> 1762b5a3efabSYeshwanth Sriram Guntuka */ 1763b5a3efabSYeshwanth Sriram Guntuka #define CFG_DP_IPA_TX_COMP_RING_SIZE \ 1764b5a3efabSYeshwanth Sriram Guntuka CFG_INI_UINT("dp_ipa_tx_comp_ring_size", \ 1765b5a3efabSYeshwanth Sriram Guntuka WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN, \ 1766b5a3efabSYeshwanth Sriram Guntuka WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX, \ 1767b5a3efabSYeshwanth Sriram Guntuka WLAN_CFG_IPA_TX_COMP_RING_SIZE, \ 1768b5a3efabSYeshwanth Sriram Guntuka CFG_VALUE_OR_DEFAULT, "IPA tx comp ring size") 1769b5a3efabSYeshwanth Sriram Guntuka 177014d9d6d6Schunquan #ifdef IPA_WDI3_TX_TWO_PIPES 177114d9d6d6Schunquan /* 177214d9d6d6Schunquan * <ini> 177314d9d6d6Schunquan * dp_ipa_tx_alt_ring_size - Set alt tcl ring size for IPA 177414d9d6d6Schunquan * @Min: 1024 177514d9d6d6Schunquan * @Max: 8096 177614d9d6d6Schunquan * @Default: 1024 177714d9d6d6Schunquan * 177814d9d6d6Schunquan * This ini sets the alt tcl ring size for IPA 177914d9d6d6Schunquan * 178014d9d6d6Schunquan * Related: N/A 178114d9d6d6Schunquan * 178214d9d6d6Schunquan * Supported Feature: IPA 178314d9d6d6Schunquan * 178414d9d6d6Schunquan * Usage: Internal 178514d9d6d6Schunquan * 178614d9d6d6Schunquan * </ini> 178714d9d6d6Schunquan */ 178814d9d6d6Schunquan #define CFG_DP_IPA_TX_ALT_RING_SIZE \ 178914d9d6d6Schunquan CFG_INI_UINT("dp_ipa_tx_alt_ring_size", \ 179014d9d6d6Schunquan WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN, \ 179114d9d6d6Schunquan WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX, \ 179214d9d6d6Schunquan WLAN_CFG_IPA_TX_ALT_RING_SIZE, \ 179314d9d6d6Schunquan CFG_VALUE_OR_DEFAULT, \ 179414d9d6d6Schunquan "DP IPA TX Alternative Ring Size") 179514d9d6d6Schunquan 179614d9d6d6Schunquan /* 179714d9d6d6Schunquan * <ini> 179814d9d6d6Schunquan * dp_ipa_tx_alt_comp_ring_size - Set tx alt comp ring size for IPA 179914d9d6d6Schunquan * @Min: 1024 180014d9d6d6Schunquan * @Max: 8096 180114d9d6d6Schunquan * @Default: 1024 180214d9d6d6Schunquan * 180314d9d6d6Schunquan * This ini sets the tx alt comp ring size for IPA 180414d9d6d6Schunquan * 180514d9d6d6Schunquan * Related: N/A 180614d9d6d6Schunquan * 180714d9d6d6Schunquan * Supported Feature: IPA 180814d9d6d6Schunquan * 180914d9d6d6Schunquan * Usage: Internal 181014d9d6d6Schunquan * 181114d9d6d6Schunquan * </ini> 181214d9d6d6Schunquan */ 181314d9d6d6Schunquan #define CFG_DP_IPA_TX_ALT_COMP_RING_SIZE \ 181414d9d6d6Schunquan CFG_INI_UINT("dp_ipa_tx_alt_comp_ring_size", \ 181514d9d6d6Schunquan WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN, \ 181614d9d6d6Schunquan WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX, \ 181714d9d6d6Schunquan WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE, \ 181814d9d6d6Schunquan CFG_VALUE_OR_DEFAULT, \ 181914d9d6d6Schunquan "DP IPA TX Alternative Completion Ring Size") 182014d9d6d6Schunquan 182114d9d6d6Schunquan #define CFG_DP_IPA_TX_ALT_RING_CFG \ 182214d9d6d6Schunquan CFG(CFG_DP_IPA_TX_ALT_RING_SIZE) \ 182314d9d6d6Schunquan CFG(CFG_DP_IPA_TX_ALT_COMP_RING_SIZE) 182414d9d6d6Schunquan 182514d9d6d6Schunquan #else 182614d9d6d6Schunquan #define CFG_DP_IPA_TX_ALT_RING_CFG 182714d9d6d6Schunquan #endif 182814d9d6d6Schunquan 1829b5a3efabSYeshwanth Sriram Guntuka #define CFG_DP_IPA_TX_RING_CFG \ 1830b5a3efabSYeshwanth Sriram Guntuka CFG(CFG_DP_IPA_TX_RING_SIZE) \ 1831b5a3efabSYeshwanth Sriram Guntuka CFG(CFG_DP_IPA_TX_COMP_RING_SIZE) 1832b5a3efabSYeshwanth Sriram Guntuka #else 1833b5a3efabSYeshwanth Sriram Guntuka #define CFG_DP_IPA_TX_RING_CFG 183414d9d6d6Schunquan #define CFG_DP_IPA_TX_ALT_RING_CFG 1835b5a3efabSYeshwanth Sriram Guntuka #endif 1836b5a3efabSYeshwanth Sriram Guntuka 18370702aaf4SChaithanya Garrepalli #ifdef WLAN_SUPPORT_PPEDS 183800422483SPavankumar Nandeshwar #define WLAN_CFG_NUM_PPEDS_TX_DESC_MIN 16 18394066ad24SPavankumar Nandeshwar #define WLAN_CFG_NUM_PPEDS_TX_DESC_MAX 0xFA00 184000422483SPavankumar Nandeshwar #define WLAN_CFG_NUM_PPEDS_TX_DESC 0x8000 184100422483SPavankumar Nandeshwar 1842ab2bd061SPavankumar Nandeshwar #define WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MIN 8 1843ab2bd061SPavankumar Nandeshwar #define WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MAX 256 1844ab2bd061SPavankumar Nandeshwar #define WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI 64 1845ab2bd061SPavankumar Nandeshwar 18460a7d729aSPavankumar Nandeshwar #define WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN_MIN 0 18470a7d729aSPavankumar Nandeshwar #define WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN_MAX 0x2000 18480a7d729aSPavankumar Nandeshwar #define WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN 0x400 18490a7d729aSPavankumar Nandeshwar 185000422483SPavankumar Nandeshwar #define CFG_DP_PPEDS_TX_DESC \ 185100422483SPavankumar Nandeshwar CFG_INI_UINT("dp_ppeds_tx_desc", \ 185200422483SPavankumar Nandeshwar WLAN_CFG_NUM_PPEDS_TX_DESC_MIN, \ 185300422483SPavankumar Nandeshwar WLAN_CFG_NUM_PPEDS_TX_DESC_MAX, \ 185400422483SPavankumar Nandeshwar WLAN_CFG_NUM_PPEDS_TX_DESC, \ 185500422483SPavankumar Nandeshwar CFG_VALUE_OR_DEFAULT, "DP PPEDS Tx Descriptors") 185600422483SPavankumar Nandeshwar 18570a7d729aSPavankumar Nandeshwar #define CFG_DP_PPEDS_TX_DESC_HOTLIST_LEN \ 18580a7d729aSPavankumar Nandeshwar CFG_INI_UINT("dp_ppeds_tx_desc_hotlist_len", \ 18590a7d729aSPavankumar Nandeshwar WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN_MIN, \ 18600a7d729aSPavankumar Nandeshwar WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN_MAX, \ 18610a7d729aSPavankumar Nandeshwar WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN, \ 18620a7d729aSPavankumar Nandeshwar CFG_VALUE_OR_DEFAULT, "DP PPEDS Tx Desc hotlist length") 18630a7d729aSPavankumar Nandeshwar 1864ab2bd061SPavankumar Nandeshwar #define CFG_DP_PPEDS_TX_CMP_NAPI_BUDGET \ 1865ab2bd061SPavankumar Nandeshwar CFG_INI_UINT("dp_ppeds_tx_cmp_napi_budget", \ 1866ab2bd061SPavankumar Nandeshwar WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MIN, \ 1867ab2bd061SPavankumar Nandeshwar WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MAX, \ 1868ab2bd061SPavankumar Nandeshwar WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI, \ 1869ab2bd061SPavankumar Nandeshwar CFG_VALUE_OR_DEFAULT, "DP PPEDS Tx Comp handler napi budget") 1870ab2bd061SPavankumar Nandeshwar 1871c811b9d5SPavankumar Nandeshwar #define CFG_DP_PPEDS_ENABLE \ 1872a7ec0b56SPavankumar Nandeshwar CFG_INI_BOOL("ppe_ds_enable", true, \ 18730702aaf4SChaithanya Garrepalli "DP ppe enable flag") 18740702aaf4SChaithanya Garrepalli 18750702aaf4SChaithanya Garrepalli #define CFG_DP_REO2PPE_RING \ 18760702aaf4SChaithanya Garrepalli CFG_INI_UINT("dp_reo2ppe_ring", \ 18770702aaf4SChaithanya Garrepalli WLAN_CFG_REO2PPE_RING_SIZE_MIN, \ 18780702aaf4SChaithanya Garrepalli WLAN_CFG_REO2PPE_RING_SIZE_MAX, \ 18790702aaf4SChaithanya Garrepalli WLAN_CFG_REO2PPE_RING_SIZE, \ 18800702aaf4SChaithanya Garrepalli CFG_VALUE_OR_DEFAULT, "DP REO2PPE ring") 18810702aaf4SChaithanya Garrepalli 18820702aaf4SChaithanya Garrepalli #define CFG_DP_PPE2TCL_RING \ 18830702aaf4SChaithanya Garrepalli CFG_INI_UINT("dp_ppe2tcl_ring", \ 18840702aaf4SChaithanya Garrepalli WLAN_CFG_PPE2TCL_RING_SIZE_MIN, \ 18850702aaf4SChaithanya Garrepalli WLAN_CFG_PPE2TCL_RING_SIZE_MAX, \ 18860702aaf4SChaithanya Garrepalli WLAN_CFG_PPE2TCL_RING_SIZE, \ 18870702aaf4SChaithanya Garrepalli CFG_VALUE_OR_DEFAULT, "DP PPE2TCL rings") 18880702aaf4SChaithanya Garrepalli 18890be3bb02SNitin Shetty #define CFG_DP_PPEDS_WIFI_SOC_CFG \ 18900be3bb02SNitin Shetty CFG_INI_UINT("ppeds_wifi_soc_cfg", \ 18910be3bb02SNitin Shetty CFG_DP_PPEDS_WIFI_SOC_CFG_NONE, \ 18920be3bb02SNitin Shetty CFG_DP_PPEDS_WIFI_SOC_CFG_ALL, \ 18930be3bb02SNitin Shetty CFG_DP_PPEDS_WIFI_SOC_CFG_DEFAULT, \ 18940be3bb02SNitin Shetty CFG_VALUE_OR_DEFAULT, "PPEDS enable per WiFi SoC") 18950be3bb02SNitin Shetty 1896c811b9d5SPavankumar Nandeshwar #define CFG_DP_PPEDS_CONFIG \ 1897ab2bd061SPavankumar Nandeshwar CFG(CFG_DP_PPEDS_TX_CMP_NAPI_BUDGET) \ 18980a7d729aSPavankumar Nandeshwar CFG(CFG_DP_PPEDS_TX_DESC_HOTLIST_LEN) \ 189900422483SPavankumar Nandeshwar CFG(CFG_DP_PPEDS_TX_DESC) \ 1900c811b9d5SPavankumar Nandeshwar CFG(CFG_DP_PPEDS_ENABLE) \ 19010702aaf4SChaithanya Garrepalli CFG(CFG_DP_REO2PPE_RING) \ 19020be3bb02SNitin Shetty CFG(CFG_DP_PPE2TCL_RING) \ 19030be3bb02SNitin Shetty CFG(CFG_DP_PPEDS_WIFI_SOC_CFG) 19040702aaf4SChaithanya Garrepalli #else 1905c811b9d5SPavankumar Nandeshwar #define CFG_DP_PPEDS_CONFIG 190600422483SPavankumar Nandeshwar #define WLAN_CFG_NUM_PPEDS_TX_DESC_MAX 0 19070702aaf4SChaithanya Garrepalli #endif 19080702aaf4SChaithanya Garrepalli 1909fc126094SYu Tian #define WLAN_CFG_SPECIAL_MSK_MIN 0 1910fc126094SYu Tian #define WLAN_CFG_SPECIAL_MSK_MAX 0xFFFFFFFF 1911fc126094SYu Tian #define WLAN_CFG_SPECIAL_MSK 0xF 1912fc126094SYu Tian 1913c42af1f6SChaithanya Garrepalli #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 1914c42af1f6SChaithanya Garrepalli /* 1915c42af1f6SChaithanya Garrepalli * <ini> 1916c42af1f6SChaithanya Garrepalli * dp_chip0_rx_ring_map - Set Rx ring map for CHIP 0 1917c42af1f6SChaithanya Garrepalli * @Min: 0x0 1918c42af1f6SChaithanya Garrepalli * @Max: 0xFF 1919c42af1f6SChaithanya Garrepalli * @Default: 0xF 1920c42af1f6SChaithanya Garrepalli * 1921c42af1f6SChaithanya Garrepalli * This ini sets Rx ring map for CHIP 0 1922c42af1f6SChaithanya Garrepalli * 1923c42af1f6SChaithanya Garrepalli * Usage: Internal 1924c42af1f6SChaithanya Garrepalli * 1925c42af1f6SChaithanya Garrepalli * </ini> 1926c42af1f6SChaithanya Garrepalli */ 1927adbb7700SChaithanya Garrepalli #define CFG_DP_MLO_RX_RING_MAP \ 1928adbb7700SChaithanya Garrepalli CFG_INI_UINT("dp_mlo_reo_rings_map", \ 1929c42af1f6SChaithanya Garrepalli WLAN_CFG_MLO_RX_RING_MAP_MIN, \ 1930c42af1f6SChaithanya Garrepalli WLAN_CFG_MLO_RX_RING_MAP_MAX, \ 1931c42af1f6SChaithanya Garrepalli WLAN_CFG_MLO_RX_RING_MAP, \ 1932adbb7700SChaithanya Garrepalli CFG_VALUE_OR_DEFAULT, "DP MLO Rx ring map") 1933c42af1f6SChaithanya Garrepalli 1934c42af1f6SChaithanya Garrepalli 1935c42af1f6SChaithanya Garrepalli #define CFG_DP_MLO_CONFIG \ 1936adbb7700SChaithanya Garrepalli CFG(CFG_DP_MLO_RX_RING_MAP) 1937c42af1f6SChaithanya Garrepalli #else 1938c42af1f6SChaithanya Garrepalli #define CFG_DP_MLO_CONFIG 1939c42af1f6SChaithanya Garrepalli #endif 1940c42af1f6SChaithanya Garrepalli 19411507b1cdSAmit Mehta /* 19421507b1cdSAmit Mehta * <ini> 19431507b1cdSAmit Mehta * dp_mpdu_retry_threshold_1 - threshold to increment mpdu success with retries 19441507b1cdSAmit Mehta * @Min: 0 19451507b1cdSAmit Mehta * @Max: 255 19461507b1cdSAmit Mehta * @Default: 0 19471507b1cdSAmit Mehta * 19481507b1cdSAmit Mehta * This ini entry is used to set first threshold to increment the value of 19491507b1cdSAmit Mehta * mpdu_success_with_retries 19501507b1cdSAmit Mehta * 19511507b1cdSAmit Mehta * Usage: Internal 19521507b1cdSAmit Mehta * 19531507b1cdSAmit Mehta * </ini> 19541507b1cdSAmit Mehta */ 19551507b1cdSAmit Mehta #define CFG_DP_MPDU_RETRY_THRESHOLD_1 \ 19561507b1cdSAmit Mehta CFG_INI_UINT("dp_mpdu_retry_threshold_1", \ 19571507b1cdSAmit Mehta CFG_DP_MPDU_RETRY_THRESHOLD_MIN, \ 19581507b1cdSAmit Mehta CFG_DP_MPDU_RETRY_THRESHOLD_MAX, \ 19591507b1cdSAmit Mehta CFG_DP_MPDU_RETRY_THRESHOLD, \ 19601507b1cdSAmit Mehta CFG_VALUE_OR_DEFAULT, "DP mpdu retry threshold 1") 19611507b1cdSAmit Mehta 19621507b1cdSAmit Mehta /* 19631507b1cdSAmit Mehta * <ini> 19641507b1cdSAmit Mehta * dp_mpdu_retry_threshold_2 - threshold to increment mpdu success with retries 19651507b1cdSAmit Mehta * @Min: 0 19661507b1cdSAmit Mehta * @Max: 255 19671507b1cdSAmit Mehta * @Default: 0 19681507b1cdSAmit Mehta * 19691507b1cdSAmit Mehta * This ini entry is used to set second threshold to increment the value of 19701507b1cdSAmit Mehta * mpdu_success_with_retries 19711507b1cdSAmit Mehta * 19721507b1cdSAmit Mehta * Usage: Internal 19731507b1cdSAmit Mehta * 19741507b1cdSAmit Mehta * </ini> 19751507b1cdSAmit Mehta */ 19761507b1cdSAmit Mehta #define CFG_DP_MPDU_RETRY_THRESHOLD_2 \ 19771507b1cdSAmit Mehta CFG_INI_UINT("dp_mpdu_retry_threshold_2", \ 19781507b1cdSAmit Mehta CFG_DP_MPDU_RETRY_THRESHOLD_MIN, \ 19791507b1cdSAmit Mehta CFG_DP_MPDU_RETRY_THRESHOLD_MAX, \ 19801507b1cdSAmit Mehta CFG_DP_MPDU_RETRY_THRESHOLD, \ 19811507b1cdSAmit Mehta CFG_VALUE_OR_DEFAULT, "DP mpdu retry threshold 2") 19821507b1cdSAmit Mehta 19830c558b77SMohit Khanna #ifdef QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES 19840c558b77SMohit Khanna /* Macro enabling support marking of notify frames by host */ 19850c558b77SMohit Khanna #define DP_MARK_NOTIFY_FRAME_SUPPORT 1 19860c558b77SMohit Khanna #else 19870c558b77SMohit Khanna #define DP_MARK_NOTIFY_FRAME_SUPPORT 0 19880c558b77SMohit Khanna #endif /* QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES */ 19890c558b77SMohit Khanna 199018f8aed5Ssyed touqeer pasha /* 199118f8aed5Ssyed touqeer pasha * <ini> 199218f8aed5Ssyed touqeer pasha * Host DP AST entries database - Enable/Disable 199318f8aed5Ssyed touqeer pasha * 199418f8aed5Ssyed touqeer pasha * @Default: 0 199518f8aed5Ssyed touqeer pasha * 199618f8aed5Ssyed touqeer pasha * This ini enables/disables AST entries database on host 199718f8aed5Ssyed touqeer pasha * 199818f8aed5Ssyed touqeer pasha * Usage: Internal 199918f8aed5Ssyed touqeer pasha * 200018f8aed5Ssyed touqeer pasha * </ini> 200118f8aed5Ssyed touqeer pasha */ 200218f8aed5Ssyed touqeer pasha #define CFG_DP_HOST_AST_DB_ENABLE \ 200318f8aed5Ssyed touqeer pasha CFG_INI_BOOL("host_ast_db_enable", false, \ 200418f8aed5Ssyed touqeer pasha "Host AST entries database Enable/Disable") 200518f8aed5Ssyed touqeer pasha 2006b4f81eacSJinwei Chen #ifdef DP_TX_PACKET_INSPECT_FOR_ILP 2007b4f81eacSJinwei Chen /* 2008b4f81eacSJinwei Chen * <ini> 2009b4f81eacSJinwei Chen * TX packet inspect for ILP - Enable/Disable 2010b4f81eacSJinwei Chen * 2011b4f81eacSJinwei Chen * @Default: true 2012b4f81eacSJinwei Chen * 2013b4f81eacSJinwei Chen * This ini enable/disables TX packet inspection for ILP feature 2014b4f81eacSJinwei Chen * 2015b4f81eacSJinwei Chen * Usage: Internal 2016b4f81eacSJinwei Chen * 2017b4f81eacSJinwei Chen * </ini> 2018b4f81eacSJinwei Chen */ 2019b4f81eacSJinwei Chen #define CFG_TX_PKT_INSPECT_FOR_ILP \ 2020b4f81eacSJinwei Chen CFG_INI_BOOL("tx_pkt_inspect_for_ilp", true, \ 2021b4f81eacSJinwei Chen "TX packet inspect for ILP") 2022b4f81eacSJinwei Chen #define CFG_TX_PKT_INSPECT_FOR_ILP_CFG CFG(CFG_TX_PKT_INSPECT_FOR_ILP) 2023b4f81eacSJinwei Chen #else 2024b4f81eacSJinwei Chen #define CFG_TX_PKT_INSPECT_FOR_ILP_CFG 2025b4f81eacSJinwei Chen #endif 2026b4f81eacSJinwei Chen 2027fc126094SYu Tian /* 2028fc126094SYu Tian * <ini> 2029fc126094SYu Tian * special_frame_msk - frame mask to mark special frame type 2030fc126094SYu Tian * @Min: 0 2031fc126094SYu Tian * @Max: 0xFFFFFFFF 2032fc126094SYu Tian * @Default: 15 2033fc126094SYu Tian * 2034fc126094SYu Tian * This ini entry is used to set frame types to deliver to stack 2035fc126094SYu Tian * in error receive path 2036fc126094SYu Tian * 2037fc126094SYu Tian * Usage: External 2038fc126094SYu Tian * 2039fc126094SYu Tian * </ini> 2040fc126094SYu Tian */ 2041fc126094SYu Tian #define CFG_SPECIAL_FRAME_MSK \ 2042fc126094SYu Tian CFG_INI_UINT("special_frame_msk", \ 2043fc126094SYu Tian WLAN_CFG_SPECIAL_MSK_MIN, \ 2044fc126094SYu Tian WLAN_CFG_SPECIAL_MSK_MAX, \ 2045fc126094SYu Tian WLAN_CFG_SPECIAL_MSK, \ 2046fc126094SYu Tian CFG_VALUE_OR_DEFAULT, "special frame to deliver to stack") 2047fc126094SYu Tian 20487f898dfcSShashikala Prabhu #ifdef DP_UMAC_HW_RESET_SUPPORT 20497f898dfcSShashikala Prabhu #define CFG_DP_UMAC_RESET_BUFFER_WINDOW_MIN 100 20507f898dfcSShashikala Prabhu #define CFG_DP_UMAC_RESET_BUFFER_WINDOW_MAX 10000 20517f898dfcSShashikala Prabhu #define CFG_DP_UMAC_RESET_BUFFER_WINDOW_DEFAULT 1000 20527f898dfcSShashikala Prabhu 20537f898dfcSShashikala Prabhu #define CFG_DP_UMAC_RESET_BUFFER_WINDOW \ 20547f898dfcSShashikala Prabhu CFG_INI_UINT("umac_reset_buffer_window", \ 20557f898dfcSShashikala Prabhu CFG_DP_UMAC_RESET_BUFFER_WINDOW_MIN, \ 20567f898dfcSShashikala Prabhu CFG_DP_UMAC_RESET_BUFFER_WINDOW_MAX, \ 20577f898dfcSShashikala Prabhu CFG_DP_UMAC_RESET_BUFFER_WINDOW_DEFAULT, \ 20587f898dfcSShashikala Prabhu CFG_VALUE_OR_DEFAULT, \ 20597f898dfcSShashikala Prabhu "Buffer time to check if umac reset was in progress during this window, configured time is in milliseconds") 20607f898dfcSShashikala Prabhu #define CFG_DP_UMAC_RESET_BUFFER_WINDOW_CFG CFG(CFG_DP_UMAC_RESET_BUFFER_WINDOW) 20617f898dfcSShashikala Prabhu #else 20627f898dfcSShashikala Prabhu #define CFG_DP_UMAC_RESET_BUFFER_WINDOW_CFG 20637f898dfcSShashikala Prabhu #endif /* DP_UMAC_HW_RESET_SUPPORT */ 20647f898dfcSShashikala Prabhu 2065126db5dbSVivek #define CFG_DP \ 2066126db5dbSVivek CFG(CFG_DP_HTT_PACKET_TYPE) \ 2067126db5dbSVivek CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \ 2068ba59a82eSSantosh Anbu CFG(CFG_DP_INT_BATCH_THRESHOLD_MON_DEST) \ 2069e5534b19SPavankumar Nandeshwar CFG(CFG_DP_INT_BATCH_THRESHOLD_PPE2TCL) \ 2070126db5dbSVivek CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \ 2071126db5dbSVivek CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \ 2072e5534b19SPavankumar Nandeshwar CFG(CFG_DP_INT_TIMER_THRESHOLD_PPE2TCL) \ 2073126db5dbSVivek CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \ 2074ba59a82eSSantosh Anbu CFG(CFG_DP_INT_TIMER_THRESHOLD_MON_DEST) \ 2075126db5dbSVivek CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \ 2076126db5dbSVivek CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \ 2077126db5dbSVivek CFG(CFG_DP_MAX_ALLOC_SIZE) \ 2078126db5dbSVivek CFG(CFG_DP_MAX_CLIENTS) \ 2079126db5dbSVivek CFG(CFG_DP_MAX_PEER_ID) \ 2080126db5dbSVivek CFG(CFG_DP_REO_DEST_RINGS) \ 20815f8681ffSNeha Bisht CFG(CFG_DP_TX_COMP_RINGS) \ 2082126db5dbSVivek CFG(CFG_DP_TCL_DATA_RINGS) \ 208395b9a6e6Sphadiman CFG(CFG_DP_NSS_REO_DEST_RINGS) \ 208495b9a6e6Sphadiman CFG(CFG_DP_NSS_TCL_DATA_RINGS) \ 2085126db5dbSVivek CFG(CFG_DP_TX_DESC) \ 2086ab649e06SHariharan Ramanathan CFG(CFG_DP_TX_DESC_POOL_3) \ 208788124ec9SSreeramya Soratkal CFG(CFG_DP_TX_SPL_DESC) \ 2088126db5dbSVivek CFG(CFG_DP_TX_EXT_DESC) \ 2089126db5dbSVivek CFG(CFG_DP_TX_EXT_DESC_POOLS) \ 2090126db5dbSVivek CFG(CFG_DP_PDEV_RX_RING) \ 2091126db5dbSVivek CFG(CFG_DP_PDEV_TX_RING) \ 2092126db5dbSVivek CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \ 2093126db5dbSVivek CFG(CFG_DP_TX_COMPL_RING_SIZE) \ 2094126db5dbSVivek CFG(CFG_DP_TX_RING_SIZE) \ 2095126db5dbSVivek CFG(CFG_DP_NSS_COMP_RING_SIZE) \ 2096126db5dbSVivek CFG(CFG_DP_PDEV_LMAC_RING) \ 209773465714SRuben Columbus CFG(CFG_DP_TIME_CONTROL_BP) \ 2098d8334769SRuben Columbus CFG(CFG_DP_QREF_CONTROL_SIZE) \ 2099126db5dbSVivek CFG(CFG_DP_BASE_HW_MAC_ID) \ 2100126db5dbSVivek CFG(CFG_DP_RX_HASH) \ 21013b770cc5SParikshit Gune CFG(CFG_DP_RX_RR) \ 2102126db5dbSVivek CFG(CFG_DP_TSO) \ 2103a4f6e173SAkshay Kosigi CFG(CFG_DP_LRO) \ 2104a4f6e173SAkshay Kosigi CFG(CFG_DP_SG) \ 2105a4f6e173SAkshay Kosigi CFG(CFG_DP_GRO) \ 2106f2ee56b2SYeshwanth Sriram Guntuka CFG(CFG_DP_TC_INGRESS_PRIO) \ 2107a4f6e173SAkshay Kosigi CFG(CFG_DP_OL_TX_CSUM) \ 2108a4f6e173SAkshay Kosigi CFG(CFG_DP_OL_RX_CSUM) \ 2109a4f6e173SAkshay Kosigi CFG(CFG_DP_RAWMODE) \ 2110a4f6e173SAkshay Kosigi CFG(CFG_DP_PEER_FLOW_CTRL) \ 2111126db5dbSVivek CFG(CFG_DP_NAPI) \ 2112126db5dbSVivek CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \ 211397200aabSMohit Khanna CFG(CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD) \ 211442a8d7efSMohit Khanna CFG(CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD) \ 2115126db5dbSVivek CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \ 2116126db5dbSVivek CFG(CFG_DP_WBM_RELEASE_RING) \ 2117f63aaef3SAnkit Kumar CFG(CFG_DP_TCL_CMD_CREDIT_RING) \ 2118126db5dbSVivek CFG(CFG_DP_TCL_STATUS_RING) \ 2119126db5dbSVivek CFG(CFG_DP_REO_REINJECT_RING) \ 2120126db5dbSVivek CFG(CFG_DP_RX_RELEASE_RING) \ 2121126db5dbSVivek CFG(CFG_DP_REO_EXCEPTION_RING) \ 21224fa2c22cSChaithanya Garrepalli CFG(CFG_DP_RX_DESTINATION_RING) \ 2123126db5dbSVivek CFG(CFG_DP_REO_CMD_RING) \ 2124126db5dbSVivek CFG(CFG_DP_REO_STATUS_RING) \ 2125126db5dbSVivek CFG(CFG_DP_RXDMA_BUF_RING) \ 2126126db5dbSVivek CFG(CFG_DP_RXDMA_REFILL_RING) \ 212764c4cb35SChaithanya Garrepalli CFG(CFG_DP_RXDMA_REFILL_LT_DISABLE) \ 212836ce817bSPrathyusha Guduri CFG(CFG_DP_TX_DESC_LIMIT_0) \ 212936ce817bSPrathyusha Guduri CFG(CFG_DP_TX_DESC_LIMIT_1) \ 213036ce817bSPrathyusha Guduri CFG(CFG_DP_TX_DESC_LIMIT_2) \ 2131aed67e19SPrathyusha Guduri CFG(CFG_DP_TX_DEVICE_LIMIT) \ 21326eba2a44SSreeramya Soratkal CFG(CFG_DP_TX_SPL_DEVICE_LIMIT) \ 2133abac9eedSPrathyusha Guduri CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \ 213430bc8285SNeha Bisht CFG(CFG_DP_TX_DESC_GLOBAL_COUNT) \ 213530bc8285SNeha Bisht CFG(CFG_DP_SPCL_TX_DESC_GLOBAL_COUNT) \ 2136126db5dbSVivek CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \ 2137126db5dbSVivek CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \ 2138126db5dbSVivek CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \ 2139126db5dbSVivek CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \ 214060ac9aa0Sjitiphil CFG(CFG_DP_RXDMA_ERR_DST_RING) \ 214103ba0f55SKrunal Soni CFG(CFG_DP_PER_PKT_LOGGING) \ 214260ac9aa0Sjitiphil CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \ 214360ac9aa0Sjitiphil CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \ 214460ac9aa0Sjitiphil CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \ 214560ac9aa0Sjitiphil CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \ 214660ac9aa0Sjitiphil CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \ 214760ac9aa0Sjitiphil CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \ 21489550273eSMainak Sen CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) \ 214976aa8d51SSumeet Rao CFG(CFG_DP_RX_SW_DESC_WEIGHT) \ 2150eeaa5b74SMainak Sen CFG(CFG_DP_RX_SW_DESC_NUM) \ 215176aa8d51SSumeet Rao CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE) \ 215276aa8d51SSumeet Rao CFG(CFG_DP_RX_FLOW_TAG_ENABLE) \ 215376aa8d51SSumeet Rao CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV) \ 2154b7a1c578SRuben Columbus CFG(CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE) \ 2155628c21c0SAlok Kumar CFG(CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD) \ 2156d501c326SManjunathappa Prakash CFG(CFG_DP_PKTLOG_BUFFER_SIZE) \ 2157e3876720SNeha Bisht CFG(CFG_DP_FULL_MON_MODE) \ 2158915f53b1SAniruddha Paul CFG(CFG_DP_REO_RINGS_MAP) \ 2159d315e2d2SManikanta Pubbisetty CFG(CFG_DP_PEER_EXT_STATS) \ 21609313b579SAmrit Sahai CFG(CFG_DP_PEER_JITTER_STATS) \ 2161bad38983SKenvish Butani CFG(CFG_DP_PEER_LINK_STATS) \ 2162db5374f0SYu Tian CFG(CFG_DP_RX_BUFF_POOL_ENABLE) \ 216347b1fe64SKarthik Kantamneni CFG(CFG_DP_RX_REFILL_BUFF_POOL_ENABLE) \ 2164fab64e0aSPrakash Manjunathappa CFG(CFG_DP_BUFS_PAGE_FRAG_ALLOCS) \ 2165db5374f0SYu Tian CFG(CFG_DP_RX_PENDING_HL_THRESHOLD) \ 216693aff9eeSManjunathappa Prakash CFG(CFG_DP_RX_PENDING_LO_THRESHOLD) \ 2167b257b236SSridhar Selvaraj CFG(CFG_DP_LEGACY_MODE_CSUM_DISABLE) \ 216802723d3bSRakesh Pillai CFG(CFG_DP_POLL_MODE_ENABLE) \ 2169aae959eeSAnkit Kumar CFG(CFG_DP_SWLM_ENABLE) \ 2170905d9e33SManikanta Pubbisetty CFG(CFG_DP_TX_PER_PKT_VDEV_ID_CHECK) \ 21713048f538SRadha Krishna Simha Jiguru CFG(CFG_DP_RX_FST_IN_CMEM) \ 21723048f538SRadha Krishna Simha Jiguru CFG(CFG_DP_RX_RADIO_0_DEFAULT_REO) \ 21733048f538SRadha Krishna Simha Jiguru CFG(CFG_DP_RX_RADIO_1_DEFAULT_REO) \ 217476fdb54eSYu Tian CFG(CFG_DP_RX_RADIO_2_DEFAULT_REO) \ 2175abb64b56SYu Tian CFG(CFG_DP_WOW_CHECK_RX_PENDING) \ 217640831551SJinwei Chen CFG(CFG_DP_HW_CC_ENABLE) \ 2177b5a3efabSYeshwanth Sriram Guntuka CFG(CFG_DP_DELAY_MON_REPLENISH) \ 2178df329ebbSNaga CFG(CFG_DP_TX_MONITOR_BUF_RING) \ 2179df329ebbSNaga CFG(CFG_DP_TX_MONITOR_DST_RING) \ 21801507b1cdSAmit Mehta CFG(CFG_DP_MPDU_RETRY_THRESHOLD_1) \ 21811507b1cdSAmit Mehta CFG(CFG_DP_MPDU_RETRY_THRESHOLD_2) \ 21820702aaf4SChaithanya Garrepalli CFG_DP_IPA_TX_RING_CFG \ 2183c811b9d5SPavankumar Nandeshwar CFG_DP_PPEDS_CONFIG \ 2184c42af1f6SChaithanya Garrepalli CFG_DP_IPA_TX_ALT_RING_CFG \ 2185f76548ddSHarsh Kumar Bijlani CFG_DP_MLO_CONFIG \ 2186e7074b08SSurya Prakash Raajen CFG_DP_INI_SECTION_PARAMS \ 2187986121ccSManoj Ekbote CFG_DP_VDEV_STATS_HW_OFFLOAD \ 2188204b7653STallapragada Kalyan CFG(CFG_DP_TX_CAPT_MAX_MEM_MB) \ 218918f8aed5Ssyed touqeer pasha CFG(CFG_DP_NAPI_SCALE_FACTOR) \ 21903b1f7cedSVivek CFG(CFG_DP_HOST_AST_DB_ENABLE) \ 21913bc97480SJeevan Kukkalli CFG_DP_SAWF_STATS_CONFIG \ 21927432a2e2SNandha Kishore Easwaran CFG(CFG_DP_HANDLE_INVALID_DECAP_TYPE_DISABLE) \ 2193b4f81eacSJinwei Chen CFG(CFG_DP_TXMON_SW_PEER_FILTERING) \ 2194c2c0f7f7SJinwei Chen CFG_TX_PKT_INSPECT_FOR_ILP_CFG \ 2195c2c0f7f7SJinwei Chen CFG(CFG_DP_POINTER_TIMER_THRESHOLD_RX) \ 21969de0de3fSSrinivas Girigowda CFG(CFG_DP_POINTER_NUM_THRESHOLD_RX) \ 2197fc126094SYu Tian CFG_DP_LOCAL_PKT_CAPTURE_CONFIG \ 2198748fe0b6SVenkateswara Naralasetty CFG(CFG_SPECIAL_FRAME_MSK) \ 21997f898dfcSShashikala Prabhu CFG(CFG_DP_SW2RXDMA_LINK_RING) \ 22006f8e9cffSnobelj CFG(CFG_DP_TX_CAPT_RADIO_0_RBM_ID) \ 22016f8e9cffSnobelj CFG(CFG_DP_TX_CAPT_RADIO_1_RBM_ID) \ 22026f8e9cffSnobelj CFG(CFG_DP_TX_CAPT_RADIO_2_RBM_ID) \ 22036f8e9cffSnobelj CFG(CFG_DP_TX_CAPT_RADIO_3_RBM_ID) \ 220470b5c653SRuben Columbus CFG_DP_UMAC_RESET_BUFFER_WINDOW_CFG \ 2205*37e5a76cSAman Mehta CFG(CFG_DP_RX_BUFFER_SIZE) \ 2206*37e5a76cSAman Mehta CFG(CFG_DP_STATS_AVG_RATE_FILTER) 2207126db5dbSVivek #endif /* _CFG_DP_H_ */ 2208