1 /* 2 * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * DOC: wlan_dfs_public_struct.h 22 * This file contains DFS data structures 23 */ 24 25 #ifndef __WLAN_DFS_PUBLIC_STRUCT_H_ 26 #define __WLAN_DFS_PUBLIC_STRUCT_H_ 27 #include <wlan_cmn.h> 28 /* TODO: This structure has many redundant variables, needs cleanup */ 29 /** 30 * struct radar_found_info - radar found info 31 * @pdev_id: pdev id. 32 * @detection_mode: 0 indicates RADAR detected, non-zero indicates debug mode. 33 * @freq_offset: frequency offset. 34 * @chan_width: channel width. 35 * @detector_id: detector id for full-offload. 36 * @segment_id: segment id (same as detector_id) for partial-offload. 37 * @timestamp: timestamp (Time when filter match is found in Firmware). 38 * @is_chirp: is chirp or not. 39 * @chan_freq: channel frequency (Primary channel frequency). 40 * @radar_freq: radar frequency (Is it same as '@chan_freq'?). 41 * @sidx: sidx value (same as freq_offset). 42 */ 43 struct radar_found_info { 44 uint32_t pdev_id; 45 uint32_t detection_mode; 46 int32_t freq_offset; 47 uint32_t chan_width; 48 uint32_t detector_id; 49 uint32_t segment_id; 50 uint32_t timestamp; 51 uint32_t is_chirp; 52 uint32_t chan_freq; 53 uint32_t radar_freq; 54 int32_t sidx; 55 }; 56 57 /** 58 * struct dfs_acs_info - acs info, ch range 59 * @acs_mode: to enable/disable acs 1/0. 60 * @chan_freq_list: channel frequency list 61 * @num_of_channel: number of channel in ACS channel list 62 */ 63 struct dfs_acs_info { 64 uint8_t acs_mode; 65 uint32_t *chan_freq_list; 66 uint8_t num_of_channel; 67 }; 68 69 /** 70 * struct radar_event_info - radar event info. 71 * @pulse_is_chirp: flag to indicate if this pulse is chirp. 72 * @pulse_center_freq: the center frequency of the radar pulse detected, KHz. 73 * @pulse_duration: the duaration of the pulse in us. 74 * @rssi: RSSI recorded in the ppdu. 75 * @pulse_detect_ts: timestamp indicates the time when DFS pulse is detected. 76 * @upload_fullts_low: low 32 tsf timestamp get from MAC tsf timer indicates 77 * the time that the radar event uploading to host. 78 * @upload_fullts_high: high 32 tsf timestamp get from MAC tsf timer indicates 79 * the time that the radar event uploading to host. 80 * @peak_sidx: index of peak magnitude bin (signed) 81 * @pdev_id: pdev_id for identifying the MAC. 82 * @delta_diff: Delta diff value. 83 * @delta_peak: Delta peak value. 84 * @psidx_diff: Psidx diff value. 85 * @is_psidx_diff_valid: Does fw send valid psidx diff. 86 */ 87 struct radar_event_info { 88 uint8_t pulse_is_chirp; 89 uint32_t pulse_center_freq; 90 uint32_t pulse_duration; 91 uint8_t rssi; 92 uint32_t pulse_detect_ts; 93 uint32_t upload_fullts_low; 94 uint32_t upload_fullts_high; 95 int32_t peak_sidx; 96 uint8_t pdev_id; 97 uint8_t delta_diff; 98 int8_t delta_peak; 99 int8_t psidx_diff; 100 int8_t is_psidx_diff_valid; 101 }; 102 103 /** 104 * struct dfs_user_config - user configuration required for for DFS. 105 * @dfs_is_phyerr_filter_offload: flag to indicate DFS phyerr filtering offload. 106 */ 107 struct dfs_user_config { 108 bool dfs_is_phyerr_filter_offload; 109 }; 110 111 /** 112 * struct dfs_radar_found_params - radar found parameters. 113 * @pri_min: Minimum PRI of detected radar pulse. 114 * @pri_max: Max PRI of detected radar pulse. 115 * @duration_min: Min duration of detected pulse in us. 116 * @duration_max: Max duration of detected pulse in us. 117 * @sidx_min: Min softare index of detected radar pulse. 118 * @sidx_max: Max software index of detected radar pulse. 119 */ 120 struct dfs_radar_found_params { 121 u_int32_t pri_min; 122 u_int32_t pri_max; 123 u_int32_t duration_min; 124 u_int32_t duration_max; 125 u_int32_t sidx_min; 126 u_int32_t sidx_max; 127 }; 128 129 /** 130 * enum adfs_ocac_mode - Various Off-Channel CAC modes. 131 * @QUICK_OCAC_MODE: Used for OCAC where the CAC timeout value is finite. 132 * This is also known as PreCAC. 133 * @EXTENSIVE_OCAC_MODE: Extensive OCAC. 134 * @QUICK_RCAC_MODE: Used for RollingCAC where the timeout value is assumed to 135 * be infinite by the Firmware code, that is, the FW has to 136 * be on the agile channel until host stop/aborts the agile 137 * CAC. 138 */ 139 enum adfs_ocac_mode { 140 QUICK_OCAC_MODE = 0, 141 EXTENSIVE_OCAC_MODE, 142 QUICK_RCAC_MODE, 143 }; 144 145 /** 146 * struct dfs_agile_cac_params - Agile DFS-CAC parameters. 147 * @precac_chan: Agile preCAC channel. 148 * @precac_center_freq_1: Agile preCAC channel frequency in MHz for 20/40/80/ 149 * 160 and left center frequency(5690MHz) for restricted 150 * 80p80. 151 * @precac_center_freq_2: Second segment Agile frequency if applicable. 0 for 152 * 20/40/80/160 and right center frequency(5775MHz) for 153 * restricted 80p80. 154 * @precac_chwidth: Agile preCAC channel width. 155 * @min_precac_timeout: Minimum agile preCAC timeout. 156 * @max_precac_timeout: Maximum agile preCAC timeout. 157 * @ocac_mode: Off-Channel CAC mode. 158 */ 159 struct dfs_agile_cac_params { 160 uint8_t precac_chan; 161 uint16_t precac_center_freq_1; 162 uint16_t precac_center_freq_2; 163 enum phy_ch_width precac_chwidth; 164 uint32_t min_precac_timeout; 165 uint32_t max_precac_timeout; 166 enum adfs_ocac_mode ocac_mode; 167 }; 168 169 /* The first DFS channel number is 52 and the last DFS channel number is 161(in 170 * case of ETSI EN302502). So, the array size is taken as (161 - 52) / 4 ~= 30. 171 */ 172 #define NUM_DFS_CHANS 30 173 174 /** 175 * enum channel_dfs_state - DFS channel states. 176 * @CH_DFS_S_INVALID: The DFS state for invalid channel numbers that are not 177 * part of the radio's channel list. 178 * @CH_DFS_S_CAC_REQ: Indicates that the CAC/Off-channel CAC has to performed 179 * before Tx on the DFS channel. 180 * @CH_DFS_S_CAC_STARTED: Indicates that the CAC has been started for the DFS 181 * channel. 182 * @CH_DFS_S_CAC_COMPLETED: Indicates that the CAC has been completed for the 183 * DFS channel. 184 * @CH_DFS_S_NOL: Indicates that the DFS channel is in NOL. 185 * @CH_DFS_S_PRECAC_STARTED: Indicates that the PreCAC has been started for the 186 * DFS channel. 187 * @CH_DFS_S_PRECAC_COMPLETED: Indicates that the PreCAC has been completed for 188 * the DFS channel. 189 */ 190 enum channel_dfs_state { 191 CH_DFS_S_INVALID, 192 CH_DFS_S_CAC_REQ, 193 CH_DFS_S_CAC_STARTED, 194 CH_DFS_S_CAC_COMPLETED, 195 CH_DFS_S_NOL, 196 CH_DFS_S_PRECAC_STARTED, 197 CH_DFS_S_PRECAC_COMPLETED, 198 }; 199 #endif 200