1 /* 2 * Copyright (c) 2015,2017-2019 The Linux Foundation. All rights reserved. 3 * 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _SPECTRAL_SIM_INTERNAL_H_ 21 #define _SPECTRAL_SIM_INTERNAL_H_ 22 23 #ifdef QCA_SUPPORT_SPECTRAL_SIMULATION 24 #include "target_if_spectral.h" 25 26 /* #define SPECTRAL_SIM_DUMP_PARAM_DATA 1 */ 27 /** 28 * struct spectralsim_report - Linked list node of spectal simulation report 29 * Spectral report data instance. Usable in a linked list. 30 * In the case of Direct Attach chipsets, one instance should correspond to 31 * one PHY Data Error frame received from the HW. 32 * XXX Direct Attach support to be implemented if needed. Any modifications 33 * required here can be made at the time of implementation. 34 * In the case of 802.11ac offload chipsets, one instance should correspond to 35 * one report received from HW, inclusive of all TLVs. 36 * 37 * @rfqual_info: RF measurement information 38 * @chan_info: Channel information 39 * @datasize: Length of report data 40 * @data: Pointer to report data 41 * @next: Pointer to next node in the struct spectralsim_report 42 */ 43 struct spectralsim_report { 44 /* 11ac onwards only */ 45 struct target_if_spectral_rfqual_info rfqual_info; 46 /* 11ac onwards only */ 47 struct target_if_spectral_chan_info chan_info; 48 uint32_t datasize; 49 uint8_t *data; 50 struct spectralsim_report *next; 51 }; 52 53 /** 54 * struct spectralsim_reportset - Set of Spectral report data instances 55 * corresponding to one particular configuration. Usable in a linked list. 56 * @config: Spectral config parameters 57 * @headreport: Pointer to the linked list of struct spectralsim_report 58 * @curr_report: Pointer to current node in the linked list of 59 * struct spectralsim_report 60 * @next: Pointer to next node in the struct spectralsim_reportset 61 */ 62 struct spectralsim_reportset { 63 struct spectral_config config; 64 struct spectralsim_report *headreport; 65 struct spectralsim_report *curr_report; 66 struct spectralsim_reportset *next; 67 }; 68 69 /* 70 * struct spectralsim_context - Main structure for Spectral simulation. 71 * All data and controls get linked here. 72 * 73 * For each width (20/40/80/160/80+80), we will have a linked list of 74 * spectralsim_reportset nodes. Each struct spectralsim_reportset will have a 75 * linked list of struct spectralsim_report nodes. When the user requests for a 76 * given PHY mode and Spectral configuration, we find the appropriate 77 * spectralsim_reportset, and then serve struct spectralsim_report instances 78 * from the linked list. If required report count is higher than size of linked 79 * list (or infinite), we repeatedly cycle through the linked list. There can 80 * be more elaborate data structures devised taking care of a large number of 81 * possibilities, but we stick to a simple scheme given limited simulation 82 * needs. 83 * 84 * @bw20_headreportset : Linked list of spectralsim_reportset for 20MHz width 85 * @bw20_headreportset : Linked list of spectralsim_reportset for 40MHz width 86 * @bw20_headreportset : Linked list of spectralsim_reportset for 80MHz width 87 * @bw20_headreportset : Linked list of spectralsim_reportset for 160MHz width 88 * @bw20_headreportset : Linked list of spectralsim_reportset for 80_80MHz width 89 * @curr_reportset : Pointer to current node in the linked list of 90 * struct spectralsim_reportset 91 * @is_enabled : Whether the simulated spectral scan is set as enabled 92 * @is_active : Whether the simulated spectral scan is set as active 93 * @ssim_pherrdelivery_timer : Simulated Phyerr delivery timer 94 * @ssim_starting_tsf64 : Starting 64-bit TSF value for spectral simulation 95 * @ssim_period_ms : Simulated Phyerr delivery period in ms 96 * @ssim_count : Number of simulated spectral samples to deliver 97 * @populate_report_static : Pointer to function to populate static spectral 98 * report data 99 */ 100 struct spectralsim_context { 101 struct spectralsim_reportset *bw20_headreportset; 102 struct spectralsim_reportset *bw40_headreportset; 103 struct spectralsim_reportset *bw80_headreportset; 104 struct spectralsim_reportset *bw160_headreportset; 105 struct spectralsim_reportset *bw80_80_headreportset; 106 107 struct spectralsim_reportset *curr_reportset; 108 bool is_enabled; 109 bool is_active; 110 111 qdf_timer_t ssim_pherrdelivery_timer; 112 uint64_t ssim_starting_tsf64; 113 uint32_t ssim_period_ms; /* TODO: Support in microseconds */ 114 uint32_t ssim_count; 115 int (*populate_report_static)(struct spectralsim_report *report, 116 enum phy_ch_width width, bool is_80_80); 117 }; 118 119 /* Helper Macros */ 120 121 /* Allocate and populate reportset for a single configuration */ 122 #define SPECTRAL_SIM_REPORTSET_ALLOCPOPL_SINGLE(simctx, reportset, width, \ 123 is_80_80) \ 124 { \ 125 (reportset) = (struct spectralsim_reportset *) \ 126 qdf_mem_malloc(sizeof(struct spectralsim_reportset)); \ 127 \ 128 if ((reportset) == NULL) { \ 129 target_if_depopulate_simdata((simctx)); \ 130 return -EPERM; \ 131 } \ 132 \ 133 qdf_mem_zero((reportset), sizeof(struct spectralsim_reportset)); \ 134 \ 135 if (target_if_populate_reportset_static( \ 136 (simctx), (reportset), (width), (is_80_80)) != 0) { \ 137 target_if_depopulate_simdata((simctx)); \ 138 return -EPERM; \ 139 } \ 140 \ 141 (reportset)->next = NULL; \ 142 } 143 144 /* Depopulate and free list of report sets */ 145 #define SPECTRAL_SIM_REPORTSET_DEPOPLFREE_LIST(reportset) \ 146 { \ 147 struct spectralsim_reportset *curr_reportset = NULL; \ 148 struct spectralsim_reportset *next_reportset = NULL; \ 149 \ 150 curr_reportset = (reportset); \ 151 \ 152 while (curr_reportset) { \ 153 next_reportset = curr_reportset->next; \ 154 target_if_depopulate_reportset(curr_reportset); \ 155 qdf_mem_free(curr_reportset); \ 156 curr_reportset = next_reportset; \ 157 } \ 158 \ 159 (reportset) = NULL; \ 160 } 161 162 /* Values for static population */ 163 164 /* 20 MHz */ 165 166 /* Report data for 20MHz bandwidth for generation 2 chipsets */ 167 static uint8_t reportdata_20_gen2[] = { 168 #ifdef BIG_ENDIAN_HOST 169 0xbb, /* Signature */ 170 0xfb, /* Tag */ 171 0x00, /* Size */ 172 0x54, 173 0x2e, 0x60, 0x0f, 0xe8, /* FFT Summary A */ 174 0x00, 0x00, 0x04, 0x00, /* FFT Summary B */ 175 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 176 #else 177 0x54, /* Length */ 178 0x00, 179 0xfb, /* Tag */ 180 0xbb, /* Signature */ 181 0xe8, 0x0f, 0x60, 0x2e, /* FFT Summary A */ 182 0x00, 0x04, 0x00, 0x00, /* FFT Summary B */ 183 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 184 #endif /* BIG_ENDIAN_HOST */ 185 /* FFT Data */ 186 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 1, 2, 0, 1, 1, 1, 0, 187 0, 1, 1, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 188 1, 1, 0, 2, 1, 2, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 189 }; 190 191 /* Report data for 20MHz bandwidth for generation 3 chipsets */ 192 static uint8_t reportdata_20_gen3[] = { 193 #ifdef BIG_ENDIAN_HOST 194 0x12, 0x34, 0x56, 0x78, /* fft_timestamp */ 195 0xfa, /* fft_hdr_sig */ 196 0x03, /* fft_hdr_tag */ 197 0x00, /* fft_hdr_length */ 198 0x14, 199 0x0f, 0xf6, 0x00, 0xe0, 200 0x00, 0x00, 0x2f, 0xba, 201 0x20, 0xb4, 0x2c, 0x01, 202 0x00, 0x00, 0x00, 0x00, /* reserved */ 203 #else 204 0x78, 0x56, 0x34, 0x12, /* fft_timestamp */ 205 0x14, /* fft_hdr_length */ 206 0x00, 207 0x03, /* fft_hdr_tag */ 208 0xfa, /* fft_hdr_sig */ 209 0xe0, 0x00, 0xf6, 0x0f, 210 0xba, 0x2f, 0x00, 0x00, 211 0x01, 0x2c, 0xb4, 0x20, 212 0x00, 0x00, 0x00, 0x00, /* reserved */ 213 #endif /* BIG_ENDIAN_HOST */ 214 /* FFT Data */ 215 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 1, 2, 0, 1, 1, 1, 0, 216 0, 1, 1, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 217 1, 1, 0, 2, 1, 2, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 218 }; 219 220 /* RF measurement information for 20 MHz bandwidth */ 221 static struct target_if_spectral_rfqual_info rfqual_info_20 = { 222 .rssi_comb = 1, 223 224 .pc_rssi_info[0].rssi_pri20 = 1, 225 .pc_rssi_info[0].rssi_sec20 = 128, 226 .pc_rssi_info[0].rssi_sec40 = 128, 227 .pc_rssi_info[0].rssi_sec80 = 128, 228 229 .pc_rssi_info[1].rssi_pri20 = 128, 230 .pc_rssi_info[1].rssi_sec20 = 128, 231 .pc_rssi_info[1].rssi_sec40 = 128, 232 .pc_rssi_info[1].rssi_sec80 = 128, 233 234 .pc_rssi_info[2].rssi_pri20 = 128, 235 .pc_rssi_info[2].rssi_sec20 = 128, 236 .pc_rssi_info[2].rssi_sec40 = 128, 237 .pc_rssi_info[2].rssi_sec80 = 128, 238 239 .pc_rssi_info[3].rssi_pri20 = 128, 240 .pc_rssi_info[3].rssi_sec20 = 128, 241 .pc_rssi_info[3].rssi_sec40 = 128, 242 .pc_rssi_info[3].rssi_sec80 = 128, 243 244 .noise_floor[0] = -90, 245 .noise_floor[1] = -90, 246 .noise_floor[2] = -90, 247 .noise_floor[3] = -90, 248 }; 249 250 /* Channel information for 20 MHz bandwidth */ 251 static struct target_if_spectral_chan_info chan_info_20 = { 252 .center_freq1 = 5180, 253 .center_freq2 = 0, 254 .chan_width = 20, 255 }; 256 257 /* Spectral config parameters for 20 MHz bandwidth */ 258 static struct spectral_config config_20_1 = { 259 .ss_fft_period = 1, 260 .ss_period = 35, 261 .ss_count = 0, 262 .ss_short_report = 1, 263 .radar_bin_thresh_sel = 0, 264 .ss_spectral_pri = 1, 265 .ss_fft_size = 7, 266 .ss_gc_ena = 1, 267 .ss_restart_ena = 0, 268 .ss_noise_floor_ref = 65440, 269 .ss_init_delay = 80, 270 .ss_nb_tone_thr = 12, 271 .ss_str_bin_thr = 8, 272 .ss_wb_rpt_mode = 0, 273 .ss_rssi_rpt_mode = 0, 274 .ss_rssi_thr = 240, 275 .ss_pwr_format = 0, 276 .ss_rpt_mode = 2, 277 .ss_bin_scale = 1, 278 .ss_dbm_adj = 1, 279 .ss_chn_mask = 1, 280 .ss_nf_cal[0] = 0, 281 .ss_nf_cal[1] = 0, 282 .ss_nf_cal[2] = 0, 283 .ss_nf_cal[3] = 0, 284 .ss_nf_cal[4] = 0, 285 .ss_nf_cal[5] = 0, 286 .ss_nf_pwr[0] = 0, 287 .ss_nf_pwr[1] = 0, 288 .ss_nf_pwr[2] = 0, 289 .ss_nf_pwr[3] = 0, 290 .ss_nf_pwr[4] = 0, 291 .ss_nf_pwr[5] = 0, 292 .ss_nf_temp_data = 0, 293 }; 294 295 /* 40 MHz */ 296 297 /* Report data for 40MHz bandwidth for generation 2 chipsets */ 298 static uint8_t reportdata_40_gen2[] = { 299 #ifdef BIG_ENDIAN_HOST 300 0xbb, /* Signature */ 301 0xfb, /* Tag */ 302 0x00, /* Size */ 303 0x94, 304 0x2e, 0x61, 0x0f, 0x80, /* FFT Summary A */ 305 0x00, 0x00, 0x06, 0x00, /* FFT Summary B */ 306 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 307 #else 308 0x94, /* Length */ 309 0x00, 310 0xfb, /* Tag */ 311 0xbb, /* Signature */ 312 0x80, 0x0f, 0x61, 0x2e, /* FFT Summary A */ 313 0x00, 0x06, 0x00, 0x00, /* FFT Summary B */ 314 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 315 #endif /* BIG_ENDIAN_HOST */ 316 /* FFT Data */ 317 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 318 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 319 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 1, 320 0, 0, 0, 1, 0, 0, 0, 0, 2, 1, 0, 2, 1, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 321 1, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 1, 0, 322 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 323 }; 324 325 /* Report data for 40MHz bandwidth for generation 3 chipsets */ 326 static uint8_t reportdata_40_gen3[] = { 327 #ifdef BIG_ENDIAN_HOST 328 0x12, 0x34, 0x56, 0x78, /* fft_timestamp */ 329 0xfa, /* fft_hdr_sig */ 330 0x03, /* fft_hdr_tag */ 331 0x00, /* fft_hdr_length */ 332 0x24, 333 0x0f, 0xf6, 0x00, 0xe0, 334 0x00, 0x00, 0x2f, 0xba, 335 0x20, 0xb4, 0x2c, 0x01, 336 0x00, 0x00, 0x00, 0x00, /* reserved */ 337 #else 338 0x78, 0x56, 0x34, 0x12, /* fft_timestamp */ 339 0x24, /* fft_hdr_length */ 340 0x00, 341 0x03, /* fft_hdr_tag */ 342 0xfa, /* fft_hdr_sig */ 343 0xe0, 0x00, 0xf6, 0x0f, 344 0xba, 0x2f, 0x00, 0x00, 345 0x01, 0x2c, 0xb4, 0x20, 346 0x00, 0x00, 0x00, 0x00, /* reserved */ 347 #endif /* BIG_ENDIAN_HOST */ 348 /* FFT Data */ 349 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 350 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 351 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 1, 352 0, 0, 0, 1, 0, 0, 0, 0, 2, 1, 0, 2, 1, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 353 1, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 1, 0, 354 0, 0, 0, 1, 0, 0, 0, 0, 355 }; 356 357 /* RF measurement information for 40 MHz bandwidth */ 358 static struct target_if_spectral_rfqual_info rfqual_info_40 = { 359 .rssi_comb = 1, 360 361 .pc_rssi_info[0].rssi_pri20 = 1, 362 .pc_rssi_info[0].rssi_sec20 = 2, 363 .pc_rssi_info[0].rssi_sec40 = 128, 364 .pc_rssi_info[0].rssi_sec80 = 128, 365 366 .pc_rssi_info[1].rssi_pri20 = 128, 367 .pc_rssi_info[1].rssi_sec20 = 128, 368 .pc_rssi_info[1].rssi_sec40 = 128, 369 .pc_rssi_info[1].rssi_sec80 = 128, 370 371 .pc_rssi_info[2].rssi_pri20 = 128, 372 .pc_rssi_info[2].rssi_sec20 = 128, 373 .pc_rssi_info[2].rssi_sec40 = 128, 374 .pc_rssi_info[2].rssi_sec80 = 128, 375 376 .pc_rssi_info[3].rssi_pri20 = 128, 377 .pc_rssi_info[3].rssi_sec20 = 128, 378 .pc_rssi_info[3].rssi_sec40 = 128, 379 .pc_rssi_info[3].rssi_sec80 = 128, 380 381 .noise_floor[0] = -90, 382 .noise_floor[1] = -90, 383 .noise_floor[2] = -90, 384 .noise_floor[3] = -90, 385 }; 386 387 /* Channel information for 40 MHz bandwidth */ 388 static struct target_if_spectral_chan_info chan_info_40 = { 389 .center_freq1 = 5180, 390 .center_freq2 = 0, 391 .chan_width = 40, 392 }; 393 394 /* Spectral config parameters for 40 MHz bandwidth */ 395 static struct spectral_config config_40_1 = { 396 .ss_fft_period = 1, 397 .ss_period = 35, 398 .ss_count = 0, 399 .ss_short_report = 1, 400 .radar_bin_thresh_sel = 0, 401 .ss_spectral_pri = 1, 402 .ss_fft_size = 8, 403 .ss_gc_ena = 1, 404 .ss_restart_ena = 0, 405 .ss_noise_floor_ref = 65440, 406 .ss_init_delay = 80, 407 .ss_nb_tone_thr = 12, 408 .ss_str_bin_thr = 8, 409 .ss_wb_rpt_mode = 0, 410 .ss_rssi_rpt_mode = 0, 411 .ss_rssi_thr = 240, 412 .ss_pwr_format = 0, 413 .ss_rpt_mode = 2, 414 .ss_bin_scale = 1, 415 .ss_dbm_adj = 1, 416 .ss_chn_mask = 1, 417 .ss_nf_cal[0] = 0, 418 .ss_nf_cal[1] = 0, 419 .ss_nf_cal[2] = 0, 420 .ss_nf_cal[3] = 0, 421 .ss_nf_cal[4] = 0, 422 .ss_nf_cal[5] = 0, 423 .ss_nf_pwr[0] = 0, 424 .ss_nf_pwr[1] = 0, 425 .ss_nf_pwr[2] = 0, 426 .ss_nf_pwr[3] = 0, 427 .ss_nf_pwr[4] = 0, 428 .ss_nf_pwr[5] = 0, 429 .ss_nf_temp_data = 0, 430 }; 431 432 /* 80 MHz */ 433 434 /* Report data for 80MHz bandwidth for generation 2 chipsets */ 435 static uint8_t reportdata_80_gen2[] = { 436 #ifdef BIG_ENDIAN_HOST 437 0xbb, /* Signature */ 438 0xfb, /* Tag */ 439 0x01, /* Size */ 440 0x14, 441 0x19, 0xeb, 0x80, 0x40, /* FFT Summary A */ 442 0x00, 0x00, 0x10, 0x00, /* FFT Summary B */ 443 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 444 #else 445 0x14, /* Length */ 446 0x01, 447 0xfb, /* Tag */ 448 0xbb, /* Signature */ 449 0x40, 0x80, 0xeb, 0x19, /* FFT Summary A */ 450 0x00, 0x10, 0x00, 0x00, /* FFT Summary B */ 451 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 452 #endif /* BIG_ENDIAN_HOST */ 453 /* FFT Data */ 454 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 455 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 456 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 457 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 458 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 459 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 460 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 462 0, 0, 0, 1, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 463 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 465 }; 466 467 /* Report data for 80MHz bandwidth for generation 3 chipsets */ 468 static uint8_t reportdata_80_gen3[] = { 469 #ifdef BIG_ENDIAN_HOST 470 0x12, 0x34, 0x56, 0x78, /* fft_timestamp */ 471 0xfa, /* fft_hdr_sig */ 472 0x03, /* fft_hdr_tag */ 473 0x00, /* fft_hdr_length */ 474 0x44, 475 0x0f, 0xf6, 0x00, 0xe0, 476 0x00, 0x00, 0x2f, 0xba, 477 0x20, 0xb4, 0x2c, 0x01, 478 0x00, 0x00, 0x00, 0x00, /* reserved */ 479 #else 480 0x78, 0x56, 0x34, 0x12, /* fft_timestamp */ 481 0x44, /* fft_hdr_length */ 482 0x00, 483 0x03, /* fft_hdr_tag */ 484 0xfa, /* fft_hdr_sig */ 485 0xe0, 0x00, 0xf6, 0x0f, 486 0xba, 0x2f, 0x00, 0x00, 487 0x01, 0x2c, 0xb4, 0x20, 488 0x00, 0x00, 0x00, 0x00, /* reserved */ 489 #endif /* BIG_ENDIAN_HOST */ 490 /* FFT Data */ 491 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 492 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 493 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 494 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 495 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 496 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 497 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 498 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 499 0, 0, 0, 1, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 500 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 501 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 502 }; 503 504 /* RF measurement information for 80 MHz bandwidth */ 505 static struct target_if_spectral_rfqual_info rfqual_info_80 = { 506 .rssi_comb = 16, 507 508 .pc_rssi_info[0].rssi_pri20 = 16, 509 .pc_rssi_info[0].rssi_sec20 = 17, 510 .pc_rssi_info[0].rssi_sec40 = 0, 511 .pc_rssi_info[0].rssi_sec80 = 128, 512 513 .pc_rssi_info[1].rssi_pri20 = 128, 514 .pc_rssi_info[1].rssi_sec20 = 128, 515 .pc_rssi_info[1].rssi_sec40 = 128, 516 .pc_rssi_info[1].rssi_sec80 = 128, 517 518 .pc_rssi_info[2].rssi_pri20 = 128, 519 .pc_rssi_info[2].rssi_sec20 = 128, 520 .pc_rssi_info[2].rssi_sec40 = 128, 521 .pc_rssi_info[2].rssi_sec80 = 128, 522 523 .pc_rssi_info[3].rssi_pri20 = 128, 524 .pc_rssi_info[3].rssi_sec20 = 128, 525 .pc_rssi_info[3].rssi_sec40 = 128, 526 .pc_rssi_info[3].rssi_sec80 = 128, 527 528 .noise_floor[0] = -90, 529 .noise_floor[1] = -90, 530 .noise_floor[2] = -90, 531 .noise_floor[3] = -90, 532 }; 533 534 /* Channel information for 80 MHz bandwidth */ 535 static struct target_if_spectral_chan_info chan_info_80 = { 536 .center_freq1 = 5210, 537 .center_freq2 = 0, 538 .chan_width = 80, 539 }; 540 541 /* Spectral config parameters for 80 MHz bandwidth */ 542 static struct spectral_config config_80_1 = { 543 .ss_fft_period = 1, 544 .ss_period = 35, 545 .ss_count = 0, 546 .ss_short_report = 1, 547 .radar_bin_thresh_sel = 0, 548 .ss_spectral_pri = 1, 549 .ss_fft_size = 9, 550 .ss_gc_ena = 1, 551 .ss_restart_ena = 0, 552 .ss_noise_floor_ref = 65440, 553 .ss_init_delay = 80, 554 .ss_nb_tone_thr = 12, 555 .ss_str_bin_thr = 8, 556 .ss_wb_rpt_mode = 0, 557 .ss_rssi_rpt_mode = 0, 558 .ss_rssi_thr = 240, 559 .ss_pwr_format = 0, 560 .ss_rpt_mode = 2, 561 .ss_bin_scale = 1, 562 .ss_dbm_adj = 1, 563 .ss_chn_mask = 1, 564 .ss_nf_cal[0] = 0, 565 .ss_nf_cal[1] = 0, 566 .ss_nf_cal[2] = 0, 567 .ss_nf_cal[3] = 0, 568 .ss_nf_cal[4] = 0, 569 .ss_nf_cal[5] = 0, 570 .ss_nf_pwr[0] = 0, 571 .ss_nf_pwr[1] = 0, 572 .ss_nf_pwr[2] = 0, 573 .ss_nf_pwr[3] = 0, 574 .ss_nf_pwr[4] = 0, 575 .ss_nf_pwr[5] = 0, 576 .ss_nf_temp_data = 0, 577 }; 578 579 /* 160 MHz */ 580 581 /* Report data for 160MHz bandwidth for generation 2 chipsets */ 582 static uint8_t reportdata_160_gen2[] = { 583 /* Segment 1 */ 584 #ifdef BIG_ENDIAN_HOST 585 0xbb, /* Signature */ 586 0xfb, /* Tag */ 587 0x01, /* Size */ 588 0x14, 589 0x23, 0x66, 0x00, 0x40, /* FFT Summary A */ 590 0x5c, 0x5c, 0x78, 0x00, /* FFT Summary B */ 591 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 592 #else 593 0x14, /* Length */ 594 0x01, 595 0xfb, /* Tag */ 596 0xbb, /* Signature */ 597 0x40, 0x00, 0x66, 0x23, /* FFT Summary A */ 598 0x00, 0x78, 0x5c, 0x5c, /* FFT Summary B */ 599 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 600 #endif /* BIG_ENDIAN_HOST */ 601 /* FFT Data */ 602 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 603 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 604 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 605 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 606 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 607 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 608 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 609 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 610 1, 1, 2, 4, 60, 4, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 611 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 612 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 613 0, 614 615 /* Segment 2 */ 616 #ifdef BIG_ENDIAN_HOST 617 0xbb, /* Signature */ 618 0xfb, /* Tag */ 619 0x01, /* Size */ 620 0x14, 621 0x23, 0x66, 0x00, 0x40, /* FFT Summary A */ 622 0x5c, 0x5c, 0x78, 0x00, /* FFT Summary B */ 623 0x00, 0x00, 0x00, 0x01, /* Segment ID */ 624 #else 625 0x14, /* Length */ 626 0x01, 627 0xfb, /* Tag */ 628 0xbb, /* Signature */ 629 0x40, 0x00, 0x66, 0x23, /* FFT Summary A */ 630 0x00, 0x78, 0x5c, 0x5c, /* FFT Summary B */ 631 0x01, 0x00, 0x00, 0x00, /* Segment ID */ 632 #endif /* BIG_ENDIAN_HOST */ 633 /* FFT Data */ 634 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 635 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 636 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 637 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 638 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 639 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 640 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 641 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 642 1, 1, 2, 4, 60, 4, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 643 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 644 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 645 0, 646 }; 647 648 /* Report data for 160MHz bandwidth for generation 3 chipsets */ 649 static uint8_t reportdata_160_gen3[] = { 650 /* Segment 1 */ 651 #ifdef BIG_ENDIAN_HOST 652 0x12, 0x34, 0x56, 0x78, /* fft_timestamp */ 653 0xfa, /* fft_hdr_sig */ 654 0x03, /* fft_hdr_tag */ 655 0x00, /* fft_hdr_length */ 656 0x44, 657 0x0f, 0xf6, 0x00, 0xe0, 658 0x00, 0x00, 0x2f, 0xba, 659 0x20, 0xb4, 0x2c, 0x01, 660 0x00, 0x00, 0x00, 0x00, /* reserved */ 661 #else 662 0x78, 0x56, 0x34, 0x12, /* fft_timestamp */ 663 0x44, /* fft_hdr_length */ 664 0x00, 665 0x03, /* fft_hdr_tag */ 666 0xfa, /* fft_hdr_sig */ 667 0xe0, 0x00, 0xf6, 0x0f, 668 0xba, 0x2f, 0x00, 0x00, 669 0x01, 0x2c, 0xb4, 0x20, 670 0x00, 0x00, 0x00, 0x00, /* reserved */ 671 #endif /* BIG_ENDIAN_HOST */ 672 /* FFT Data */ 673 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 674 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 675 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 676 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 677 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 678 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 679 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 680 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 681 1, 1, 2, 4, 60, 4, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 682 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 683 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 684 685 /* Segment 2 */ 686 #ifdef BIG_ENDIAN_HOST 687 0x12, 0x34, 0x56, 0x78, /* fft_timestamp */ 688 0xfa, /* fft_hdr_sig */ 689 0x03, /* fft_hdr_tag */ 690 0x00, /* fft_hdr_length */ 691 0x44, 692 0x0f, 0xf6, 0x00, 0xe1, 693 0x00, 0x00, 0x2f, 0xba, 694 0x20, 0xb4, 0x2c, 0x01, 695 0x00, 0x00, 0x00, 0x00, /* reserved */ 696 #else 697 0x78, 0x56, 0x34, 0x12, /* fft_timestamp */ 698 0x44, /* fft_hdr_length */ 699 0x00, 700 0x03, /* fft_hdr_tag */ 701 0xfa, /* fft_hdr_sig */ 702 0xe1, 0x00, 0xf6, 0x0f, 703 0xba, 0x2f, 0x00, 0x00, 704 0x01, 0x2c, 0xb4, 0x20, 705 0x00, 0x00, 0x00, 0x00, /* reserved */ 706 #endif /* BIG_ENDIAN_HOST */ 707 /* FFT Data */ 708 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 709 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 710 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 711 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 712 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 713 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 714 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 715 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 716 1, 1, 2, 4, 60, 4, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 717 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 718 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 719 }; 720 721 /* RF measurement information for 160 MHz bandwidth */ 722 static struct target_if_spectral_rfqual_info rfqual_info_160 = { 723 .rssi_comb = 3, 724 725 .pc_rssi_info[0].rssi_pri20 = 3, 726 .pc_rssi_info[0].rssi_sec20 = 12, 727 .pc_rssi_info[0].rssi_sec40 = 41, 728 .pc_rssi_info[0].rssi_sec80 = 128, 729 730 .pc_rssi_info[1].rssi_pri20 = 128, 731 .pc_rssi_info[1].rssi_sec20 = 128, 732 .pc_rssi_info[1].rssi_sec40 = 128, 733 .pc_rssi_info[1].rssi_sec80 = 128, 734 735 .pc_rssi_info[2].rssi_pri20 = 128, 736 .pc_rssi_info[2].rssi_sec20 = 128, 737 .pc_rssi_info[2].rssi_sec40 = 128, 738 .pc_rssi_info[2].rssi_sec80 = 128, 739 740 .pc_rssi_info[3].rssi_pri20 = 128, 741 .pc_rssi_info[3].rssi_sec20 = 128, 742 .pc_rssi_info[3].rssi_sec40 = 128, 743 .pc_rssi_info[3].rssi_sec80 = 128, 744 745 .noise_floor[0] = -90, 746 .noise_floor[1] = -90, 747 .noise_floor[2] = -90, 748 .noise_floor[3] = -90, 749 }; 750 751 /* Channel information for 160 MHz bandwidth */ 752 static struct target_if_spectral_chan_info chan_info_160 = { 753 .center_freq1 = 5250, 754 .center_freq2 = 0, 755 .chan_width = 160, 756 }; 757 758 /* Spectral config parameters for 160 MHz bandwidth */ 759 static struct spectral_config config_160_1 = { 760 .ss_fft_period = 1, 761 .ss_period = 35, 762 .ss_count = 0, 763 .ss_short_report = 1, 764 .radar_bin_thresh_sel = 0, 765 .ss_spectral_pri = 1, 766 .ss_fft_size = 9, 767 .ss_gc_ena = 1, 768 .ss_restart_ena = 0, 769 .ss_noise_floor_ref = 65440, 770 .ss_init_delay = 80, 771 .ss_nb_tone_thr = 12, 772 .ss_str_bin_thr = 8, 773 .ss_wb_rpt_mode = 0, 774 .ss_rssi_rpt_mode = 0, 775 .ss_rssi_thr = 240, 776 .ss_pwr_format = 0, 777 .ss_rpt_mode = 2, 778 .ss_bin_scale = 1, 779 .ss_dbm_adj = 1, 780 .ss_chn_mask = 1, 781 .ss_nf_cal[0] = 0, 782 .ss_nf_cal[1] = 0, 783 .ss_nf_cal[2] = 0, 784 .ss_nf_cal[3] = 0, 785 .ss_nf_cal[4] = 0, 786 .ss_nf_cal[5] = 0, 787 .ss_nf_pwr[0] = 0, 788 .ss_nf_pwr[1] = 0, 789 .ss_nf_pwr[2] = 0, 790 .ss_nf_pwr[3] = 0, 791 .ss_nf_pwr[4] = 0, 792 .ss_nf_pwr[5] = 0, 793 .ss_nf_temp_data = 0, 794 }; 795 796 /* 80+80 MHz */ 797 798 /* Report data for 80_80MHz bandwidth for generation 2 chipsets */ 799 static uint8_t reportdata_80_80_gen2[] = { 800 /* Segment 1 */ 801 #ifdef BIG_ENDIAN_HOST 802 0xbb, /* Signature */ 803 0xfb, /* Tag */ 804 0x01, /* Size */ 805 0x14, 806 0x23, 0x66, 0x00, 0x40, /* FFT Summary A */ 807 0x64, 0x64, 0x89, 0x00, /* FFT Summary B */ 808 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 809 #else 810 0x14, /* Length */ 811 0x01, 812 0xfb, /* Tag */ 813 0xbb, /* Signature */ 814 0x40, 0x00, 0x66, 0x23, /* FFT Summary A */ 815 0x00, 0x89, 0x64, 0x64, /* FFT Summary B */ 816 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 817 #endif /* BIG_ENDIAN_HOST */ 818 /* FFT Data */ 819 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 820 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 821 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 822 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 823 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 824 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 825 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 826 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 827 1, 1, 2, 6, 68, 5, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 828 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 829 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 830 0, 831 832 /* Segment 2 */ 833 #ifdef BIG_ENDIAN_HOST 834 0xbb, /* Signature */ 835 0xfb, /* Tag */ 836 0x01, /* Size */ 837 0x14, 838 0x23, 0x66, 0x00, 0x40, /* FFT Summary A */ 839 0x64, 0x64, 0x89, 0x00, /* FFT Summary B */ 840 0x00, 0x00, 0x00, 0x01, /* Segment ID */ 841 #else 842 0x14, /* Length */ 843 0x01, 844 0xfb, /* Tag */ 845 0xbb, /* Signature */ 846 0x40, 0x00, 0x66, 0x23, /* FFT Summary A */ 847 0x00, 0x89, 0x64, 0x64, /* FFT Summary B */ 848 0x01, 0x00, 0x00, 0x00, /* Segment ID */ 849 #endif /* BIG_ENDIAN_HOST */ 850 /* FFT Data */ 851 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 852 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 853 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 854 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 855 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 856 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 857 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 858 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 859 1, 1, 2, 6, 68, 5, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 860 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 861 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 862 0, 863 }; 864 865 /* Report data for 80_80MHz bandwidth for generation 3 chipsets */ 866 static uint8_t reportdata_80_80_gen3[] = { 867 /* Segment 1 */ 868 #ifdef BIG_ENDIAN_HOST 869 0x12, 0x34, 0x56, 0x78, /* fft_timestamp */ 870 0xfa, /* fft_hdr_sig */ 871 0x03, /* fft_hdr_tag */ 872 0x00, /* fft_hdr_length */ 873 0x44, 874 0x0f, 0xf6, 0x00, 0xe0, 875 0x00, 0x00, 0x2f, 0xba, 876 0x20, 0xb4, 0x2c, 0x01, 877 0x00, 0x00, 0x00, 0x00, /* reserved */ 878 #else 879 0x78, 0x56, 0x34, 0x12, /* fft_timestamp */ 880 0x44, /* fft_hdr_length */ 881 0x00, 882 0x03, /* fft_hdr_tag */ 883 0xfa, /* fft_hdr_sig */ 884 0xe0, 0x00, 0xf6, 0x0f, 885 0xba, 0x2f, 0x00, 0x00, 886 0x01, 0x2c, 0xb4, 0x20, 887 0x00, 0x00, 0x00, 0x00, /* reserved */ 888 #endif /* BIG_ENDIAN_HOST */ 889 /* FFT Data */ 890 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 891 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 892 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 893 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 894 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 895 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 896 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 897 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 898 1, 1, 2, 6, 68, 5, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 899 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 900 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 901 902 /* Segment 2 */ 903 #ifdef BIG_ENDIAN_HOST 904 0x12, 0x34, 0x56, 0x78, /* fft_timestamp */ 905 0xfa, /* fft_hdr_sig */ 906 0x03, /* fft_hdr_tag */ 907 0x00, /* fft_hdr_length */ 908 0x44, 909 0x0f, 0xf6, 0x00, 0xe1, 910 0x00, 0x00, 0x2f, 0xba, 911 0x20, 0xb4, 0x2c, 0x01, 912 0x00, 0x00, 0x00, 0x00, /* reserved */ 913 #else 914 0x78, 0x56, 0x34, 0x12, /* fft_timestamp */ 915 0x44, /* fft_hdr_length */ 916 0x00, 917 0x03, /* fft_hdr_tag */ 918 0xfa, /* fft_hdr_sig */ 919 0xe1, 0x00, 0xf6, 0x0f, 920 0xba, 0x2f, 0x00, 0x00, 921 0x01, 0x2c, 0xb4, 0x20, 922 0x00, 0x00, 0x00, 0x00, /* reserved */ 923 #endif /* BIG_ENDIAN_HOST */ 924 /* FFT Data */ 925 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 926 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 927 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 928 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 929 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 930 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 931 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 932 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 933 1, 1, 2, 6, 68, 5, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 934 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 935 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 936 }; 937 938 /* RF measurement information for 80_80 MHz bandwidth */ 939 static struct target_if_spectral_rfqual_info rfqual_info_80_80 = { 940 .rssi_comb = 1, 941 942 .pc_rssi_info[0].rssi_pri20 = 1, 943 .pc_rssi_info[0].rssi_sec20 = 17, 944 .pc_rssi_info[0].rssi_sec40 = 40, 945 .pc_rssi_info[0].rssi_sec80 = 128, 946 947 .pc_rssi_info[1].rssi_pri20 = 128, 948 .pc_rssi_info[1].rssi_sec20 = 128, 949 .pc_rssi_info[1].rssi_sec40 = 128, 950 .pc_rssi_info[1].rssi_sec80 = 128, 951 952 .pc_rssi_info[2].rssi_pri20 = 128, 953 .pc_rssi_info[2].rssi_sec20 = 128, 954 .pc_rssi_info[2].rssi_sec40 = 128, 955 .pc_rssi_info[2].rssi_sec80 = 128, 956 957 .pc_rssi_info[3].rssi_pri20 = 128, 958 .pc_rssi_info[3].rssi_sec20 = 128, 959 .pc_rssi_info[3].rssi_sec40 = 128, 960 .pc_rssi_info[3].rssi_sec80 = 128, 961 962 .noise_floor[0] = -90, 963 .noise_floor[1] = -90, 964 .noise_floor[2] = -90, 965 .noise_floor[3] = -90, 966 }; 967 968 /* Channel information for 80_80 MHz bandwidth */ 969 static struct target_if_spectral_chan_info chan_info_80_80 = { 970 .center_freq1 = 5210, 971 .center_freq2 = 5530, 972 .chan_width = 160, 973 }; 974 975 /* Spectral config parameters for 80_80 MHz bandwidth */ 976 static struct spectral_config config_80_80_1 = { 977 .ss_fft_period = 1, 978 .ss_period = 35, 979 .ss_count = 0, 980 .ss_short_report = 1, 981 .radar_bin_thresh_sel = 0, 982 .ss_spectral_pri = 1, 983 .ss_fft_size = 9, 984 .ss_gc_ena = 1, 985 .ss_restart_ena = 0, 986 .ss_noise_floor_ref = 65440, 987 .ss_init_delay = 80, 988 .ss_nb_tone_thr = 12, 989 .ss_str_bin_thr = 8, 990 .ss_wb_rpt_mode = 0, 991 .ss_rssi_rpt_mode = 0, 992 .ss_rssi_thr = 240, 993 .ss_pwr_format = 0, 994 .ss_rpt_mode = 2, 995 .ss_bin_scale = 1, 996 .ss_dbm_adj = 1, 997 .ss_chn_mask = 1, 998 .ss_nf_cal[0] = 0, 999 .ss_nf_cal[1] = 0, 1000 .ss_nf_cal[2] = 0, 1001 .ss_nf_cal[3] = 0, 1002 .ss_nf_cal[4] = 0, 1003 .ss_nf_cal[5] = 0, 1004 .ss_nf_pwr[0] = 0, 1005 .ss_nf_pwr[1] = 0, 1006 .ss_nf_pwr[2] = 0, 1007 .ss_nf_pwr[3] = 0, 1008 .ss_nf_pwr[4] = 0, 1009 .ss_nf_pwr[5] = 0, 1010 .ss_nf_temp_data = 0, 1011 }; 1012 1013 #endif /* QCA_SUPPORT_SPECTRAL_SIMULATION */ 1014 #endif /* _SPECTRAL_SIM_INTERNAL_H_ */ 1015