1 /* 2 * Copyright (c) 2015,2017-2018 The Linux Foundation. All rights reserved. 3 * 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _SPECTRAL_SIM_INTERNAL_H_ 21 #define _SPECTRAL_SIM_INTERNAL_H_ 22 23 #ifdef QCA_SUPPORT_SPECTRAL_SIMULATION 24 #include "target_if_spectral.h" 25 26 /* #define SPECTRAL_SIM_DUMP_PARAM_DATA 1 */ 27 /** 28 * struct spectralsim_report - Linked list node of spectal simulation report 29 * Spectral report data instance. Usable in a linked list. 30 * In the case of Direct Attach chipsets, one instance should correspond to 31 * one PHY Data Error frame received from the HW. 32 * XXX Direct Attach support to be implemented if needed. Any modifications 33 * required here can be made at the time of implementation. 34 * In the case of 802.11ac offload chipsets, one instance should correspond to 35 * one report received from HW, inclusive of all TLVs. 36 * 37 * @rfqual_info: RF measurement information 38 * @chan_info: Channel information 39 * @datasize: Length of report data 40 * @data: Pointer to report data 41 * @next: Pointer to next node in the struct spectralsim_report 42 */ 43 struct spectralsim_report { 44 /* 11ac onwards only */ 45 struct target_if_spectral_rfqual_info rfqual_info; 46 /* 11ac onwards only */ 47 struct target_if_spectral_chan_info chan_info; 48 uint32_t datasize; 49 uint8_t *data; 50 struct spectralsim_report *next; 51 }; 52 53 /** 54 * struct spectralsim_reportset - Set of Spectral report data instances 55 * corresponding to one particular configuration. Usable in a linked list. 56 * @config: Spectral config parameters 57 * @headreport: Pointer to the linked list of struct spectralsim_report 58 * @curr_report: Pointer to current node in the linked list of 59 * struct spectralsim_report 60 * @next: Pointer to next node in the struct spectralsim_reportset 61 */ 62 struct spectralsim_reportset { 63 struct spectral_config config; 64 struct spectralsim_report *headreport; 65 struct spectralsim_report *curr_report; 66 struct spectralsim_reportset *next; 67 }; 68 69 /* 70 * struct spectralsim_context - Main structure for Spectral simulation. 71 * All data and controls get linked here. 72 * 73 * For each width (20/40/80/160/80+80), we will have a linked list of 74 * spectralsim_reportset nodes. Each struct spectralsim_reportset will have a 75 * linked list of struct spectralsim_report nodes. When the user requests for a 76 * given PHY mode and Spectral configuration, we find the appropriate 77 * spectralsim_reportset, and then serve struct spectralsim_report instances 78 * from the linked list. If required report count is higher than size of linked 79 * list (or infinite), we repeatedly cycle through the linked list. There can 80 * be more elaborate data structures devised taking care of a large number of 81 * possibilities, but we stick to a simple scheme given limited simulation 82 * needs. 83 * 84 * @bw20_headreportset : Linked list of spectralsim_reportset for 20MHz width 85 * @bw20_headreportset : Linked list of spectralsim_reportset for 40MHz width 86 * @bw20_headreportset : Linked list of spectralsim_reportset for 80MHz width 87 * @bw20_headreportset : Linked list of spectralsim_reportset for 160MHz width 88 * @bw20_headreportset : Linked list of spectralsim_reportset for 80_80MHz width 89 * @curr_reportset : Pointer to current node in the linked list of 90 * struct spectralsim_reportset 91 * @is_enabled : Whether the simulated spectral scan is set as enabled 92 * @is_active : Whether the simulated spectral scan is set as active 93 * @ssim_pherrdelivery_timer : Simulated Phyerr delivery timer 94 * @ssim_starting_tsf64 : Starting 64-bit TSF value for spectral simulation 95 * @ssim_period_ms : Simulated Phyerr delivery period in ms 96 * @ssim_count : Number of simulated spectral samples to deliver 97 * @populate_report_static : Pointer to function to populate static spectral 98 * report data 99 */ 100 struct spectralsim_context { 101 struct spectralsim_reportset *bw20_headreportset; 102 struct spectralsim_reportset *bw40_headreportset; 103 struct spectralsim_reportset *bw80_headreportset; 104 struct spectralsim_reportset *bw160_headreportset; 105 struct spectralsim_reportset *bw80_80_headreportset; 106 107 struct spectralsim_reportset *curr_reportset; 108 bool is_enabled; 109 bool is_active; 110 111 qdf_timer_t ssim_pherrdelivery_timer; 112 uint64_t ssim_starting_tsf64; 113 uint32_t ssim_period_ms; /* TODO: Support in microseconds */ 114 uint32_t ssim_count; 115 int (*populate_report_static)(struct spectralsim_report *report, 116 enum phy_ch_width width, bool is_80_80); 117 }; 118 119 /* Helper Macros */ 120 121 /* Allocate and populate reportset for a single configuration */ 122 #define SPECTRAL_SIM_REPORTSET_ALLOCPOPL_SINGLE(simctx, reportset, width, \ 123 is_80_80) \ 124 { \ 125 (reportset) = (struct spectralsim_reportset *) \ 126 qdf_mem_malloc(sizeof(struct spectralsim_reportset)); \ 127 \ 128 if ((reportset) == NULL) { \ 129 spectral_err("Spectral simulation: Could not allocate memory for report set"); \ 130 target_if_depopulate_simdata((simctx)); \ 131 return -EPERM; \ 132 } \ 133 \ 134 qdf_mem_zero((reportset), sizeof(struct spectralsim_reportset)); \ 135 \ 136 if (target_if_populate_reportset_static( \ 137 (simctx), (reportset), (width), (is_80_80)) != 0) { \ 138 target_if_depopulate_simdata((simctx)); \ 139 return -EPERM; \ 140 } \ 141 \ 142 (reportset)->next = NULL; \ 143 } 144 145 /* Depopulate and free list of report sets */ 146 #define SPECTRAL_SIM_REPORTSET_DEPOPLFREE_LIST(reportset) \ 147 { \ 148 struct spectralsim_reportset *curr_reportset = NULL; \ 149 struct spectralsim_reportset *next_reportset = NULL; \ 150 \ 151 curr_reportset = (reportset); \ 152 \ 153 while (curr_reportset) { \ 154 next_reportset = curr_reportset->next; \ 155 target_if_depopulate_reportset(curr_reportset); \ 156 qdf_mem_free(curr_reportset); \ 157 curr_reportset = next_reportset; \ 158 } \ 159 \ 160 (reportset) = NULL; \ 161 } 162 163 /* Values for static population */ 164 165 /* 20 MHz */ 166 167 /* Report data for 20MHz bandwidth for generation 2 chipsets */ 168 static uint8_t reportdata_20_gen2[] = { 169 #ifdef BIG_ENDIAN_HOST 170 0xbb, /* Signature */ 171 0xfb, /* Tag */ 172 0x00, /* Size */ 173 0x54, 174 0x2e, 0x60, 0x0f, 0xe8, /* FFT Summary A */ 175 0x00, 0x00, 0x04, 0x00, /* FFT Summary B */ 176 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 177 #else 178 0x54, /* Length */ 179 0x00, 180 0xfb, /* Tag */ 181 0xbb, /* Signature */ 182 0xe8, 0x0f, 0x60, 0x2e, /* FFT Summary A */ 183 0x00, 0x04, 0x00, 0x00, /* FFT Summary B */ 184 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 185 #endif /* BIG_ENDIAN_HOST */ 186 /* FFT Data */ 187 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 1, 2, 0, 1, 1, 1, 0, 188 0, 1, 1, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 189 1, 1, 0, 2, 1, 2, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 190 }; 191 192 /* Report data for 20MHz bandwidth for generation 3 chipsets */ 193 static uint8_t reportdata_20_gen3[] = { 194 #ifdef BIG_ENDIAN_HOST 195 0x12, 0x34, 0x56, 0x78, /* fft_timestamp */ 196 0xfa, /* fft_hdr_sig */ 197 0x03, /* fft_hdr_tag */ 198 0x00, /* fft_hdr_length */ 199 0x14, 200 0x0f, 0xf6, 0x00, 0xe0, 201 0x00, 0x00, 0x2f, 0xba, 202 0x20, 0xb4, 0x2c, 0x01, 203 0x00, 0x00, 0x00, 0x00, /* reserved */ 204 #else 205 0x78, 0x56, 0x34, 0x12, /* fft_timestamp */ 206 0x14, /* fft_hdr_length */ 207 0x00, 208 0x03, /* fft_hdr_tag */ 209 0xfa, /* fft_hdr_sig */ 210 0xe0, 0x00, 0xf6, 0x0f, 211 0xba, 0x2f, 0x00, 0x00, 212 0x01, 0x2c, 0xb4, 0x20, 213 0x00, 0x00, 0x00, 0x00, /* reserved */ 214 #endif /* BIG_ENDIAN_HOST */ 215 /* FFT Data */ 216 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 1, 2, 0, 1, 1, 1, 0, 217 0, 1, 1, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 218 1, 1, 0, 2, 1, 2, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 219 }; 220 221 /* RF measurement information for 20 MHz bandwidth */ 222 static struct target_if_spectral_rfqual_info rfqual_info_20 = { 223 .rssi_comb = 1, 224 225 .pc_rssi_info[0].rssi_pri20 = 1, 226 .pc_rssi_info[0].rssi_sec20 = 128, 227 .pc_rssi_info[0].rssi_sec40 = 128, 228 .pc_rssi_info[0].rssi_sec80 = 128, 229 230 .pc_rssi_info[1].rssi_pri20 = 128, 231 .pc_rssi_info[1].rssi_sec20 = 128, 232 .pc_rssi_info[1].rssi_sec40 = 128, 233 .pc_rssi_info[1].rssi_sec80 = 128, 234 235 .pc_rssi_info[2].rssi_pri20 = 128, 236 .pc_rssi_info[2].rssi_sec20 = 128, 237 .pc_rssi_info[2].rssi_sec40 = 128, 238 .pc_rssi_info[2].rssi_sec80 = 128, 239 240 .pc_rssi_info[3].rssi_pri20 = 128, 241 .pc_rssi_info[3].rssi_sec20 = 128, 242 .pc_rssi_info[3].rssi_sec40 = 128, 243 .pc_rssi_info[3].rssi_sec80 = 128, 244 245 .noise_floor[0] = -90, 246 .noise_floor[1] = -90, 247 .noise_floor[2] = -90, 248 .noise_floor[3] = -90, 249 }; 250 251 /* Channel information for 20 MHz bandwidth */ 252 static struct target_if_spectral_chan_info chan_info_20 = { 253 .center_freq1 = 5180, 254 .center_freq2 = 0, 255 .chan_width = 20, 256 }; 257 258 /* Spectral config parameters for 20 MHz bandwidth */ 259 static struct spectral_config config_20_1 = { 260 .ss_fft_period = 1, 261 .ss_period = 35, 262 .ss_count = 0, 263 .ss_short_report = 1, 264 .radar_bin_thresh_sel = 0, 265 .ss_spectral_pri = 1, 266 .ss_fft_size = 7, 267 .ss_gc_ena = 1, 268 .ss_restart_ena = 0, 269 .ss_noise_floor_ref = 65440, 270 .ss_init_delay = 80, 271 .ss_nb_tone_thr = 12, 272 .ss_str_bin_thr = 8, 273 .ss_wb_rpt_mode = 0, 274 .ss_rssi_rpt_mode = 0, 275 .ss_rssi_thr = 240, 276 .ss_pwr_format = 0, 277 .ss_rpt_mode = 2, 278 .ss_bin_scale = 1, 279 .ss_dbm_adj = 1, 280 .ss_chn_mask = 1, 281 .ss_nf_cal[0] = 0, 282 .ss_nf_cal[1] = 0, 283 .ss_nf_cal[2] = 0, 284 .ss_nf_cal[3] = 0, 285 .ss_nf_cal[4] = 0, 286 .ss_nf_cal[5] = 0, 287 .ss_nf_pwr[0] = 0, 288 .ss_nf_pwr[1] = 0, 289 .ss_nf_pwr[2] = 0, 290 .ss_nf_pwr[3] = 0, 291 .ss_nf_pwr[4] = 0, 292 .ss_nf_pwr[5] = 0, 293 .ss_nf_temp_data = 0, 294 }; 295 296 /* 40 MHz */ 297 298 /* Report data for 40MHz bandwidth for generation 2 chipsets */ 299 static uint8_t reportdata_40_gen2[] = { 300 #ifdef BIG_ENDIAN_HOST 301 0xbb, /* Signature */ 302 0xfb, /* Tag */ 303 0x00, /* Size */ 304 0x94, 305 0x2e, 0x61, 0x0f, 0x80, /* FFT Summary A */ 306 0x00, 0x00, 0x06, 0x00, /* FFT Summary B */ 307 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 308 #else 309 0x94, /* Length */ 310 0x00, 311 0xfb, /* Tag */ 312 0xbb, /* Signature */ 313 0x80, 0x0f, 0x61, 0x2e, /* FFT Summary A */ 314 0x00, 0x06, 0x00, 0x00, /* FFT Summary B */ 315 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 316 #endif /* BIG_ENDIAN_HOST */ 317 /* FFT Data */ 318 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 319 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 320 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 1, 321 0, 0, 0, 1, 0, 0, 0, 0, 2, 1, 0, 2, 1, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 322 1, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 1, 0, 323 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 324 }; 325 326 /* Report data for 40MHz bandwidth for generation 3 chipsets */ 327 static uint8_t reportdata_40_gen3[] = { 328 #ifdef BIG_ENDIAN_HOST 329 0x12, 0x34, 0x56, 0x78, /* fft_timestamp */ 330 0xfa, /* fft_hdr_sig */ 331 0x03, /* fft_hdr_tag */ 332 0x00, /* fft_hdr_length */ 333 0x24, 334 0x0f, 0xf6, 0x00, 0xe0, 335 0x00, 0x00, 0x2f, 0xba, 336 0x20, 0xb4, 0x2c, 0x01, 337 0x00, 0x00, 0x00, 0x00, /* reserved */ 338 #else 339 0x78, 0x56, 0x34, 0x12, /* fft_timestamp */ 340 0x24, /* fft_hdr_length */ 341 0x00, 342 0x03, /* fft_hdr_tag */ 343 0xfa, /* fft_hdr_sig */ 344 0xe0, 0x00, 0xf6, 0x0f, 345 0xba, 0x2f, 0x00, 0x00, 346 0x01, 0x2c, 0xb4, 0x20, 347 0x00, 0x00, 0x00, 0x00, /* reserved */ 348 #endif /* BIG_ENDIAN_HOST */ 349 /* FFT Data */ 350 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 351 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 352 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 1, 353 0, 0, 0, 1, 0, 0, 0, 0, 2, 1, 0, 2, 1, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 354 1, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 1, 0, 355 0, 0, 0, 1, 0, 0, 0, 0, 356 }; 357 358 /* RF measurement information for 40 MHz bandwidth */ 359 static struct target_if_spectral_rfqual_info rfqual_info_40 = { 360 .rssi_comb = 1, 361 362 .pc_rssi_info[0].rssi_pri20 = 1, 363 .pc_rssi_info[0].rssi_sec20 = 2, 364 .pc_rssi_info[0].rssi_sec40 = 128, 365 .pc_rssi_info[0].rssi_sec80 = 128, 366 367 .pc_rssi_info[1].rssi_pri20 = 128, 368 .pc_rssi_info[1].rssi_sec20 = 128, 369 .pc_rssi_info[1].rssi_sec40 = 128, 370 .pc_rssi_info[1].rssi_sec80 = 128, 371 372 .pc_rssi_info[2].rssi_pri20 = 128, 373 .pc_rssi_info[2].rssi_sec20 = 128, 374 .pc_rssi_info[2].rssi_sec40 = 128, 375 .pc_rssi_info[2].rssi_sec80 = 128, 376 377 .pc_rssi_info[3].rssi_pri20 = 128, 378 .pc_rssi_info[3].rssi_sec20 = 128, 379 .pc_rssi_info[3].rssi_sec40 = 128, 380 .pc_rssi_info[3].rssi_sec80 = 128, 381 382 .noise_floor[0] = -90, 383 .noise_floor[1] = -90, 384 .noise_floor[2] = -90, 385 .noise_floor[3] = -90, 386 }; 387 388 /* Channel information for 40 MHz bandwidth */ 389 static struct target_if_spectral_chan_info chan_info_40 = { 390 .center_freq1 = 5180, 391 .center_freq2 = 0, 392 .chan_width = 40, 393 }; 394 395 /* Spectral config parameters for 40 MHz bandwidth */ 396 static struct spectral_config config_40_1 = { 397 .ss_fft_period = 1, 398 .ss_period = 35, 399 .ss_count = 0, 400 .ss_short_report = 1, 401 .radar_bin_thresh_sel = 0, 402 .ss_spectral_pri = 1, 403 .ss_fft_size = 8, 404 .ss_gc_ena = 1, 405 .ss_restart_ena = 0, 406 .ss_noise_floor_ref = 65440, 407 .ss_init_delay = 80, 408 .ss_nb_tone_thr = 12, 409 .ss_str_bin_thr = 8, 410 .ss_wb_rpt_mode = 0, 411 .ss_rssi_rpt_mode = 0, 412 .ss_rssi_thr = 240, 413 .ss_pwr_format = 0, 414 .ss_rpt_mode = 2, 415 .ss_bin_scale = 1, 416 .ss_dbm_adj = 1, 417 .ss_chn_mask = 1, 418 .ss_nf_cal[0] = 0, 419 .ss_nf_cal[1] = 0, 420 .ss_nf_cal[2] = 0, 421 .ss_nf_cal[3] = 0, 422 .ss_nf_cal[4] = 0, 423 .ss_nf_cal[5] = 0, 424 .ss_nf_pwr[0] = 0, 425 .ss_nf_pwr[1] = 0, 426 .ss_nf_pwr[2] = 0, 427 .ss_nf_pwr[3] = 0, 428 .ss_nf_pwr[4] = 0, 429 .ss_nf_pwr[5] = 0, 430 .ss_nf_temp_data = 0, 431 }; 432 433 /* 80 MHz */ 434 435 /* Report data for 80MHz bandwidth for generation 2 chipsets */ 436 static uint8_t reportdata_80_gen2[] = { 437 #ifdef BIG_ENDIAN_HOST 438 0xbb, /* Signature */ 439 0xfb, /* Tag */ 440 0x01, /* Size */ 441 0x14, 442 0x19, 0xeb, 0x80, 0x40, /* FFT Summary A */ 443 0x00, 0x00, 0x10, 0x00, /* FFT Summary B */ 444 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 445 #else 446 0x14, /* Length */ 447 0x01, 448 0xfb, /* Tag */ 449 0xbb, /* Signature */ 450 0x40, 0x80, 0xeb, 0x19, /* FFT Summary A */ 451 0x00, 0x10, 0x00, 0x00, /* FFT Summary B */ 452 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 453 #endif /* BIG_ENDIAN_HOST */ 454 /* FFT Data */ 455 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 456 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 457 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 458 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 459 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 460 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 462 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 463 0, 0, 0, 1, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 466 }; 467 468 /* Report data for 80MHz bandwidth for generation 3 chipsets */ 469 static uint8_t reportdata_80_gen3[] = { 470 #ifdef BIG_ENDIAN_HOST 471 0x12, 0x34, 0x56, 0x78, /* fft_timestamp */ 472 0xfa, /* fft_hdr_sig */ 473 0x03, /* fft_hdr_tag */ 474 0x00, /* fft_hdr_length */ 475 0x44, 476 0x0f, 0xf6, 0x00, 0xe0, 477 0x00, 0x00, 0x2f, 0xba, 478 0x20, 0xb4, 0x2c, 0x01, 479 0x00, 0x00, 0x00, 0x00, /* reserved */ 480 #else 481 0x78, 0x56, 0x34, 0x12, /* fft_timestamp */ 482 0x44, /* fft_hdr_length */ 483 0x00, 484 0x03, /* fft_hdr_tag */ 485 0xfa, /* fft_hdr_sig */ 486 0xe0, 0x00, 0xf6, 0x0f, 487 0xba, 0x2f, 0x00, 0x00, 488 0x01, 0x2c, 0xb4, 0x20, 489 0x00, 0x00, 0x00, 0x00, /* reserved */ 490 #endif /* BIG_ENDIAN_HOST */ 491 /* FFT Data */ 492 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 493 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 494 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 495 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 496 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 497 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 498 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 499 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 500 0, 0, 0, 1, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 501 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 502 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 503 }; 504 505 /* RF measurement information for 80 MHz bandwidth */ 506 static struct target_if_spectral_rfqual_info rfqual_info_80 = { 507 .rssi_comb = 16, 508 509 .pc_rssi_info[0].rssi_pri20 = 16, 510 .pc_rssi_info[0].rssi_sec20 = 17, 511 .pc_rssi_info[0].rssi_sec40 = 0, 512 .pc_rssi_info[0].rssi_sec80 = 128, 513 514 .pc_rssi_info[1].rssi_pri20 = 128, 515 .pc_rssi_info[1].rssi_sec20 = 128, 516 .pc_rssi_info[1].rssi_sec40 = 128, 517 .pc_rssi_info[1].rssi_sec80 = 128, 518 519 .pc_rssi_info[2].rssi_pri20 = 128, 520 .pc_rssi_info[2].rssi_sec20 = 128, 521 .pc_rssi_info[2].rssi_sec40 = 128, 522 .pc_rssi_info[2].rssi_sec80 = 128, 523 524 .pc_rssi_info[3].rssi_pri20 = 128, 525 .pc_rssi_info[3].rssi_sec20 = 128, 526 .pc_rssi_info[3].rssi_sec40 = 128, 527 .pc_rssi_info[3].rssi_sec80 = 128, 528 529 .noise_floor[0] = -90, 530 .noise_floor[1] = -90, 531 .noise_floor[2] = -90, 532 .noise_floor[3] = -90, 533 }; 534 535 /* Channel information for 80 MHz bandwidth */ 536 static struct target_if_spectral_chan_info chan_info_80 = { 537 .center_freq1 = 5210, 538 .center_freq2 = 0, 539 .chan_width = 80, 540 }; 541 542 /* Spectral config parameters for 80 MHz bandwidth */ 543 static struct spectral_config config_80_1 = { 544 .ss_fft_period = 1, 545 .ss_period = 35, 546 .ss_count = 0, 547 .ss_short_report = 1, 548 .radar_bin_thresh_sel = 0, 549 .ss_spectral_pri = 1, 550 .ss_fft_size = 9, 551 .ss_gc_ena = 1, 552 .ss_restart_ena = 0, 553 .ss_noise_floor_ref = 65440, 554 .ss_init_delay = 80, 555 .ss_nb_tone_thr = 12, 556 .ss_str_bin_thr = 8, 557 .ss_wb_rpt_mode = 0, 558 .ss_rssi_rpt_mode = 0, 559 .ss_rssi_thr = 240, 560 .ss_pwr_format = 0, 561 .ss_rpt_mode = 2, 562 .ss_bin_scale = 1, 563 .ss_dbm_adj = 1, 564 .ss_chn_mask = 1, 565 .ss_nf_cal[0] = 0, 566 .ss_nf_cal[1] = 0, 567 .ss_nf_cal[2] = 0, 568 .ss_nf_cal[3] = 0, 569 .ss_nf_cal[4] = 0, 570 .ss_nf_cal[5] = 0, 571 .ss_nf_pwr[0] = 0, 572 .ss_nf_pwr[1] = 0, 573 .ss_nf_pwr[2] = 0, 574 .ss_nf_pwr[3] = 0, 575 .ss_nf_pwr[4] = 0, 576 .ss_nf_pwr[5] = 0, 577 .ss_nf_temp_data = 0, 578 }; 579 580 /* 160 MHz */ 581 582 /* Report data for 160MHz bandwidth for generation 2 chipsets */ 583 static uint8_t reportdata_160_gen2[] = { 584 /* Segment 1 */ 585 #ifdef BIG_ENDIAN_HOST 586 0xbb, /* Signature */ 587 0xfb, /* Tag */ 588 0x01, /* Size */ 589 0x14, 590 0x23, 0x66, 0x00, 0x40, /* FFT Summary A */ 591 0x5c, 0x5c, 0x78, 0x00, /* FFT Summary B */ 592 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 593 #else 594 0x14, /* Length */ 595 0x01, 596 0xfb, /* Tag */ 597 0xbb, /* Signature */ 598 0x40, 0x00, 0x66, 0x23, /* FFT Summary A */ 599 0x00, 0x78, 0x5c, 0x5c, /* FFT Summary B */ 600 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 601 #endif /* BIG_ENDIAN_HOST */ 602 /* FFT Data */ 603 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 604 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 605 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 606 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 607 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 608 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 609 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 610 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 611 1, 1, 2, 4, 60, 4, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 612 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 613 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 614 0, 615 616 /* Segment 2 */ 617 #ifdef BIG_ENDIAN_HOST 618 0xbb, /* Signature */ 619 0xfb, /* Tag */ 620 0x01, /* Size */ 621 0x14, 622 0x23, 0x66, 0x00, 0x40, /* FFT Summary A */ 623 0x5c, 0x5c, 0x78, 0x00, /* FFT Summary B */ 624 0x00, 0x00, 0x00, 0x01, /* Segment ID */ 625 #else 626 0x14, /* Length */ 627 0x01, 628 0xfb, /* Tag */ 629 0xbb, /* Signature */ 630 0x40, 0x00, 0x66, 0x23, /* FFT Summary A */ 631 0x00, 0x78, 0x5c, 0x5c, /* FFT Summary B */ 632 0x01, 0x00, 0x00, 0x00, /* Segment ID */ 633 #endif /* BIG_ENDIAN_HOST */ 634 /* FFT Data */ 635 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 636 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 637 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 638 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 639 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 640 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 641 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 642 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 643 1, 1, 2, 4, 60, 4, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 644 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 645 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 646 0, 647 }; 648 649 /* Report data for 160MHz bandwidth for generation 3 chipsets */ 650 static uint8_t reportdata_160_gen3[] = { 651 /* Segment 1 */ 652 #ifdef BIG_ENDIAN_HOST 653 0x12, 0x34, 0x56, 0x78, /* fft_timestamp */ 654 0xfa, /* fft_hdr_sig */ 655 0x03, /* fft_hdr_tag */ 656 0x00, /* fft_hdr_length */ 657 0x44, 658 0x0f, 0xf6, 0x00, 0xe0, 659 0x00, 0x00, 0x2f, 0xba, 660 0x20, 0xb4, 0x2c, 0x01, 661 0x00, 0x00, 0x00, 0x00, /* reserved */ 662 #else 663 0x78, 0x56, 0x34, 0x12, /* fft_timestamp */ 664 0x44, /* fft_hdr_length */ 665 0x00, 666 0x03, /* fft_hdr_tag */ 667 0xfa, /* fft_hdr_sig */ 668 0xe0, 0x00, 0xf6, 0x0f, 669 0xba, 0x2f, 0x00, 0x00, 670 0x01, 0x2c, 0xb4, 0x20, 671 0x00, 0x00, 0x00, 0x00, /* reserved */ 672 #endif /* BIG_ENDIAN_HOST */ 673 /* FFT Data */ 674 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 675 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 676 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 677 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 678 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 679 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 680 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 681 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 682 1, 1, 2, 4, 60, 4, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 683 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 684 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 685 686 /* Segment 2 */ 687 #ifdef BIG_ENDIAN_HOST 688 0x12, 0x34, 0x56, 0x78, /* fft_timestamp */ 689 0xfa, /* fft_hdr_sig */ 690 0x03, /* fft_hdr_tag */ 691 0x00, /* fft_hdr_length */ 692 0x44, 693 0x0f, 0xf6, 0x00, 0xe1, 694 0x00, 0x00, 0x2f, 0xba, 695 0x20, 0xb4, 0x2c, 0x01, 696 0x00, 0x00, 0x00, 0x00, /* reserved */ 697 #else 698 0x78, 0x56, 0x34, 0x12, /* fft_timestamp */ 699 0x44, /* fft_hdr_length */ 700 0x00, 701 0x03, /* fft_hdr_tag */ 702 0xfa, /* fft_hdr_sig */ 703 0xe1, 0x00, 0xf6, 0x0f, 704 0xba, 0x2f, 0x00, 0x00, 705 0x01, 0x2c, 0xb4, 0x20, 706 0x00, 0x00, 0x00, 0x00, /* reserved */ 707 #endif /* BIG_ENDIAN_HOST */ 708 /* FFT Data */ 709 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 710 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 711 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 712 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 713 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 714 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 715 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 716 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 717 1, 1, 2, 4, 60, 4, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 718 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 719 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 720 }; 721 722 /* RF measurement information for 160 MHz bandwidth */ 723 static struct target_if_spectral_rfqual_info rfqual_info_160 = { 724 .rssi_comb = 3, 725 726 .pc_rssi_info[0].rssi_pri20 = 3, 727 .pc_rssi_info[0].rssi_sec20 = 12, 728 .pc_rssi_info[0].rssi_sec40 = 41, 729 .pc_rssi_info[0].rssi_sec80 = 128, 730 731 .pc_rssi_info[1].rssi_pri20 = 128, 732 .pc_rssi_info[1].rssi_sec20 = 128, 733 .pc_rssi_info[1].rssi_sec40 = 128, 734 .pc_rssi_info[1].rssi_sec80 = 128, 735 736 .pc_rssi_info[2].rssi_pri20 = 128, 737 .pc_rssi_info[2].rssi_sec20 = 128, 738 .pc_rssi_info[2].rssi_sec40 = 128, 739 .pc_rssi_info[2].rssi_sec80 = 128, 740 741 .pc_rssi_info[3].rssi_pri20 = 128, 742 .pc_rssi_info[3].rssi_sec20 = 128, 743 .pc_rssi_info[3].rssi_sec40 = 128, 744 .pc_rssi_info[3].rssi_sec80 = 128, 745 746 .noise_floor[0] = -90, 747 .noise_floor[1] = -90, 748 .noise_floor[2] = -90, 749 .noise_floor[3] = -90, 750 }; 751 752 /* Channel information for 160 MHz bandwidth */ 753 static struct target_if_spectral_chan_info chan_info_160 = { 754 .center_freq1 = 5250, 755 .center_freq2 = 0, 756 .chan_width = 160, 757 }; 758 759 /* Spectral config parameters for 160 MHz bandwidth */ 760 static struct spectral_config config_160_1 = { 761 .ss_fft_period = 1, 762 .ss_period = 35, 763 .ss_count = 0, 764 .ss_short_report = 1, 765 .radar_bin_thresh_sel = 0, 766 .ss_spectral_pri = 1, 767 .ss_fft_size = 9, 768 .ss_gc_ena = 1, 769 .ss_restart_ena = 0, 770 .ss_noise_floor_ref = 65440, 771 .ss_init_delay = 80, 772 .ss_nb_tone_thr = 12, 773 .ss_str_bin_thr = 8, 774 .ss_wb_rpt_mode = 0, 775 .ss_rssi_rpt_mode = 0, 776 .ss_rssi_thr = 240, 777 .ss_pwr_format = 0, 778 .ss_rpt_mode = 2, 779 .ss_bin_scale = 1, 780 .ss_dbm_adj = 1, 781 .ss_chn_mask = 1, 782 .ss_nf_cal[0] = 0, 783 .ss_nf_cal[1] = 0, 784 .ss_nf_cal[2] = 0, 785 .ss_nf_cal[3] = 0, 786 .ss_nf_cal[4] = 0, 787 .ss_nf_cal[5] = 0, 788 .ss_nf_pwr[0] = 0, 789 .ss_nf_pwr[1] = 0, 790 .ss_nf_pwr[2] = 0, 791 .ss_nf_pwr[3] = 0, 792 .ss_nf_pwr[4] = 0, 793 .ss_nf_pwr[5] = 0, 794 .ss_nf_temp_data = 0, 795 }; 796 797 /* 80+80 MHz */ 798 799 /* Report data for 80_80MHz bandwidth for generation 2 chipsets */ 800 static uint8_t reportdata_80_80_gen2[] = { 801 /* Segment 1 */ 802 #ifdef BIG_ENDIAN_HOST 803 0xbb, /* Signature */ 804 0xfb, /* Tag */ 805 0x01, /* Size */ 806 0x14, 807 0x23, 0x66, 0x00, 0x40, /* FFT Summary A */ 808 0x64, 0x64, 0x89, 0x00, /* FFT Summary B */ 809 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 810 #else 811 0x14, /* Length */ 812 0x01, 813 0xfb, /* Tag */ 814 0xbb, /* Signature */ 815 0x40, 0x00, 0x66, 0x23, /* FFT Summary A */ 816 0x00, 0x89, 0x64, 0x64, /* FFT Summary B */ 817 0x00, 0x00, 0x00, 0x00, /* Segment ID */ 818 #endif /* BIG_ENDIAN_HOST */ 819 /* FFT Data */ 820 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 821 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 822 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 823 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 824 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 825 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 826 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 827 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 828 1, 1, 2, 6, 68, 5, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 829 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 830 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 831 0, 832 833 /* Segment 2 */ 834 #ifdef BIG_ENDIAN_HOST 835 0xbb, /* Signature */ 836 0xfb, /* Tag */ 837 0x01, /* Size */ 838 0x14, 839 0x23, 0x66, 0x00, 0x40, /* FFT Summary A */ 840 0x64, 0x64, 0x89, 0x00, /* FFT Summary B */ 841 0x00, 0x00, 0x00, 0x01, /* Segment ID */ 842 #else 843 0x14, /* Length */ 844 0x01, 845 0xfb, /* Tag */ 846 0xbb, /* Signature */ 847 0x40, 0x00, 0x66, 0x23, /* FFT Summary A */ 848 0x00, 0x89, 0x64, 0x64, /* FFT Summary B */ 849 0x01, 0x00, 0x00, 0x00, /* Segment ID */ 850 #endif /* BIG_ENDIAN_HOST */ 851 /* FFT Data */ 852 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 853 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 854 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 855 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 856 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 857 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 858 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 859 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 860 1, 1, 2, 6, 68, 5, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 861 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 862 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 863 0, 864 }; 865 866 /* Report data for 80_80MHz bandwidth for generation 3 chipsets */ 867 static uint8_t reportdata_80_80_gen3[] = { 868 /* Segment 1 */ 869 #ifdef BIG_ENDIAN_HOST 870 0x12, 0x34, 0x56, 0x78, /* fft_timestamp */ 871 0xfa, /* fft_hdr_sig */ 872 0x03, /* fft_hdr_tag */ 873 0x00, /* fft_hdr_length */ 874 0x44, 875 0x0f, 0xf6, 0x00, 0xe0, 876 0x00, 0x00, 0x2f, 0xba, 877 0x20, 0xb4, 0x2c, 0x01, 878 0x00, 0x00, 0x00, 0x00, /* reserved */ 879 #else 880 0x78, 0x56, 0x34, 0x12, /* fft_timestamp */ 881 0x44, /* fft_hdr_length */ 882 0x00, 883 0x03, /* fft_hdr_tag */ 884 0xfa, /* fft_hdr_sig */ 885 0xe0, 0x00, 0xf6, 0x0f, 886 0xba, 0x2f, 0x00, 0x00, 887 0x01, 0x2c, 0xb4, 0x20, 888 0x00, 0x00, 0x00, 0x00, /* reserved */ 889 #endif /* BIG_ENDIAN_HOST */ 890 /* FFT Data */ 891 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 892 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 893 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 894 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 895 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 896 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 897 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 898 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 899 1, 1, 2, 6, 68, 5, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 900 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 901 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 902 903 /* Segment 2 */ 904 #ifdef BIG_ENDIAN_HOST 905 0x12, 0x34, 0x56, 0x78, /* fft_timestamp */ 906 0xfa, /* fft_hdr_sig */ 907 0x03, /* fft_hdr_tag */ 908 0x00, /* fft_hdr_length */ 909 0x44, 910 0x0f, 0xf6, 0x00, 0xe1, 911 0x00, 0x00, 0x2f, 0xba, 912 0x20, 0xb4, 0x2c, 0x01, 913 0x00, 0x00, 0x00, 0x00, /* reserved */ 914 #else 915 0x78, 0x56, 0x34, 0x12, /* fft_timestamp */ 916 0x44, /* fft_hdr_length */ 917 0x00, 918 0x03, /* fft_hdr_tag */ 919 0xfa, /* fft_hdr_sig */ 920 0xe1, 0x00, 0xf6, 0x0f, 921 0xba, 0x2f, 0x00, 0x00, 922 0x01, 0x2c, 0xb4, 0x20, 923 0x00, 0x00, 0x00, 0x00, /* reserved */ 924 #endif /* BIG_ENDIAN_HOST */ 925 /* FFT Data */ 926 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 927 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 928 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 929 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 930 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 931 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 932 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 933 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 934 1, 1, 2, 6, 68, 5, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 935 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 936 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 937 }; 938 939 /* RF measurement information for 80_80 MHz bandwidth */ 940 static struct target_if_spectral_rfqual_info rfqual_info_80_80 = { 941 .rssi_comb = 1, 942 943 .pc_rssi_info[0].rssi_pri20 = 1, 944 .pc_rssi_info[0].rssi_sec20 = 17, 945 .pc_rssi_info[0].rssi_sec40 = 40, 946 .pc_rssi_info[0].rssi_sec80 = 128, 947 948 .pc_rssi_info[1].rssi_pri20 = 128, 949 .pc_rssi_info[1].rssi_sec20 = 128, 950 .pc_rssi_info[1].rssi_sec40 = 128, 951 .pc_rssi_info[1].rssi_sec80 = 128, 952 953 .pc_rssi_info[2].rssi_pri20 = 128, 954 .pc_rssi_info[2].rssi_sec20 = 128, 955 .pc_rssi_info[2].rssi_sec40 = 128, 956 .pc_rssi_info[2].rssi_sec80 = 128, 957 958 .pc_rssi_info[3].rssi_pri20 = 128, 959 .pc_rssi_info[3].rssi_sec20 = 128, 960 .pc_rssi_info[3].rssi_sec40 = 128, 961 .pc_rssi_info[3].rssi_sec80 = 128, 962 963 .noise_floor[0] = -90, 964 .noise_floor[1] = -90, 965 .noise_floor[2] = -90, 966 .noise_floor[3] = -90, 967 }; 968 969 /* Channel information for 80_80 MHz bandwidth */ 970 static struct target_if_spectral_chan_info chan_info_80_80 = { 971 .center_freq1 = 5210, 972 .center_freq2 = 5530, 973 .chan_width = 160, 974 }; 975 976 /* Spectral config parameters for 80_80 MHz bandwidth */ 977 static struct spectral_config config_80_80_1 = { 978 .ss_fft_period = 1, 979 .ss_period = 35, 980 .ss_count = 0, 981 .ss_short_report = 1, 982 .radar_bin_thresh_sel = 0, 983 .ss_spectral_pri = 1, 984 .ss_fft_size = 9, 985 .ss_gc_ena = 1, 986 .ss_restart_ena = 0, 987 .ss_noise_floor_ref = 65440, 988 .ss_init_delay = 80, 989 .ss_nb_tone_thr = 12, 990 .ss_str_bin_thr = 8, 991 .ss_wb_rpt_mode = 0, 992 .ss_rssi_rpt_mode = 0, 993 .ss_rssi_thr = 240, 994 .ss_pwr_format = 0, 995 .ss_rpt_mode = 2, 996 .ss_bin_scale = 1, 997 .ss_dbm_adj = 1, 998 .ss_chn_mask = 1, 999 .ss_nf_cal[0] = 0, 1000 .ss_nf_cal[1] = 0, 1001 .ss_nf_cal[2] = 0, 1002 .ss_nf_cal[3] = 0, 1003 .ss_nf_cal[4] = 0, 1004 .ss_nf_cal[5] = 0, 1005 .ss_nf_pwr[0] = 0, 1006 .ss_nf_pwr[1] = 0, 1007 .ss_nf_pwr[2] = 0, 1008 .ss_nf_pwr[3] = 0, 1009 .ss_nf_pwr[4] = 0, 1010 .ss_nf_pwr[5] = 0, 1011 .ss_nf_temp_data = 0, 1012 }; 1013 1014 #endif /* QCA_SUPPORT_SPECTRAL_SIMULATION */ 1015 #endif /* _SPECTRAL_SIM_INTERNAL_H_ */ 1016