1 /* 2 * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _REGTABLE_USB_H_ 20 #define _REGTABLE_USB_H_ 21 #include "if_usb.h" 22 23 #define MISSING 0 24 25 struct targetdef_s { 26 u_int32_t d_RTC_SOC_BASE_ADDRESS; 27 u_int32_t d_RTC_WMAC_BASE_ADDRESS; 28 u_int32_t d_SYSTEM_SLEEP_OFFSET; 29 u_int32_t d_WLAN_SYSTEM_SLEEP_OFFSET; 30 u_int32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB; 31 u_int32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK; 32 u_int32_t d_CLOCK_CONTROL_OFFSET; 33 u_int32_t d_CLOCK_CONTROL_SI0_CLK_MASK; 34 u_int32_t d_RESET_CONTROL_OFFSET; 35 u_int32_t d_RESET_CONTROL_MBOX_RST_MASK; 36 u_int32_t d_RESET_CONTROL_SI0_RST_MASK; 37 u_int32_t d_WLAN_RESET_CONTROL_OFFSET; 38 u_int32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK; 39 u_int32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK; 40 u_int32_t d_GPIO_BASE_ADDRESS; 41 u_int32_t d_GPIO_PIN0_OFFSET; 42 u_int32_t d_GPIO_PIN1_OFFSET; 43 u_int32_t d_GPIO_PIN0_CONFIG_MASK; 44 u_int32_t d_GPIO_PIN1_CONFIG_MASK; 45 u_int32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB; 46 u_int32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK; 47 u_int32_t d_SI_CONFIG_I2C_LSB; 48 u_int32_t d_SI_CONFIG_I2C_MASK; 49 u_int32_t d_SI_CONFIG_POS_SAMPLE_LSB; 50 u_int32_t d_SI_CONFIG_POS_SAMPLE_MASK; 51 u_int32_t d_SI_CONFIG_INACTIVE_CLK_LSB; 52 u_int32_t d_SI_CONFIG_INACTIVE_CLK_MASK; 53 u_int32_t d_SI_CONFIG_INACTIVE_DATA_LSB; 54 u_int32_t d_SI_CONFIG_INACTIVE_DATA_MASK; 55 u_int32_t d_SI_CONFIG_DIVIDER_LSB; 56 u_int32_t d_SI_CONFIG_DIVIDER_MASK; 57 u_int32_t d_SI_BASE_ADDRESS; 58 u_int32_t d_SI_CONFIG_OFFSET; 59 u_int32_t d_SI_TX_DATA0_OFFSET; 60 u_int32_t d_SI_TX_DATA1_OFFSET; 61 u_int32_t d_SI_RX_DATA0_OFFSET; 62 u_int32_t d_SI_RX_DATA1_OFFSET; 63 u_int32_t d_SI_CS_OFFSET; 64 u_int32_t d_SI_CS_DONE_ERR_MASK; 65 u_int32_t d_SI_CS_DONE_INT_MASK; 66 u_int32_t d_SI_CS_START_LSB; 67 u_int32_t d_SI_CS_START_MASK; 68 u_int32_t d_SI_CS_RX_CNT_LSB; 69 u_int32_t d_SI_CS_RX_CNT_MASK; 70 u_int32_t d_SI_CS_TX_CNT_LSB; 71 u_int32_t d_SI_CS_TX_CNT_MASK; 72 u_int32_t d_BOARD_DATA_SZ; 73 u_int32_t d_BOARD_EXT_DATA_SZ; 74 u_int32_t d_MBOX_BASE_ADDRESS; 75 u_int32_t d_LOCAL_SCRATCH_OFFSET; 76 u_int32_t d_CPU_CLOCK_OFFSET; 77 u_int32_t d_LPO_CAL_OFFSET; 78 u_int32_t d_GPIO_PIN10_OFFSET; 79 u_int32_t d_GPIO_PIN11_OFFSET; 80 u_int32_t d_GPIO_PIN12_OFFSET; 81 u_int32_t d_GPIO_PIN13_OFFSET; 82 u_int32_t d_CLOCK_GPIO_OFFSET; 83 u_int32_t d_CPU_CLOCK_STANDARD_LSB; 84 u_int32_t d_CPU_CLOCK_STANDARD_MASK; 85 u_int32_t d_LPO_CAL_ENABLE_LSB; 86 u_int32_t d_LPO_CAL_ENABLE_MASK; 87 u_int32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB; 88 u_int32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK; 89 u_int32_t d_ANALOG_INTF_BASE_ADDRESS; 90 u_int32_t d_WLAN_MAC_BASE_ADDRESS; 91 u_int32_t d_CE0_BASE_ADDRESS; 92 u_int32_t d_CE1_BASE_ADDRESS; 93 u_int32_t d_FW_INDICATOR_ADDRESS; 94 u_int32_t d_DRAM_BASE_ADDRESS; 95 u_int32_t d_SOC_CORE_BASE_ADDRESS; 96 u_int32_t d_CORE_CTRL_ADDRESS; 97 u_int32_t d_CE_COUNT; 98 u_int32_t d_MSI_NUM_REQUEST; 99 u_int32_t d_MSI_ASSIGN_FW; 100 u_int32_t d_MSI_ASSIGN_CE_INITIAL; 101 u_int32_t d_PCIE_INTR_ENABLE_ADDRESS; 102 u_int32_t d_PCIE_INTR_CLR_ADDRESS; 103 u_int32_t d_PCIE_INTR_FIRMWARE_MASK; 104 u_int32_t d_PCIE_INTR_CE_MASK_ALL; 105 u_int32_t d_CORE_CTRL_CPU_INTR_MASK; 106 u_int32_t d_SR_WR_INDEX_ADDRESS; 107 u_int32_t d_DST_WATERMARK_ADDRESS; 108 109 /* htt_rx.c */ 110 u_int32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK; 111 u_int32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB; 112 uint32_t d_RX_MPDU_START_0_RETRY_LSB; 113 uint32_t d_RX_MPDU_START_0_RETRY_MASK; 114 u_int32_t d_RX_MPDU_START_0_SEQ_NUM_MASK; 115 u_int32_t d_RX_MPDU_START_0_SEQ_NUM_LSB; 116 u_int32_t d_RX_MPDU_START_2_PN_47_32_LSB; 117 u_int32_t d_RX_MPDU_START_2_PN_47_32_MASK; 118 uint32_t d_RX_MPDU_START_2_TID_LSB; 119 uint32_t d_RX_MPDU_START_2_TID_MASK; 120 u_int32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK; 121 u_int32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB; 122 u_int32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK; 123 u_int32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB; 124 u_int32_t d_RX_MSDU_END_4_LAST_MSDU_MASK; 125 u_int32_t d_RX_MSDU_END_4_LAST_MSDU_LSB; 126 u_int32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK; 127 u_int32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB; 128 u_int32_t d_RX_ATTENTION_0_FRAGMENT_MASK; 129 u_int32_t d_RX_ATTENTION_0_FRAGMENT_LSB; 130 u_int32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK; 131 u_int32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK; 132 u_int32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB; 133 u_int32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK; 134 u_int32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB; 135 u_int32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET; 136 u_int32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK; 137 u_int32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB; 138 u_int32_t d_RX_MPDU_START_0_ENCRYPTED_MASK; 139 u_int32_t d_RX_MPDU_START_0_ENCRYPTED_LSB; 140 u_int32_t d_RX_ATTENTION_0_MORE_DATA_MASK; 141 u_int32_t d_RX_ATTENTION_0_MSDU_DONE_MASK; 142 u_int32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK; 143 /* end */ 144 /* copy_engine.c */ 145 u_int32_t d_DST_WR_INDEX_ADDRESS; 146 u_int32_t d_SRC_WATERMARK_ADDRESS; 147 u_int32_t d_SRC_WATERMARK_LOW_MASK; 148 u_int32_t d_SRC_WATERMARK_HIGH_MASK; 149 u_int32_t d_DST_WATERMARK_LOW_MASK; 150 u_int32_t d_DST_WATERMARK_HIGH_MASK; 151 u_int32_t d_CURRENT_SRRI_ADDRESS; 152 u_int32_t d_CURRENT_DRRI_ADDRESS; 153 u_int32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK; 154 u_int32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK; 155 u_int32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK; 156 u_int32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK; 157 u_int32_t d_HOST_IS_ADDRESS; 158 u_int32_t d_HOST_IS_COPY_COMPLETE_MASK; 159 u_int32_t d_CE_WRAPPER_BASE_ADDRESS; 160 u_int32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS; 161 u_int32_t d_HOST_IE_ADDRESS; 162 u_int32_t d_HOST_IE_COPY_COMPLETE_MASK; 163 u_int32_t d_SR_BA_ADDRESS; 164 u_int32_t d_SR_SIZE_ADDRESS; 165 u_int32_t d_CE_CTRL1_ADDRESS; 166 u_int32_t d_CE_CTRL1_DMAX_LENGTH_MASK; 167 u_int32_t d_DR_BA_ADDRESS; 168 u_int32_t d_DR_SIZE_ADDRESS; 169 u_int32_t d_MISC_IE_ADDRESS; 170 u_int32_t d_MISC_IS_AXI_ERR_MASK; 171 u_int32_t d_MISC_IS_DST_ADDR_ERR_MASK; 172 u_int32_t d_MISC_IS_SRC_LEN_ERR_MASK; 173 u_int32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK; 174 u_int32_t d_MISC_IS_DST_RING_OVERFLOW_MASK; 175 u_int32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK; 176 u_int32_t d_SRC_WATERMARK_LOW_LSB; 177 u_int32_t d_SRC_WATERMARK_HIGH_LSB; 178 u_int32_t d_DST_WATERMARK_LOW_LSB; 179 u_int32_t d_DST_WATERMARK_HIGH_LSB; 180 u_int32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK; 181 u_int32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB; 182 u_int32_t d_CE_CTRL1_DMAX_LENGTH_LSB; 183 u_int32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK; 184 u_int32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK; 185 u_int32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB; 186 u_int32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB; 187 u_int32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET; 188 u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB; 189 u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB; 190 u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK; 191 u_int32_t d_WLAN_DEBUG_CONTROL_OFFSET; 192 u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB; 193 u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB; 194 u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK; 195 u_int32_t d_WLAN_DEBUG_OUT_OFFSET; 196 u_int32_t d_WLAN_DEBUG_OUT_DATA_MSB; 197 u_int32_t d_WLAN_DEBUG_OUT_DATA_LSB; 198 u_int32_t d_WLAN_DEBUG_OUT_DATA_MASK; 199 u_int32_t d_AMBA_DEBUG_BUS_OFFSET; 200 u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB; 201 u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB; 202 u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK; 203 u_int32_t d_AMBA_DEBUG_BUS_SEL_MSB; 204 u_int32_t d_AMBA_DEBUG_BUS_SEL_LSB; 205 u_int32_t d_AMBA_DEBUG_BUS_SEL_MASK; 206 u_int32_t d_CE_WRAPPER_DEBUG_OFFSET; 207 u_int32_t d_CE_WRAPPER_DEBUG_SEL_MSB; 208 u_int32_t d_CE_WRAPPER_DEBUG_SEL_LSB; 209 u_int32_t d_CE_WRAPPER_DEBUG_SEL_MASK; 210 u_int32_t d_CE_DEBUG_OFFSET; 211 u_int32_t d_CE_DEBUG_SEL_MSB; 212 u_int32_t d_CE_DEBUG_SEL_LSB; 213 u_int32_t d_CE_DEBUG_SEL_MASK; 214 /* end */ 215 /* PLL start */ 216 u_int32_t d_EFUSE_OFFSET; 217 u_int32_t d_EFUSE_XTAL_SEL_MSB; 218 u_int32_t d_EFUSE_XTAL_SEL_LSB; 219 u_int32_t d_EFUSE_XTAL_SEL_MASK; 220 u_int32_t d_BB_PLL_CONFIG_OFFSET; 221 u_int32_t d_BB_PLL_CONFIG_OUTDIV_MSB; 222 u_int32_t d_BB_PLL_CONFIG_OUTDIV_LSB; 223 u_int32_t d_BB_PLL_CONFIG_OUTDIV_MASK; 224 u_int32_t d_BB_PLL_CONFIG_FRAC_MSB; 225 u_int32_t d_BB_PLL_CONFIG_FRAC_LSB; 226 u_int32_t d_BB_PLL_CONFIG_FRAC_MASK; 227 u_int32_t d_WLAN_PLL_SETTLE_TIME_MSB; 228 u_int32_t d_WLAN_PLL_SETTLE_TIME_LSB; 229 u_int32_t d_WLAN_PLL_SETTLE_TIME_MASK; 230 u_int32_t d_WLAN_PLL_SETTLE_OFFSET; 231 u_int32_t d_WLAN_PLL_SETTLE_SW_MASK; 232 u_int32_t d_WLAN_PLL_SETTLE_RSTMASK; 233 u_int32_t d_WLAN_PLL_SETTLE_RESET; 234 u_int32_t d_WLAN_PLL_CONTROL_NOPWD_MSB; 235 u_int32_t d_WLAN_PLL_CONTROL_NOPWD_LSB; 236 u_int32_t d_WLAN_PLL_CONTROL_NOPWD_MASK; 237 u_int32_t d_WLAN_PLL_CONTROL_BYPASS_MSB; 238 u_int32_t d_WLAN_PLL_CONTROL_BYPASS_LSB; 239 u_int32_t d_WLAN_PLL_CONTROL_BYPASS_MASK; 240 u_int32_t d_WLAN_PLL_CONTROL_BYPASS_RESET; 241 u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB; 242 u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB; 243 u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK; 244 u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET; 245 u_int32_t d_WLAN_PLL_CONTROL_REFDIV_MSB; 246 u_int32_t d_WLAN_PLL_CONTROL_REFDIV_LSB; 247 u_int32_t d_WLAN_PLL_CONTROL_REFDIV_MASK; 248 u_int32_t d_WLAN_PLL_CONTROL_REFDIV_RESET; 249 u_int32_t d_WLAN_PLL_CONTROL_DIV_MSB; 250 u_int32_t d_WLAN_PLL_CONTROL_DIV_LSB; 251 u_int32_t d_WLAN_PLL_CONTROL_DIV_MASK; 252 u_int32_t d_WLAN_PLL_CONTROL_DIV_RESET; 253 u_int32_t d_WLAN_PLL_CONTROL_OFFSET; 254 u_int32_t d_WLAN_PLL_CONTROL_SW_MASK; 255 u_int32_t d_WLAN_PLL_CONTROL_RSTMASK; 256 u_int32_t d_WLAN_PLL_CONTROL_RESET; 257 u_int32_t d_SOC_CORE_CLK_CTRL_OFFSET; 258 u_int32_t d_SOC_CORE_CLK_CTRL_DIV_MSB; 259 u_int32_t d_SOC_CORE_CLK_CTRL_DIV_LSB; 260 u_int32_t d_SOC_CORE_CLK_CTRL_DIV_MASK; 261 u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB; 262 u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB; 263 u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK; 264 u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET; 265 u_int32_t d_RTC_SYNC_STATUS_OFFSET; 266 u_int32_t d_SOC_CPU_CLOCK_OFFSET; 267 u_int32_t d_SOC_CPU_CLOCK_STANDARD_MSB; 268 u_int32_t d_SOC_CPU_CLOCK_STANDARD_LSB; 269 u_int32_t d_SOC_CPU_CLOCK_STANDARD_MASK; 270 /* PLL end */ 271 u_int32_t d_SOC_POWER_REG_OFFSET; 272 u_int32_t d_PCIE_INTR_CAUSE_ADDRESS; 273 u_int32_t d_SOC_RESET_CONTROL_ADDRESS; 274 u_int32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK; 275 u_int32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB; 276 u_int32_t d_SOC_RESET_CONTROL_CE_RST_MASK; 277 u_int32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK; 278 u_int32_t d_CPU_INTR_ADDRESS; 279 u_int32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS; 280 u_int32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK; 281 u_int32_t d_SOC_LF_TIMER_STATUS0_ADDRESS; 282 /* chip id start */ 283 u_int32_t d_SOC_CHIP_ID_ADDRESS; 284 u_int32_t d_SOC_CHIP_ID_VERSION_MASK; 285 u_int32_t d_SOC_CHIP_ID_VERSION_LSB; 286 u_int32_t d_SOC_CHIP_ID_REVISION_MASK; 287 u_int32_t d_SOC_CHIP_ID_REVISION_LSB; 288 /* chip id end */ 289 }; 290 291 #define RTC_SOC_BASE_ADDRESS \ 292 (scn->targetdef->d_RTC_SOC_BASE_ADDRESS) 293 #define RTC_WMAC_BASE_ADDRESS \ 294 (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS) 295 #define SYSTEM_SLEEP_OFFSET \ 296 (scn->targetdef->d_SYSTEM_SLEEP_OFFSET) 297 #define WLAN_SYSTEM_SLEEP_OFFSET \ 298 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET) 299 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB \ 300 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB) 301 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK \ 302 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK) 303 #define CLOCK_CONTROL_OFFSET \ 304 (scn->targetdef->d_CLOCK_CONTROL_OFFSET) 305 #define CLOCK_CONTROL_SI0_CLK_MASK \ 306 (scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK) 307 #define RESET_CONTROL_OFFSET \ 308 (scn->targetdef->d_RESET_CONTROL_OFFSET) 309 #define RESET_CONTROL_MBOX_RST_MASK \ 310 (scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK) 311 #define RESET_CONTROL_SI0_RST_MASK \ 312 (scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK) 313 #define WLAN_RESET_CONTROL_OFFSET \ 314 (scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET) 315 #define WLAN_RESET_CONTROL_COLD_RST_MASK \ 316 (scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK) 317 #define WLAN_RESET_CONTROL_WARM_RST_MASK \ 318 (scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK) 319 #define GPIO_BASE_ADDRESS \ 320 (scn->targetdef->d_GPIO_BASE_ADDRESS) 321 #define GPIO_PIN0_OFFSET \ 322 (scn->targetdef->d_GPIO_PIN0_OFFSET) 323 #define GPIO_PIN1_OFFSET \ 324 (scn->targetdef->d_GPIO_PIN1_OFFSET) 325 #define GPIO_PIN0_CONFIG_MASK \ 326 (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK) 327 #define GPIO_PIN1_CONFIG_MASK \ 328 (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK) 329 #define SI_CONFIG_BIDIR_OD_DATA_LSB \ 330 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB) 331 #define SI_CONFIG_BIDIR_OD_DATA_MASK \ 332 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK) 333 #define SI_CONFIG_I2C_LSB \ 334 (scn->targetdef->d_SI_CONFIG_I2C_LSB) 335 #define SI_CONFIG_I2C_MASK \ 336 (scn->targetdef->d_SI_CONFIG_I2C_MASK) 337 #define SI_CONFIG_POS_SAMPLE_LSB \ 338 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB) 339 #define SI_CONFIG_POS_SAMPLE_MASK \ 340 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK) 341 #define SI_CONFIG_INACTIVE_CLK_LSB \ 342 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB) 343 #define SI_CONFIG_INACTIVE_CLK_MASK \ 344 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK) 345 #define SI_CONFIG_INACTIVE_DATA_LSB \ 346 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB) 347 #define SI_CONFIG_INACTIVE_DATA_MASK \ 348 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK) 349 #define SI_CONFIG_DIVIDER_LSB \ 350 (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB) 351 #define SI_CONFIG_DIVIDER_MASK \ 352 (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK) 353 #define SI_BASE_ADDRESS \ 354 (scn->targetdef->d_SI_BASE_ADDRESS) 355 #define SI_CONFIG_OFFSET \ 356 (scn->targetdef->d_SI_CONFIG_OFFSET) 357 #define SI_TX_DATA0_OFFSET \ 358 (scn->targetdef->d_SI_TX_DATA0_OFFSET) 359 #define SI_TX_DATA1_OFFSET \ 360 (scn->targetdef->d_SI_TX_DATA1_OFFSET) 361 #define SI_RX_DATA0_OFFSET \ 362 (scn->targetdef->d_SI_RX_DATA0_OFFSET) 363 #define SI_RX_DATA1_OFFSET \ 364 (scn->targetdef->d_SI_RX_DATA1_OFFSET) 365 #define SI_CS_OFFSET \ 366 (scn->targetdef->d_SI_CS_OFFSET) 367 #define SI_CS_DONE_ERR_MASK \ 368 (scn->targetdef->d_SI_CS_DONE_ERR_MASK) 369 #define SI_CS_DONE_INT_MASK \ 370 (scn->targetdef->d_SI_CS_DONE_INT_MASK) 371 #define SI_CS_START_LSB \ 372 (scn->targetdef->d_SI_CS_START_LSB) 373 #define SI_CS_START_MASK \ 374 (scn->targetdef->d_SI_CS_START_MASK) 375 #define SI_CS_RX_CNT_LSB \ 376 (scn->targetdef->d_SI_CS_RX_CNT_LSB) 377 #define SI_CS_RX_CNT_MASK \ 378 (scn->targetdef->d_SI_CS_RX_CNT_MASK) 379 #define SI_CS_TX_CNT_LSB \ 380 (scn->targetdef->d_SI_CS_TX_CNT_LSB) 381 #define SI_CS_TX_CNT_MASK \ 382 (scn->targetdef->d_SI_CS_TX_CNT_MASK) 383 #define EEPROM_SZ \ 384 (scn->targetdef->d_BOARD_DATA_SZ) 385 #define EEPROM_EXT_SZ \ 386 (scn->targetdef->d_BOARD_EXT_DATA_SZ) 387 #define MBOX_BASE_ADDRESS \ 388 (scn->targetdef->d_MBOX_BASE_ADDRESS) 389 #define LOCAL_SCRATCH_OFFSET \ 390 (scn->targetdef->d_LOCAL_SCRATCH_OFFSET) 391 #define CPU_CLOCK_OFFSET \ 392 (scn->targetdef->d_CPU_CLOCK_OFFSET) 393 #define LPO_CAL_OFFSET \ 394 (scn->targetdef->d_LPO_CAL_OFFSET) 395 #define GPIO_PIN10_OFFSET \ 396 (scn->targetdef->d_GPIO_PIN10_OFFSET) 397 #define GPIO_PIN11_OFFSET \ 398 (scn->targetdef->d_GPIO_PIN11_OFFSET) 399 #define GPIO_PIN12_OFFSET \ 400 (scn->targetdef->d_GPIO_PIN12_OFFSET) 401 #define GPIO_PIN13_OFFSET \ 402 (scn->targetdef->d_GPIO_PIN13_OFFSET) 403 #define CLOCK_GPIO_OFFSET \ 404 (scn->targetdef->d_CLOCK_GPIO_OFFSET) 405 #define CPU_CLOCK_STANDARD_LSB \ 406 (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB) 407 #define CPU_CLOCK_STANDARD_MASK \ 408 (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK) 409 #define LPO_CAL_ENABLE_LSB \ 410 (scn->targetdef->d_LPO_CAL_ENABLE_LSB) 411 #define LPO_CAL_ENABLE_MASK \ 412 (scn->targetdef->d_LPO_CAL_ENABLE_MASK) 413 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \ 414 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB) 415 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \ 416 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 417 #define ANALOG_INTF_BASE_ADDRESS \ 418 (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS) 419 #define WLAN_MAC_BASE_ADDRESS \ 420 (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS) 421 #define CE0_BASE_ADDRESS \ 422 (scn->targetdef->d_CE0_BASE_ADDRESS) 423 #define CE1_BASE_ADDRESS \ 424 (scn->targetdef->d_CE1_BASE_ADDRESS) 425 #define FW_INDICATOR_ADDRESS \ 426 (scn->targetdef->d_FW_INDICATOR_ADDRESS) 427 #define DRAM_BASE_ADDRESS \ 428 (scn->targetdef->d_DRAM_BASE_ADDRESS) 429 #define SOC_CORE_BASE_ADDRESS \ 430 (scn->targetdef->d_SOC_CORE_BASE_ADDRESS) 431 #define CORE_CTRL_ADDRESS \ 432 (scn->targetdef->d_CORE_CTRL_ADDRESS) 433 #define CE_COUNT \ 434 (scn->targetdef->d_CE_COUNT) 435 #define PCIE_INTR_ENABLE_ADDRESS \ 436 (scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS) 437 #define PCIE_INTR_CLR_ADDRESS \ 438 (scn->targetdef->d_PCIE_INTR_CLR_ADDRESS) 439 #define PCIE_INTR_FIRMWARE_MASK \ 440 (scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK) 441 #define PCIE_INTR_CE_MASK_ALL \ 442 (scn->targetdef->d_PCIE_INTR_CE_MASK_ALL) 443 #define CORE_CTRL_CPU_INTR_MASK \ 444 (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK) 445 #define PCIE_INTR_CAUSE_ADDRESS \ 446 (scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS) 447 #define SOC_RESET_CONTROL_ADDRESS \ 448 (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS) 449 #define SOC_RESET_CONTROL_CE_RST_MASK \ 450 (scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK) 451 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK\ 452 (scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK) 453 #define CPU_INTR_ADDRESS \ 454 (scn->targetdef->d_CPU_INTR_ADDRESS) 455 #define SOC_LF_TIMER_CONTROL0_ADDRESS \ 456 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS) 457 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \ 458 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK) 459 #define SOC_LF_TIMER_STATUS0_ADDRESS \ 460 (scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS) 461 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB \ 462 (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) 463 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK \ 464 (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) 465 466 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) \ 467 (((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> \ 468 SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) 469 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) \ 470 (((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & \ 471 SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) 472 473 /* hif_pci.c */ 474 #define CHIP_ID_ADDRESS \ 475 (scn->targetdef->d_SOC_CHIP_ID_ADDRESS) 476 #define SOC_CHIP_ID_REVISION_MASK \ 477 (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK) 478 #define SOC_CHIP_ID_REVISION_LSB \ 479 (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB) 480 #define SOC_CHIP_ID_VERSION_MASK \ 481 (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK) 482 #define SOC_CHIP_ID_VERSION_LSB \ 483 (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB) 484 #define CHIP_ID_REVISION_GET(x) \ 485 (((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB) 486 #define CHIP_ID_VERSION_GET(x) \ 487 (((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB) 488 /* hif_pci.c end */ 489 490 /* misc */ 491 #define SR_WR_INDEX_ADDRESS \ 492 (scn->targetdef->d_SR_WR_INDEX_ADDRESS) 493 #define DST_WATERMARK_ADDRESS \ 494 (scn->targetdef->d_DST_WATERMARK_ADDRESS) 495 #define SOC_POWER_REG_OFFSET \ 496 (scn->targetdef->d_SOC_POWER_REG_OFFSET) 497 /* end */ 498 499 /* htt_rx.c */ 500 #define RX_MSDU_END_4_FIRST_MSDU_MASK \ 501 (pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_MASK) 502 #define RX_MSDU_END_4_FIRST_MSDU_LSB \ 503 (pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_LSB) 504 #define RX_MPDU_START_0_RETRY_LSB \ 505 (pdev->targetdef->d_RX_MPDU_START_0_RETRY_LSB) 506 #define RX_MPDU_START_0_RETRY_MASK \ 507 (pdev->targetdef->d_RX_MPDU_START_0_RETRY_MASK) 508 #define RX_MPDU_START_0_SEQ_NUM_MASK \ 509 (pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_MASK) 510 #define RX_MPDU_START_0_SEQ_NUM_LSB \ 511 (pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_LSB) 512 #define RX_MPDU_START_2_PN_47_32_LSB \ 513 (pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_LSB) 514 #define RX_MPDU_START_2_PN_47_32_MASK \ 515 (pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_MASK) 516 #define RX_MPDU_START_2_TID_LSB \ 517 (pdev->targetdef->d_RX_MPDU_START_2_TID_LSB) 518 #define RX_MPDU_START_2_TID_MASK \ 519 (pdev->targetdef->d_RX_MPDU_START_2_TID_MASK) 520 #define RX_MSDU_END_1_KEY_ID_OCT_MASK \ 521 (pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_MASK) 522 #define RX_MSDU_END_1_KEY_ID_OCT_LSB \ 523 (pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_LSB) 524 #define RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK \ 525 (pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK) 526 #define RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB\ 527 (pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB) 528 #define RX_MSDU_END_4_LAST_MSDU_MASK \ 529 (pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_MASK) 530 #define RX_MSDU_END_4_LAST_MSDU_LSB \ 531 (pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_LSB) 532 #define RX_ATTENTION_0_MCAST_BCAST_MASK \ 533 (pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_MASK) 534 #define RX_ATTENTION_0_MCAST_BCAST_LSB \ 535 (pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_LSB) 536 #define RX_ATTENTION_0_FRAGMENT_MASK \ 537 (pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_MASK) 538 #define RX_ATTENTION_0_FRAGMENT_LSB \ 539 (pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_LSB) 540 #define RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK\ 541 (pdev->targetdef->d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK) 542 #define RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK \ 543 (pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK) 544 #define RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB\ 545 (pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB) 546 #define RX_MSDU_START_0_MSDU_LENGTH_MASK \ 547 (pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_MASK) 548 #define RX_MSDU_START_0_MSDU_LENGTH_LSB \ 549 (pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_LSB) 550 #define RX_MSDU_START_2_DECAP_FORMAT_OFFSET\ 551 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET) 552 #define RX_MSDU_START_2_DECAP_FORMAT_MASK \ 553 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_MASK) 554 #define RX_MSDU_START_2_DECAP_FORMAT_LSB \ 555 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_LSB) 556 #define RX_MPDU_START_0_ENCRYPTED_MASK \ 557 (pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_MASK) 558 #define RX_MPDU_START_0_ENCRYPTED_LSB \ 559 (pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_LSB) 560 #define RX_ATTENTION_0_MORE_DATA_MASK \ 561 (pdev->targetdef->d_RX_ATTENTION_0_MORE_DATA_MASK) 562 #define RX_ATTENTION_0_MSDU_DONE_MASK \ 563 (pdev->targetdef->d_RX_ATTENTION_0_MSDU_DONE_MASK) 564 #define RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK \ 565 (pdev->targetdef->d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK) 566 /* end */ 567 568 /* copy_engine.c */ 569 #define DST_WR_INDEX_ADDRESS \ 570 (scn->targetdef->d_DST_WR_INDEX_ADDRESS) 571 #define SRC_WATERMARK_ADDRESS \ 572 (scn->targetdef->d_SRC_WATERMARK_ADDRESS) 573 #define SRC_WATERMARK_LOW_MASK \ 574 (scn->targetdef->d_SRC_WATERMARK_LOW_MASK) 575 #define SRC_WATERMARK_HIGH_MASK \ 576 (scn->targetdef->d_SRC_WATERMARK_HIGH_MASK) 577 #define DST_WATERMARK_LOW_MASK \ 578 (scn->targetdef->d_DST_WATERMARK_LOW_MASK) 579 #define DST_WATERMARK_HIGH_MASK \ 580 (scn->targetdef->d_DST_WATERMARK_HIGH_MASK) 581 #define CURRENT_SRRI_ADDRESS \ 582 (scn->targetdef->d_CURRENT_SRRI_ADDRESS) 583 #define CURRENT_DRRI_ADDRESS \ 584 (scn->targetdef->d_CURRENT_DRRI_ADDRESS) 585 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \ 586 (scn->targetdef->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK) 587 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK\ 588 (scn->targetdef->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK) 589 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK \ 590 (scn->targetdef->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK) 591 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK\ 592 (scn->targetdef->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK) 593 #define HOST_IS_ADDRESS \ 594 (scn->targetdef->d_HOST_IS_ADDRESS) 595 #define HOST_IS_COPY_COMPLETE_MASK \ 596 (scn->targetdef->d_HOST_IS_COPY_COMPLETE_MASK) 597 #define CE_WRAPPER_BASE_ADDRESS \ 598 (scn->targetdef->d_CE_WRAPPER_BASE_ADDRESS) 599 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS \ 600 (scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS) 601 #define HOST_IE_ADDRESS \ 602 (scn->targetdef->d_HOST_IE_ADDRESS) 603 #define HOST_IE_COPY_COMPLETE_MASK \ 604 (scn->targetdef->d_HOST_IE_COPY_COMPLETE_MASK) 605 #define SR_BA_ADDRESS \ 606 (scn->targetdef->d_SR_BA_ADDRESS) 607 #define SR_SIZE_ADDRESS \ 608 (scn->targetdef->d_SR_SIZE_ADDRESS) 609 #define CE_CTRL1_ADDRESS \ 610 (scn->targetdef->d_CE_CTRL1_ADDRESS) 611 #define CE_CTRL1_DMAX_LENGTH_MASK \ 612 (scn->targetdef->d_CE_CTRL1_DMAX_LENGTH_MASK) 613 #define DR_BA_ADDRESS \ 614 (scn->targetdef->d_DR_BA_ADDRESS) 615 #define DR_SIZE_ADDRESS \ 616 (scn->targetdef->d_DR_SIZE_ADDRESS) 617 #define MISC_IE_ADDRESS \ 618 (scn->targetdef->d_MISC_IE_ADDRESS) 619 #define MISC_IS_AXI_ERR_MASK \ 620 (scn->targetdef->d_MISC_IS_AXI_ERR_MASK) 621 #define MISC_IS_DST_ADDR_ERR_MASK \ 622 (scn->targetdef->d_MISC_IS_DST_ADDR_ERR_MASK) 623 #define MISC_IS_SRC_LEN_ERR_MASK \ 624 (scn->targetdef->d_MISC_IS_SRC_LEN_ERR_MASK) 625 #define MISC_IS_DST_MAX_LEN_VIO_MASK \ 626 (scn->targetdef->d_MISC_IS_DST_MAX_LEN_VIO_MASK) 627 #define MISC_IS_DST_RING_OVERFLOW_MASK \ 628 (scn->targetdef->d_MISC_IS_DST_RING_OVERFLOW_MASK) 629 #define MISC_IS_SRC_RING_OVERFLOW_MASK \ 630 (scn->targetdef->d_MISC_IS_SRC_RING_OVERFLOW_MASK) 631 #define SRC_WATERMARK_LOW_LSB \ 632 (scn->targetdef->d_SRC_WATERMARK_LOW_LSB) 633 #define SRC_WATERMARK_HIGH_LSB \ 634 (scn->targetdef->d_SRC_WATERMARK_HIGH_LSB) 635 #define DST_WATERMARK_LOW_LSB \ 636 (scn->targetdef->d_DST_WATERMARK_LOW_LSB) 637 #define DST_WATERMARK_HIGH_LSB \ 638 (scn->targetdef->d_DST_WATERMARK_HIGH_LSB) 639 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \ 640 (scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) 641 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ 642 (scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 643 #define CE_CTRL1_DMAX_LENGTH_LSB \ 644 (scn->targetdef->d_CE_CTRL1_DMAX_LENGTH_LSB) 645 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK\ 646 (scn->targetdef->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 647 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK\ 648 (scn->targetdef->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 649 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \ 650 (scn->targetdef->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) 651 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \ 652 (scn->targetdef->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) 653 #define WLAN_DEBUG_INPUT_SEL_OFFSET \ 654 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET) 655 #define WLAN_DEBUG_INPUT_SEL_SRC_MSB \ 656 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB) 657 #define WLAN_DEBUG_INPUT_SEL_SRC_LSB \ 658 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB) 659 #define WLAN_DEBUG_INPUT_SEL_SRC_MASK \ 660 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK) 661 #define WLAN_DEBUG_CONTROL_OFFSET \ 662 (scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET) 663 #define WLAN_DEBUG_CONTROL_ENABLE_MSB \ 664 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB) 665 #define WLAN_DEBUG_CONTROL_ENABLE_LSB \ 666 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB) 667 #define WLAN_DEBUG_CONTROL_ENABLE_MASK \ 668 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK) 669 #define WLAN_DEBUG_OUT_OFFSET \ 670 (scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET) 671 #define WLAN_DEBUG_OUT_DATA_MSB \ 672 (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB) 673 #define WLAN_DEBUG_OUT_DATA_LSB \ 674 (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB) 675 #define WLAN_DEBUG_OUT_DATA_MASK \ 676 (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK) 677 #define AMBA_DEBUG_BUS_OFFSET \ 678 (scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET) 679 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB \ 680 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB) 681 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB \ 682 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) 683 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK \ 684 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) 685 #define AMBA_DEBUG_BUS_SEL_MSB \ 686 (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB) 687 #define AMBA_DEBUG_BUS_SEL_LSB \ 688 (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB) 689 #define AMBA_DEBUG_BUS_SEL_MASK \ 690 (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK) 691 #define CE_WRAPPER_DEBUG_OFFSET \ 692 (scn->targetdef->d_CE_WRAPPER_DEBUG_OFFSET) 693 #define CE_WRAPPER_DEBUG_SEL_MSB \ 694 (scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_MSB) 695 #define CE_WRAPPER_DEBUG_SEL_LSB \ 696 (scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_LSB) 697 #define CE_WRAPPER_DEBUG_SEL_MASK \ 698 (scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_MASK) 699 #define CE_DEBUG_OFFSET \ 700 (scn->targetdef->d_CE_DEBUG_OFFSET) 701 #define CE_DEBUG_SEL_MSB \ 702 (scn->targetdef->d_CE_DEBUG_SEL_MSB) 703 #define CE_DEBUG_SEL_LSB \ 704 (scn->targetdef->d_CE_DEBUG_SEL_LSB) 705 #define CE_DEBUG_SEL_MASK \ 706 (scn->targetdef->d_CE_DEBUG_SEL_MASK) 707 /* end */ 708 /* PLL start */ 709 #define EFUSE_OFFSET \ 710 (scn->targetdef->d_EFUSE_OFFSET) 711 #define EFUSE_XTAL_SEL_MSB \ 712 (scn->targetdef->d_EFUSE_XTAL_SEL_MSB) 713 #define EFUSE_XTAL_SEL_LSB \ 714 (scn->targetdef->d_EFUSE_XTAL_SEL_LSB) 715 #define EFUSE_XTAL_SEL_MASK \ 716 (scn->targetdef->d_EFUSE_XTAL_SEL_MASK) 717 #define BB_PLL_CONFIG_OFFSET \ 718 (scn->targetdef->d_BB_PLL_CONFIG_OFFSET) 719 #define BB_PLL_CONFIG_OUTDIV_MSB \ 720 (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB) 721 #define BB_PLL_CONFIG_OUTDIV_LSB \ 722 (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB) 723 #define BB_PLL_CONFIG_OUTDIV_MASK \ 724 (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK) 725 #define BB_PLL_CONFIG_FRAC_MSB \ 726 (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB) 727 #define BB_PLL_CONFIG_FRAC_LSB \ 728 (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB) 729 #define BB_PLL_CONFIG_FRAC_MASK \ 730 (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK) 731 #define WLAN_PLL_SETTLE_TIME_MSB \ 732 (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB) 733 #define WLAN_PLL_SETTLE_TIME_LSB \ 734 (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB) 735 #define WLAN_PLL_SETTLE_TIME_MASK \ 736 (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK) 737 #define WLAN_PLL_SETTLE_OFFSET \ 738 (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET) 739 #define WLAN_PLL_SETTLE_SW_MASK \ 740 (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK) 741 #define WLAN_PLL_SETTLE_RSTMASK \ 742 (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK) 743 #define WLAN_PLL_SETTLE_RESET \ 744 (scn->targetdef->d_WLAN_PLL_SETTLE_RESET) 745 #define WLAN_PLL_CONTROL_NOPWD_MSB \ 746 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB) 747 #define WLAN_PLL_CONTROL_NOPWD_LSB \ 748 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB) 749 #define WLAN_PLL_CONTROL_NOPWD_MASK \ 750 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK) 751 #define WLAN_PLL_CONTROL_BYPASS_MSB \ 752 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB) 753 #define WLAN_PLL_CONTROL_BYPASS_LSB \ 754 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB) 755 #define WLAN_PLL_CONTROL_BYPASS_MASK \ 756 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK) 757 #define WLAN_PLL_CONTROL_BYPASS_RESET \ 758 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET) 759 #define WLAN_PLL_CONTROL_CLK_SEL_MSB \ 760 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB) 761 #define WLAN_PLL_CONTROL_CLK_SEL_LSB \ 762 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB) 763 #define WLAN_PLL_CONTROL_CLK_SEL_MASK \ 764 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK) 765 #define WLAN_PLL_CONTROL_CLK_SEL_RESET \ 766 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET) 767 #define WLAN_PLL_CONTROL_REFDIV_MSB \ 768 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB) 769 #define WLAN_PLL_CONTROL_REFDIV_LSB \ 770 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB) 771 #define WLAN_PLL_CONTROL_REFDIV_MASK \ 772 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK) 773 #define WLAN_PLL_CONTROL_REFDIV_RESET \ 774 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET) 775 #define WLAN_PLL_CONTROL_DIV_MSB \ 776 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB) 777 #define WLAN_PLL_CONTROL_DIV_LSB \ 778 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB) 779 #define WLAN_PLL_CONTROL_DIV_MASK \ 780 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK) 781 #define WLAN_PLL_CONTROL_DIV_RESET \ 782 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET) 783 #define WLAN_PLL_CONTROL_OFFSET \ 784 (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET) 785 #define WLAN_PLL_CONTROL_SW_MASK \ 786 (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK) 787 #define WLAN_PLL_CONTROL_RSTMASK \ 788 (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK) 789 #define WLAN_PLL_CONTROL_RESET \ 790 (scn->targetdef->d_WLAN_PLL_CONTROL_RESET) 791 #define SOC_CORE_CLK_CTRL_OFFSET \ 792 (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET) 793 #define SOC_CORE_CLK_CTRL_DIV_MSB \ 794 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB) 795 #define SOC_CORE_CLK_CTRL_DIV_LSB \ 796 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB) 797 #define SOC_CORE_CLK_CTRL_DIV_MASK \ 798 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK) 799 #define RTC_SYNC_STATUS_PLL_CHANGING_MSB \ 800 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB) 801 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB \ 802 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB) 803 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK \ 804 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK) 805 #define RTC_SYNC_STATUS_PLL_CHANGING_RESET \ 806 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET) 807 #define RTC_SYNC_STATUS_OFFSET \ 808 (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET) 809 #define SOC_CPU_CLOCK_OFFSET \ 810 (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET) 811 #define SOC_CPU_CLOCK_STANDARD_MSB \ 812 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB) 813 #define SOC_CPU_CLOCK_STANDARD_LSB \ 814 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB) 815 #define SOC_CPU_CLOCK_STANDARD_MASK \ 816 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK) 817 /* PLL end */ 818 819 /* SET macros */ 820 #define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \ 821 (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \ 822 WLAN_SYSTEM_SLEEP_DISABLE_MASK) 823 #define SI_CONFIG_BIDIR_OD_DATA_SET(x) \ 824 (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & \ 825 SI_CONFIG_BIDIR_OD_DATA_MASK) 826 #define SI_CONFIG_I2C_SET(x) \ 827 (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) 828 #define SI_CONFIG_POS_SAMPLE_SET(x) \ 829 (((x) << SI_CONFIG_POS_SAMPLE_LSB) & \ 830 SI_CONFIG_POS_SAMPLE_MASK) 831 #define SI_CONFIG_INACTIVE_CLK_SET(x) \ 832 (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & \ 833 SI_CONFIG_INACTIVE_CLK_MASK) 834 #define SI_CONFIG_INACTIVE_DATA_SET(x) \ 835 (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & \ 836 SI_CONFIG_INACTIVE_DATA_MASK) 837 #define SI_CONFIG_DIVIDER_SET(x) \ 838 (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) 839 #define SI_CS_START_SET(x) \ 840 (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) 841 #define SI_CS_RX_CNT_SET(x) \ 842 (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) 843 #define SI_CS_TX_CNT_SET(x) \ 844 (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) 845 #define LPO_CAL_ENABLE_SET(x) \ 846 (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) 847 #define CPU_CLOCK_STANDARD_SET(x) \ 848 (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) 849 #define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \ 850 (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & \ 851 CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 852 /* copy_engine.c */ 853 #define SRC_WATERMARK_LOW_SET(x) \ 854 (((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK) 855 #define SRC_WATERMARK_HIGH_SET(x) \ 856 (((x) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK) 857 #define DST_WATERMARK_LOW_SET(x) \ 858 (((x) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK) 859 #define DST_WATERMARK_HIGH_SET(x) \ 860 (((x) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK) 861 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) (((x) & \ 862 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \ 863 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 864 #define CE_CTRL1_DMAX_LENGTH_SET(x) \ 865 (((x) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK) 866 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \ 867 (((x) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \ 868 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 869 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \ 870 (((x) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \ 871 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 872 #define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) \ 873 (((x) & \ 874 WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> \ 875 WLAN_DEBUG_INPUT_SEL_SRC_LSB) 876 #define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) \ 877 (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & \ 878 WLAN_DEBUG_INPUT_SEL_SRC_MASK) 879 #define WLAN_DEBUG_CONTROL_ENABLE_GET(x) \ 880 (((x) & \ 881 WLAN_DEBUG_CONTROL_ENABLE_MASK) >> \ 882 WLAN_DEBUG_CONTROL_ENABLE_LSB) 883 #define WLAN_DEBUG_CONTROL_ENABLE_SET(x) \ 884 (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & \ 885 WLAN_DEBUG_CONTROL_ENABLE_MASK) 886 #define WLAN_DEBUG_OUT_DATA_GET(x) \ 887 (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB) 888 #define WLAN_DEBUG_OUT_DATA_SET(x) \ 889 (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK) 890 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_GET(x) \ 891 (((x) & \ 892 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) >> \ 893 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) 894 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(x) \ 895 (((x) << AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) & \ 896 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) 897 #define AMBA_DEBUG_BUS_SEL_GET(x) \ 898 (((x) & AMBA_DEBUG_BUS_SEL_MASK) >> AMBA_DEBUG_BUS_SEL_LSB) 899 #define AMBA_DEBUG_BUS_SEL_SET(x) \ 900 (((x) << AMBA_DEBUG_BUS_SEL_LSB) & AMBA_DEBUG_BUS_SEL_MASK) 901 #define CE_WRAPPER_DEBUG_SEL_GET(x) \ 902 (((x) & CE_WRAPPER_DEBUG_SEL_MASK) >> CE_WRAPPER_DEBUG_SEL_LSB) 903 #define CE_WRAPPER_DEBUG_SEL_SET(x) \ 904 (((x) << CE_WRAPPER_DEBUG_SEL_LSB) & CE_WRAPPER_DEBUG_SEL_MASK) 905 #define CE_DEBUG_SEL_GET(x) \ 906 (((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB) 907 #define CE_DEBUG_SEL_SET(x) \ 908 (((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK) 909 /* end */ 910 /* PLL start */ 911 #define EFUSE_XTAL_SEL_GET(x) \ 912 (((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB) 913 #define EFUSE_XTAL_SEL_SET(x) \ 914 (((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK) 915 #define BB_PLL_CONFIG_OUTDIV_GET(x) \ 916 (((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB) 917 #define BB_PLL_CONFIG_OUTDIV_SET(x) \ 918 (((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK) 919 #define BB_PLL_CONFIG_FRAC_GET(x) \ 920 (((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB) 921 #define BB_PLL_CONFIG_FRAC_SET(x) \ 922 (((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK) 923 #define WLAN_PLL_SETTLE_TIME_GET(x) \ 924 (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB) 925 #define WLAN_PLL_SETTLE_TIME_SET(x) \ 926 (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK) 927 #define WLAN_PLL_CONTROL_NOPWD_GET(x) \ 928 (((x) & \ 929 WLAN_PLL_CONTROL_NOPWD_MASK) >> \ 930 WLAN_PLL_CONTROL_NOPWD_LSB) 931 #define WLAN_PLL_CONTROL_NOPWD_SET(x) \ 932 (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & \ 933 WLAN_PLL_CONTROL_NOPWD_MASK) 934 #define WLAN_PLL_CONTROL_BYPASS_GET(x) \ 935 (((x) & \ 936 WLAN_PLL_CONTROL_BYPASS_MASK) >> \ 937 WLAN_PLL_CONTROL_BYPASS_LSB) 938 #define WLAN_PLL_CONTROL_BYPASS_SET(x) \ 939 (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & \ 940 WLAN_PLL_CONTROL_BYPASS_MASK) 941 #define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \ 942 (((x) & \ 943 WLAN_PLL_CONTROL_CLK_SEL_MASK) >> \ 944 WLAN_PLL_CONTROL_CLK_SEL_LSB) 945 #define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \ 946 (((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & \ 947 WLAN_PLL_CONTROL_CLK_SEL_MASK) 948 #define WLAN_PLL_CONTROL_REFDIV_GET(x) \ 949 (((x) & \ 950 WLAN_PLL_CONTROL_REFDIV_MASK) >> \ 951 WLAN_PLL_CONTROL_REFDIV_LSB) 952 #define WLAN_PLL_CONTROL_REFDIV_SET(x) \ 953 (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & \ 954 WLAN_PLL_CONTROL_REFDIV_MASK) 955 #define WLAN_PLL_CONTROL_DIV_GET(x) \ 956 (((x) & \ 957 WLAN_PLL_CONTROL_DIV_MASK) >> \ 958 WLAN_PLL_CONTROL_DIV_LSB) 959 #define WLAN_PLL_CONTROL_DIV_SET(x) \ 960 (((x) << WLAN_PLL_CONTROL_DIV_LSB) & \ 961 WLAN_PLL_CONTROL_DIV_MASK) 962 #define SOC_CORE_CLK_CTRL_DIV_GET(x) \ 963 (((x) & \ 964 SOC_CORE_CLK_CTRL_DIV_MASK) >> \ 965 SOC_CORE_CLK_CTRL_DIV_LSB) 966 #define SOC_CORE_CLK_CTRL_DIV_SET(x) \ 967 (((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & \ 968 SOC_CORE_CLK_CTRL_DIV_MASK) 969 #define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \ 970 (((x) & \ 971 RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \ 972 RTC_SYNC_STATUS_PLL_CHANGING_LSB) 973 #define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \ 974 (((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \ 975 RTC_SYNC_STATUS_PLL_CHANGING_MASK) 976 #define SOC_CPU_CLOCK_STANDARD_GET(x) \ 977 (((x) & \ 978 SOC_CPU_CLOCK_STANDARD_MASK) >> \ 979 SOC_CPU_CLOCK_STANDARD_LSB) 980 #define SOC_CPU_CLOCK_STANDARD_SET(x) \ 981 (((x) << SOC_CPU_CLOCK_STANDARD_LSB) & \ 982 SOC_CPU_CLOCK_STANDARD_MASK) 983 /* PLL end */ 984 985 struct hostdef_s { 986 uint32_t d_INT_STATUS_ENABLE_ERROR_LSB; 987 uint32_t d_INT_STATUS_ENABLE_ERROR_MASK; 988 uint32_t d_INT_STATUS_ENABLE_CPU_LSB; 989 uint32_t d_INT_STATUS_ENABLE_CPU_MASK; 990 uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB; 991 uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK; 992 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB; 993 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK; 994 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB; 995 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK; 996 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB; 997 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK; 998 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB; 999 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK; 1000 uint32_t d_INT_STATUS_ENABLE_ADDRESS; 1001 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB; 1002 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK; 1003 uint32_t d_HOST_INT_STATUS_ADDRESS; 1004 uint32_t d_CPU_INT_STATUS_ADDRESS; 1005 uint32_t d_ERROR_INT_STATUS_ADDRESS; 1006 uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK; 1007 uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB; 1008 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK; 1009 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB; 1010 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK; 1011 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB; 1012 uint32_t d_COUNT_DEC_ADDRESS; 1013 uint32_t d_HOST_INT_STATUS_CPU_MASK; 1014 uint32_t d_HOST_INT_STATUS_CPU_LSB; 1015 uint32_t d_HOST_INT_STATUS_ERROR_MASK; 1016 uint32_t d_HOST_INT_STATUS_ERROR_LSB; 1017 uint32_t d_HOST_INT_STATUS_COUNTER_MASK; 1018 uint32_t d_HOST_INT_STATUS_COUNTER_LSB; 1019 uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS; 1020 uint32_t d_WINDOW_DATA_ADDRESS; 1021 uint32_t d_WINDOW_READ_ADDR_ADDRESS; 1022 uint32_t d_WINDOW_WRITE_ADDR_ADDRESS; 1023 uint32_t d_SOC_GLOBAL_RESET_ADDRESS; 1024 uint32_t d_RTC_STATE_ADDRESS; 1025 uint32_t d_RTC_STATE_COLD_RESET_MASK; 1026 uint32_t d_PCIE_LOCAL_BASE_ADDRESS; 1027 uint32_t d_PCIE_SOC_WAKE_RESET; 1028 uint32_t d_PCIE_SOC_WAKE_ADDRESS; 1029 uint32_t d_PCIE_SOC_WAKE_V_MASK; 1030 uint32_t d_RTC_STATE_V_MASK; 1031 uint32_t d_RTC_STATE_V_LSB; 1032 uint32_t d_FW_IND_EVENT_PENDING; 1033 uint32_t d_FW_IND_INITIALIZED; 1034 uint32_t d_RTC_STATE_V_ON; 1035 #if defined(SDIO_3_0) 1036 uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK; 1037 uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB; 1038 #endif 1039 uint32_t d_PCIE_SOC_RDY_STATUS_ADDRESS; 1040 uint32_t d_PCIE_SOC_RDY_STATUS_BAR_MASK; 1041 uint32_t d_SOC_PCIE_BASE_ADDRESS; 1042 uint32_t d_MSI_MAGIC_ADR_ADDRESS; 1043 uint32_t d_MSI_MAGIC_ADDRESS; 1044 }; 1045 1046 #define INT_STATUS_ENABLE_ERROR_LSB \ 1047 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB) 1048 #define INT_STATUS_ENABLE_ERROR_MASK \ 1049 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK) 1050 #define INT_STATUS_ENABLE_CPU_LSB \ 1051 (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB) 1052 #define INT_STATUS_ENABLE_CPU_MASK \ 1053 (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK) 1054 #define INT_STATUS_ENABLE_COUNTER_LSB \ 1055 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB) 1056 #define INT_STATUS_ENABLE_COUNTER_MASK \ 1057 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK) 1058 #define INT_STATUS_ENABLE_MBOX_DATA_LSB \ 1059 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB) 1060 #define INT_STATUS_ENABLE_MBOX_DATA_MASK \ 1061 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK) 1062 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \ 1063 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) 1064 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \ 1065 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 1066 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB\ 1067 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) 1068 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \ 1069 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 1070 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB \ 1071 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB) 1072 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK \ 1073 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK) 1074 #define INT_STATUS_ENABLE_ADDRESS \ 1075 (scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS) 1076 #define CPU_INT_STATUS_ENABLE_BIT_LSB \ 1077 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB) 1078 #define CPU_INT_STATUS_ENABLE_BIT_MASK \ 1079 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK) 1080 #define HOST_INT_STATUS_ADDRESS \ 1081 (scn->hostdef->d_HOST_INT_STATUS_ADDRESS) 1082 #define CPU_INT_STATUS_ADDRESS \ 1083 (scn->hostdef->d_CPU_INT_STATUS_ADDRESS) 1084 #define ERROR_INT_STATUS_ADDRESS \ 1085 (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS) 1086 #define ERROR_INT_STATUS_WAKEUP_MASK \ 1087 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK) 1088 #define ERROR_INT_STATUS_WAKEUP_LSB \ 1089 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB) 1090 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \ 1091 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK) 1092 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \ 1093 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 1094 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK \ 1095 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK) 1096 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB \ 1097 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB) 1098 #define COUNT_DEC_ADDRESS \ 1099 (scn->hostdef->d_COUNT_DEC_ADDRESS) 1100 #define HOST_INT_STATUS_CPU_MASK \ 1101 (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK) 1102 #define HOST_INT_STATUS_CPU_LSB \ 1103 (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB) 1104 #define HOST_INT_STATUS_ERROR_MASK \ 1105 (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK) 1106 #define HOST_INT_STATUS_ERROR_LSB \ 1107 (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB) 1108 #define HOST_INT_STATUS_COUNTER_MASK \ 1109 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK) 1110 #define HOST_INT_STATUS_COUNTER_LSB \ 1111 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB) 1112 #define RX_LOOKAHEAD_VALID_ADDRESS \ 1113 (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS) 1114 #define WINDOW_DATA_ADDRESS \ 1115 (scn->hostdef->d_WINDOW_DATA_ADDRESS) 1116 #define WINDOW_READ_ADDR_ADDRESS \ 1117 (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS) 1118 #define WINDOW_WRITE_ADDR_ADDRESS \ 1119 (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS) 1120 #define SOC_GLOBAL_RESET_ADDRESS \ 1121 (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS) 1122 #define RTC_STATE_ADDRESS \ 1123 (scn->hostdef->d_RTC_STATE_ADDRESS) 1124 #define RTC_STATE_COLD_RESET_MASK \ 1125 (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK) 1126 #define PCIE_LOCAL_BASE_ADDRESS \ 1127 (scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS) 1128 #define PCIE_SOC_WAKE_RESET \ 1129 (scn->hostdef->d_PCIE_SOC_WAKE_RESET) 1130 #define PCIE_SOC_WAKE_ADDRESS \ 1131 (scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS) 1132 #define PCIE_SOC_WAKE_V_MASK \ 1133 (scn->hostdef->d_PCIE_SOC_WAKE_V_MASK) 1134 #define RTC_STATE_V_MASK \ 1135 (scn->hostdef->d_RTC_STATE_V_MASK) 1136 #define RTC_STATE_V_LSB \ 1137 (scn->hostdef->d_RTC_STATE_V_LSB) 1138 #define FW_IND_EVENT_PENDING \ 1139 (scn->hostdef->d_FW_IND_EVENT_PENDING) 1140 #define FW_IND_INITIALIZED \ 1141 (scn->hostdef->d_FW_IND_INITIALIZED) 1142 #define RTC_STATE_V_ON \ 1143 (scn->hostdef->d_RTC_STATE_V_ON) 1144 #if defined(SDIO_3_0) 1145 #define HOST_INT_STATUS_MBOX_DATA_MASK \ 1146 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK) 1147 #define HOST_INT_STATUS_MBOX_DATA_LSB \ 1148 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB) 1149 #endif 1150 1151 #if !defined(SOC_PCIE_BASE_ADDRESS) 1152 #define SOC_PCIE_BASE_ADDRESS 0 1153 #endif 1154 1155 #if !defined(PCIE_SOC_RDY_STATUS_ADDRESS) 1156 #define PCIE_SOC_RDY_STATUS_ADDRESS 0 1157 #define PCIE_SOC_RDY_STATUS_BAR_MASK 0 1158 #endif 1159 1160 #if !defined(MSI_MAGIC_ADR_ADDRESS) 1161 #define MSI_MAGIC_ADR_ADDRESS 0 1162 #define MSI_MAGIC_ADDRESS 0 1163 #endif 1164 1165 /* SET/GET macros */ 1166 #define INT_STATUS_ENABLE_ERROR_SET(x) \ 1167 (((x) << INT_STATUS_ENABLE_ERROR_LSB) & \ 1168 INT_STATUS_ENABLE_ERROR_MASK) 1169 #define INT_STATUS_ENABLE_CPU_SET(x) \ 1170 (((x) << INT_STATUS_ENABLE_CPU_LSB) & \ 1171 INT_STATUS_ENABLE_CPU_MASK) 1172 #define INT_STATUS_ENABLE_COUNTER_SET(x) \ 1173 (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \ 1174 INT_STATUS_ENABLE_COUNTER_MASK) 1175 #define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \ 1176 (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \ 1177 INT_STATUS_ENABLE_MBOX_DATA_MASK) 1178 #define CPU_INT_STATUS_ENABLE_BIT_SET(x) \ 1179 (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \ 1180 CPU_INT_STATUS_ENABLE_BIT_MASK) 1181 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \ 1182 (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \ 1183 ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 1184 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x)\ 1185 (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \ 1186 ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 1187 #define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \ 1188 (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \ 1189 COUNTER_INT_STATUS_ENABLE_BIT_MASK) 1190 #define ERROR_INT_STATUS_WAKEUP_GET(x) \ 1191 (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \ 1192 ERROR_INT_STATUS_WAKEUP_LSB) 1193 #define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \ 1194 (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \ 1195 ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 1196 #define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \ 1197 (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \ 1198 ERROR_INT_STATUS_TX_OVERFLOW_LSB) 1199 #define HOST_INT_STATUS_CPU_GET(x) \ 1200 (((x) & HOST_INT_STATUS_CPU_MASK) >> \ 1201 HOST_INT_STATUS_CPU_LSB) 1202 #define HOST_INT_STATUS_ERROR_GET(x) \ 1203 (((x) & HOST_INT_STATUS_ERROR_MASK) >> \ 1204 HOST_INT_STATUS_ERROR_LSB) 1205 #define HOST_INT_STATUS_COUNTER_GET(x) \ 1206 (((x) & HOST_INT_STATUS_COUNTER_MASK) >> \ 1207 HOST_INT_STATUS_COUNTER_LSB) 1208 #define RTC_STATE_V_GET(x) \ 1209 (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 1210 #if defined(SDIO_3_0) 1211 #define HOST_INT_STATUS_MBOX_DATA_GET(x) \ 1212 (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \ 1213 HOST_INT_STATUS_MBOX_DATA_LSB) 1214 #endif 1215 1216 #define INVALID_REG_LOC_DUMMY_DATA 0xAA 1217 1218 1219 1220 #define ROME_USB_RTC_SOC_BASE_ADDRESS 0x00000800 1221 #define ROME_USB_SOC_RESET_CONTROL_COLD_RST_LSB 0x0 1222 #define SOC_RESET_CONTROL_COLD_RST_LSB 8 1223 #define SOC_RESET_CONTROL_COLD_RST_MASK 0x00000100 1224 #define SOC_RESET_CONTROL_COLD_RST_SET(x) \ 1225 (((x) << SOC_RESET_CONTROL_COLD_RST_LSB) & \ 1226 SOC_RESET_CONTROL_COLD_RST_MASK) 1227 1228 #define AR6320_CORE_CLK_DIV_ADDR 0x403fa8 1229 #define AR6320_CPU_PLL_INIT_DONE_ADDR 0x403fd0 1230 #define AR6320_CPU_SPEED_ADDR 0x403fa4 1231 #define AR6320V2_CORE_CLK_DIV_ADDR 0x403fd8 1232 #define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0 1233 #define AR6320V2_CPU_SPEED_ADDR 0x403fd4 1234 #define AR6320V3_CORE_CLK_DIV_ADDR 0x404028 1235 #define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020 1236 #define AR6320V3_CPU_SPEED_ADDR 0x404024 1237 1238 enum a_refclk_speed_t { 1239 /* Unsupported ref clock -- use PLL Bypass */ 1240 SOC_REFCLK_UNKNOWN = -1, 1241 SOC_REFCLK_48_MHZ = 0, 1242 SOC_REFCLK_19_2_MHZ = 1, 1243 SOC_REFCLK_24_MHZ = 2, 1244 SOC_REFCLK_26_MHZ = 3, 1245 SOC_REFCLK_37_4_MHZ = 4, 1246 SOC_REFCLK_38_4_MHZ = 5, 1247 SOC_REFCLK_40_MHZ = 6, 1248 SOC_REFCLK_52_MHZ = 7, 1249 }; 1250 1251 #define A_REFCLK_UNKNOWN SOC_REFCLK_UNKNOWN 1252 #define A_REFCLK_48_MHZ SOC_REFCLK_48_MHZ 1253 #define A_REFCLK_19_2_MHZ SOC_REFCLK_19_2_MHZ 1254 #define A_REFCLK_24_MHZ SOC_REFCLK_24_MHZ 1255 #define A_REFCLK_26_MHZ SOC_REFCLK_26_MHZ 1256 #define A_REFCLK_37_4_MHZ SOC_REFCLK_37_4_MHZ 1257 #define A_REFCLK_38_4_MHZ SOC_REFCLK_38_4_MHZ 1258 #define A_REFCLK_40_MHZ SOC_REFCLK_40_MHZ 1259 #define A_REFCLK_52_MHZ SOC_REFCLK_52_MHZ 1260 1261 #define TARGET_CPU_FREQ 176000000 1262 1263 struct wlan_pll_s { 1264 u_int32_t refdiv; 1265 u_int32_t div; 1266 u_int32_t rnfrac; 1267 u_int32_t outdiv; 1268 }; 1269 1270 struct cmnos_clock_s { 1271 enum a_refclk_speed_t refclk_speed; 1272 u_int32_t refclk_hz; 1273 u_int32_t pll_settling_time; /* 50us */ 1274 struct wlan_pll_s wlan_pll; 1275 }; 1276 1277 struct tgt_reg_section { 1278 u_int32_t start_addr; 1279 u_int32_t end_addr; 1280 }; 1281 1282 struct tgt_reg_table { 1283 const struct tgt_reg_section *section; 1284 u_int32_t section_size; 1285 }; 1286 1287 void target_register_tbl_attach(struct hif_softc *scn, 1288 uint32_t target_type); 1289 void hif_register_tbl_attach(struct hif_softc *scn, 1290 uint32_t target_type); 1291 #endif 1292