1 /* 2 * Copyright (c) 2013-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _REGTABLE_USB_H_ 20 #define _REGTABLE_USB_H_ 21 #include "if_usb.h" 22 23 #define MISSING 0 24 25 struct targetdef_s { 26 u_int32_t d_RTC_SOC_BASE_ADDRESS; 27 u_int32_t d_RTC_WMAC_BASE_ADDRESS; 28 u_int32_t d_SYSTEM_SLEEP_OFFSET; 29 u_int32_t d_WLAN_SYSTEM_SLEEP_OFFSET; 30 u_int32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB; 31 u_int32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK; 32 u_int32_t d_CLOCK_CONTROL_OFFSET; 33 u_int32_t d_CLOCK_CONTROL_SI0_CLK_MASK; 34 u_int32_t d_RESET_CONTROL_OFFSET; 35 u_int32_t d_RESET_CONTROL_MBOX_RST_MASK; 36 u_int32_t d_RESET_CONTROL_SI0_RST_MASK; 37 u_int32_t d_WLAN_RESET_CONTROL_OFFSET; 38 u_int32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK; 39 u_int32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK; 40 u_int32_t d_GPIO_BASE_ADDRESS; 41 u_int32_t d_GPIO_PIN0_OFFSET; 42 u_int32_t d_GPIO_PIN1_OFFSET; 43 u_int32_t d_GPIO_PIN0_CONFIG_MASK; 44 u_int32_t d_GPIO_PIN1_CONFIG_MASK; 45 u_int32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB; 46 u_int32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK; 47 u_int32_t d_SI_CONFIG_I2C_LSB; 48 u_int32_t d_SI_CONFIG_I2C_MASK; 49 u_int32_t d_SI_CONFIG_POS_SAMPLE_LSB; 50 u_int32_t d_SI_CONFIG_POS_SAMPLE_MASK; 51 u_int32_t d_SI_CONFIG_INACTIVE_CLK_LSB; 52 u_int32_t d_SI_CONFIG_INACTIVE_CLK_MASK; 53 u_int32_t d_SI_CONFIG_INACTIVE_DATA_LSB; 54 u_int32_t d_SI_CONFIG_INACTIVE_DATA_MASK; 55 u_int32_t d_SI_CONFIG_DIVIDER_LSB; 56 u_int32_t d_SI_CONFIG_DIVIDER_MASK; 57 u_int32_t d_SI_BASE_ADDRESS; 58 u_int32_t d_SI_CONFIG_OFFSET; 59 u_int32_t d_SI_TX_DATA0_OFFSET; 60 u_int32_t d_SI_TX_DATA1_OFFSET; 61 u_int32_t d_SI_RX_DATA0_OFFSET; 62 u_int32_t d_SI_RX_DATA1_OFFSET; 63 u_int32_t d_SI_CS_OFFSET; 64 u_int32_t d_SI_CS_DONE_ERR_MASK; 65 u_int32_t d_SI_CS_DONE_INT_MASK; 66 u_int32_t d_SI_CS_START_LSB; 67 u_int32_t d_SI_CS_START_MASK; 68 u_int32_t d_SI_CS_RX_CNT_LSB; 69 u_int32_t d_SI_CS_RX_CNT_MASK; 70 u_int32_t d_SI_CS_TX_CNT_LSB; 71 u_int32_t d_SI_CS_TX_CNT_MASK; 72 u_int32_t d_BOARD_DATA_SZ; 73 u_int32_t d_BOARD_EXT_DATA_SZ; 74 u_int32_t d_MBOX_BASE_ADDRESS; 75 u_int32_t d_LOCAL_SCRATCH_OFFSET; 76 u_int32_t d_CPU_CLOCK_OFFSET; 77 u_int32_t d_LPO_CAL_OFFSET; 78 u_int32_t d_GPIO_PIN10_OFFSET; 79 u_int32_t d_GPIO_PIN11_OFFSET; 80 u_int32_t d_GPIO_PIN12_OFFSET; 81 u_int32_t d_GPIO_PIN13_OFFSET; 82 u_int32_t d_CLOCK_GPIO_OFFSET; 83 u_int32_t d_CPU_CLOCK_STANDARD_LSB; 84 u_int32_t d_CPU_CLOCK_STANDARD_MASK; 85 u_int32_t d_LPO_CAL_ENABLE_LSB; 86 u_int32_t d_LPO_CAL_ENABLE_MASK; 87 u_int32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB; 88 u_int32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK; 89 u_int32_t d_ANALOG_INTF_BASE_ADDRESS; 90 u_int32_t d_WLAN_MAC_BASE_ADDRESS; 91 u_int32_t d_CE0_BASE_ADDRESS; 92 u_int32_t d_CE1_BASE_ADDRESS; 93 u_int32_t d_FW_INDICATOR_ADDRESS; 94 u_int32_t d_DRAM_BASE_ADDRESS; 95 u_int32_t d_SOC_CORE_BASE_ADDRESS; 96 u_int32_t d_CORE_CTRL_ADDRESS; 97 u_int32_t d_CE_COUNT; 98 u_int32_t d_MSI_NUM_REQUEST; 99 u_int32_t d_MSI_ASSIGN_FW; 100 u_int32_t d_MSI_ASSIGN_CE_INITIAL; 101 u_int32_t d_PCIE_INTR_ENABLE_ADDRESS; 102 u_int32_t d_PCIE_INTR_CLR_ADDRESS; 103 u_int32_t d_PCIE_INTR_FIRMWARE_MASK; 104 u_int32_t d_PCIE_INTR_CE_MASK_ALL; 105 u_int32_t d_CORE_CTRL_CPU_INTR_MASK; 106 u_int32_t d_SR_WR_INDEX_ADDRESS; 107 u_int32_t d_DST_WATERMARK_ADDRESS; 108 109 /* htt_rx.c */ 110 u_int32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK; 111 u_int32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB; 112 uint32_t d_RX_MPDU_START_0_RETRY_LSB; 113 uint32_t d_RX_MPDU_START_0_RETRY_MASK; 114 u_int32_t d_RX_MPDU_START_0_SEQ_NUM_MASK; 115 u_int32_t d_RX_MPDU_START_0_SEQ_NUM_LSB; 116 u_int32_t d_RX_MPDU_START_2_PN_47_32_LSB; 117 u_int32_t d_RX_MPDU_START_2_PN_47_32_MASK; 118 uint32_t d_RX_MPDU_START_2_TID_LSB; 119 uint32_t d_RX_MPDU_START_2_TID_MASK; 120 u_int32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK; 121 u_int32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB; 122 u_int32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK; 123 u_int32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB; 124 u_int32_t d_RX_MSDU_END_4_LAST_MSDU_MASK; 125 u_int32_t d_RX_MSDU_END_4_LAST_MSDU_LSB; 126 u_int32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK; 127 u_int32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB; 128 u_int32_t d_RX_ATTENTION_0_FRAGMENT_MASK; 129 u_int32_t d_RX_ATTENTION_0_FRAGMENT_LSB; 130 u_int32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK; 131 u_int32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK; 132 u_int32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB; 133 u_int32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK; 134 u_int32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB; 135 u_int32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET; 136 u_int32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK; 137 u_int32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB; 138 u_int32_t d_RX_MPDU_START_0_ENCRYPTED_MASK; 139 u_int32_t d_RX_MPDU_START_0_ENCRYPTED_LSB; 140 u_int32_t d_RX_ATTENTION_0_MORE_DATA_MASK; 141 u_int32_t d_RX_ATTENTION_0_MSDU_DONE_MASK; 142 u_int32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK; 143 /* end */ 144 /* copy_engine.c */ 145 u_int32_t d_DST_WR_INDEX_ADDRESS; 146 u_int32_t d_SRC_WATERMARK_ADDRESS; 147 u_int32_t d_SRC_WATERMARK_LOW_MASK; 148 u_int32_t d_SRC_WATERMARK_HIGH_MASK; 149 u_int32_t d_DST_WATERMARK_LOW_MASK; 150 u_int32_t d_DST_WATERMARK_HIGH_MASK; 151 u_int32_t d_CURRENT_SRRI_ADDRESS; 152 u_int32_t d_CURRENT_DRRI_ADDRESS; 153 u_int32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK; 154 u_int32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK; 155 u_int32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK; 156 u_int32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK; 157 u_int32_t d_HOST_IS_ADDRESS; 158 u_int32_t d_HOST_IS_COPY_COMPLETE_MASK; 159 u_int32_t d_CE_WRAPPER_BASE_ADDRESS; 160 u_int32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS; 161 u_int32_t d_HOST_IE_ADDRESS; 162 u_int32_t d_HOST_IE_COPY_COMPLETE_MASK; 163 u_int32_t d_SR_BA_ADDRESS; 164 u_int32_t d_SR_SIZE_ADDRESS; 165 u_int32_t d_CE_CTRL1_ADDRESS; 166 u_int32_t d_CE_CTRL1_DMAX_LENGTH_MASK; 167 u_int32_t d_DR_BA_ADDRESS; 168 u_int32_t d_DR_SIZE_ADDRESS; 169 u_int32_t d_MISC_IE_ADDRESS; 170 u_int32_t d_MISC_IS_AXI_ERR_MASK; 171 u_int32_t d_MISC_IS_DST_ADDR_ERR_MASK; 172 u_int32_t d_MISC_IS_SRC_LEN_ERR_MASK; 173 u_int32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK; 174 u_int32_t d_MISC_IS_DST_RING_OVERFLOW_MASK; 175 u_int32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK; 176 u_int32_t d_SRC_WATERMARK_LOW_LSB; 177 u_int32_t d_SRC_WATERMARK_HIGH_LSB; 178 u_int32_t d_DST_WATERMARK_LOW_LSB; 179 u_int32_t d_DST_WATERMARK_HIGH_LSB; 180 u_int32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK; 181 u_int32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB; 182 u_int32_t d_CE_CTRL1_DMAX_LENGTH_LSB; 183 u_int32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK; 184 u_int32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK; 185 u_int32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB; 186 u_int32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB; 187 u_int32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET; 188 u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB; 189 u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB; 190 u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK; 191 u_int32_t d_WLAN_DEBUG_CONTROL_OFFSET; 192 u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB; 193 u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB; 194 u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK; 195 u_int32_t d_WLAN_DEBUG_OUT_OFFSET; 196 u_int32_t d_WLAN_DEBUG_OUT_DATA_MSB; 197 u_int32_t d_WLAN_DEBUG_OUT_DATA_LSB; 198 u_int32_t d_WLAN_DEBUG_OUT_DATA_MASK; 199 u_int32_t d_AMBA_DEBUG_BUS_OFFSET; 200 u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB; 201 u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB; 202 u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK; 203 u_int32_t d_AMBA_DEBUG_BUS_SEL_MSB; 204 u_int32_t d_AMBA_DEBUG_BUS_SEL_LSB; 205 u_int32_t d_AMBA_DEBUG_BUS_SEL_MASK; 206 u_int32_t d_CE_WRAPPER_DEBUG_OFFSET; 207 u_int32_t d_CE_WRAPPER_DEBUG_SEL_MSB; 208 u_int32_t d_CE_WRAPPER_DEBUG_SEL_LSB; 209 u_int32_t d_CE_WRAPPER_DEBUG_SEL_MASK; 210 u_int32_t d_CE_DEBUG_OFFSET; 211 u_int32_t d_CE_DEBUG_SEL_MSB; 212 u_int32_t d_CE_DEBUG_SEL_LSB; 213 u_int32_t d_CE_DEBUG_SEL_MASK; 214 /* end */ 215 /* PLL start */ 216 u_int32_t d_EFUSE_OFFSET; 217 u_int32_t d_EFUSE_XTAL_SEL_MSB; 218 u_int32_t d_EFUSE_XTAL_SEL_LSB; 219 u_int32_t d_EFUSE_XTAL_SEL_MASK; 220 u_int32_t d_BB_PLL_CONFIG_OFFSET; 221 u_int32_t d_BB_PLL_CONFIG_OUTDIV_MSB; 222 u_int32_t d_BB_PLL_CONFIG_OUTDIV_LSB; 223 u_int32_t d_BB_PLL_CONFIG_OUTDIV_MASK; 224 u_int32_t d_BB_PLL_CONFIG_FRAC_MSB; 225 u_int32_t d_BB_PLL_CONFIG_FRAC_LSB; 226 u_int32_t d_BB_PLL_CONFIG_FRAC_MASK; 227 u_int32_t d_WLAN_PLL_SETTLE_TIME_MSB; 228 u_int32_t d_WLAN_PLL_SETTLE_TIME_LSB; 229 u_int32_t d_WLAN_PLL_SETTLE_TIME_MASK; 230 u_int32_t d_WLAN_PLL_SETTLE_OFFSET; 231 u_int32_t d_WLAN_PLL_SETTLE_SW_MASK; 232 u_int32_t d_WLAN_PLL_SETTLE_RSTMASK; 233 u_int32_t d_WLAN_PLL_SETTLE_RESET; 234 u_int32_t d_WLAN_PLL_CONTROL_NOPWD_MSB; 235 u_int32_t d_WLAN_PLL_CONTROL_NOPWD_LSB; 236 u_int32_t d_WLAN_PLL_CONTROL_NOPWD_MASK; 237 u_int32_t d_WLAN_PLL_CONTROL_BYPASS_MSB; 238 u_int32_t d_WLAN_PLL_CONTROL_BYPASS_LSB; 239 u_int32_t d_WLAN_PLL_CONTROL_BYPASS_MASK; 240 u_int32_t d_WLAN_PLL_CONTROL_BYPASS_RESET; 241 u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB; 242 u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB; 243 u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK; 244 u_int32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET; 245 u_int32_t d_WLAN_PLL_CONTROL_REFDIV_MSB; 246 u_int32_t d_WLAN_PLL_CONTROL_REFDIV_LSB; 247 u_int32_t d_WLAN_PLL_CONTROL_REFDIV_MASK; 248 u_int32_t d_WLAN_PLL_CONTROL_REFDIV_RESET; 249 u_int32_t d_WLAN_PLL_CONTROL_DIV_MSB; 250 u_int32_t d_WLAN_PLL_CONTROL_DIV_LSB; 251 u_int32_t d_WLAN_PLL_CONTROL_DIV_MASK; 252 u_int32_t d_WLAN_PLL_CONTROL_DIV_RESET; 253 u_int32_t d_WLAN_PLL_CONTROL_OFFSET; 254 u_int32_t d_WLAN_PLL_CONTROL_SW_MASK; 255 u_int32_t d_WLAN_PLL_CONTROL_RSTMASK; 256 u_int32_t d_WLAN_PLL_CONTROL_RESET; 257 u_int32_t d_SOC_CORE_CLK_CTRL_OFFSET; 258 u_int32_t d_SOC_CORE_CLK_CTRL_DIV_MSB; 259 u_int32_t d_SOC_CORE_CLK_CTRL_DIV_LSB; 260 u_int32_t d_SOC_CORE_CLK_CTRL_DIV_MASK; 261 u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB; 262 u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB; 263 u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK; 264 u_int32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET; 265 u_int32_t d_RTC_SYNC_STATUS_OFFSET; 266 u_int32_t d_SOC_CPU_CLOCK_OFFSET; 267 u_int32_t d_SOC_CPU_CLOCK_STANDARD_MSB; 268 u_int32_t d_SOC_CPU_CLOCK_STANDARD_LSB; 269 u_int32_t d_SOC_CPU_CLOCK_STANDARD_MASK; 270 /* PLL end */ 271 u_int32_t d_SOC_POWER_REG_OFFSET; 272 u_int32_t d_PCIE_INTR_CAUSE_ADDRESS; 273 u_int32_t d_SOC_RESET_CONTROL_ADDRESS; 274 u_int32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK; 275 u_int32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB; 276 u_int32_t d_SOC_RESET_CONTROL_CE_RST_MASK; 277 u_int32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK; 278 u_int32_t d_CPU_INTR_ADDRESS; 279 u_int32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS; 280 u_int32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK; 281 /* chip id start */ 282 u_int32_t d_SOC_CHIP_ID_ADDRESS; 283 u_int32_t d_SOC_CHIP_ID_VERSION_MASK; 284 u_int32_t d_SOC_CHIP_ID_VERSION_LSB; 285 u_int32_t d_SOC_CHIP_ID_REVISION_MASK; 286 u_int32_t d_SOC_CHIP_ID_REVISION_LSB; 287 /* chip id end */ 288 }; 289 290 #define RTC_SOC_BASE_ADDRESS \ 291 (scn->targetdef->d_RTC_SOC_BASE_ADDRESS) 292 #define RTC_WMAC_BASE_ADDRESS \ 293 (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS) 294 #define SYSTEM_SLEEP_OFFSET \ 295 (scn->targetdef->d_SYSTEM_SLEEP_OFFSET) 296 #define WLAN_SYSTEM_SLEEP_OFFSET \ 297 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET) 298 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB \ 299 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB) 300 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK \ 301 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK) 302 #define CLOCK_CONTROL_OFFSET \ 303 (scn->targetdef->d_CLOCK_CONTROL_OFFSET) 304 #define CLOCK_CONTROL_SI0_CLK_MASK \ 305 (scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK) 306 #define RESET_CONTROL_OFFSET \ 307 (scn->targetdef->d_RESET_CONTROL_OFFSET) 308 #define RESET_CONTROL_MBOX_RST_MASK \ 309 (scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK) 310 #define RESET_CONTROL_SI0_RST_MASK \ 311 (scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK) 312 #define WLAN_RESET_CONTROL_OFFSET \ 313 (scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET) 314 #define WLAN_RESET_CONTROL_COLD_RST_MASK \ 315 (scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK) 316 #define WLAN_RESET_CONTROL_WARM_RST_MASK \ 317 (scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK) 318 #define GPIO_BASE_ADDRESS \ 319 (scn->targetdef->d_GPIO_BASE_ADDRESS) 320 #define GPIO_PIN0_OFFSET \ 321 (scn->targetdef->d_GPIO_PIN0_OFFSET) 322 #define GPIO_PIN1_OFFSET \ 323 (scn->targetdef->d_GPIO_PIN1_OFFSET) 324 #define GPIO_PIN0_CONFIG_MASK \ 325 (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK) 326 #define GPIO_PIN1_CONFIG_MASK \ 327 (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK) 328 #define SI_CONFIG_BIDIR_OD_DATA_LSB \ 329 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB) 330 #define SI_CONFIG_BIDIR_OD_DATA_MASK \ 331 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK) 332 #define SI_CONFIG_I2C_LSB \ 333 (scn->targetdef->d_SI_CONFIG_I2C_LSB) 334 #define SI_CONFIG_I2C_MASK \ 335 (scn->targetdef->d_SI_CONFIG_I2C_MASK) 336 #define SI_CONFIG_POS_SAMPLE_LSB \ 337 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB) 338 #define SI_CONFIG_POS_SAMPLE_MASK \ 339 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK) 340 #define SI_CONFIG_INACTIVE_CLK_LSB \ 341 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB) 342 #define SI_CONFIG_INACTIVE_CLK_MASK \ 343 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK) 344 #define SI_CONFIG_INACTIVE_DATA_LSB \ 345 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB) 346 #define SI_CONFIG_INACTIVE_DATA_MASK \ 347 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK) 348 #define SI_CONFIG_DIVIDER_LSB \ 349 (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB) 350 #define SI_CONFIG_DIVIDER_MASK \ 351 (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK) 352 #define SI_BASE_ADDRESS \ 353 (scn->targetdef->d_SI_BASE_ADDRESS) 354 #define SI_CONFIG_OFFSET \ 355 (scn->targetdef->d_SI_CONFIG_OFFSET) 356 #define SI_TX_DATA0_OFFSET \ 357 (scn->targetdef->d_SI_TX_DATA0_OFFSET) 358 #define SI_TX_DATA1_OFFSET \ 359 (scn->targetdef->d_SI_TX_DATA1_OFFSET) 360 #define SI_RX_DATA0_OFFSET \ 361 (scn->targetdef->d_SI_RX_DATA0_OFFSET) 362 #define SI_RX_DATA1_OFFSET \ 363 (scn->targetdef->d_SI_RX_DATA1_OFFSET) 364 #define SI_CS_OFFSET \ 365 (scn->targetdef->d_SI_CS_OFFSET) 366 #define SI_CS_DONE_ERR_MASK \ 367 (scn->targetdef->d_SI_CS_DONE_ERR_MASK) 368 #define SI_CS_DONE_INT_MASK \ 369 (scn->targetdef->d_SI_CS_DONE_INT_MASK) 370 #define SI_CS_START_LSB \ 371 (scn->targetdef->d_SI_CS_START_LSB) 372 #define SI_CS_START_MASK \ 373 (scn->targetdef->d_SI_CS_START_MASK) 374 #define SI_CS_RX_CNT_LSB \ 375 (scn->targetdef->d_SI_CS_RX_CNT_LSB) 376 #define SI_CS_RX_CNT_MASK \ 377 (scn->targetdef->d_SI_CS_RX_CNT_MASK) 378 #define SI_CS_TX_CNT_LSB \ 379 (scn->targetdef->d_SI_CS_TX_CNT_LSB) 380 #define SI_CS_TX_CNT_MASK \ 381 (scn->targetdef->d_SI_CS_TX_CNT_MASK) 382 #define EEPROM_SZ \ 383 (scn->targetdef->d_BOARD_DATA_SZ) 384 #define EEPROM_EXT_SZ \ 385 (scn->targetdef->d_BOARD_EXT_DATA_SZ) 386 #define MBOX_BASE_ADDRESS \ 387 (scn->targetdef->d_MBOX_BASE_ADDRESS) 388 #define LOCAL_SCRATCH_OFFSET \ 389 (scn->targetdef->d_LOCAL_SCRATCH_OFFSET) 390 #define CPU_CLOCK_OFFSET \ 391 (scn->targetdef->d_CPU_CLOCK_OFFSET) 392 #define LPO_CAL_OFFSET \ 393 (scn->targetdef->d_LPO_CAL_OFFSET) 394 #define GPIO_PIN10_OFFSET \ 395 (scn->targetdef->d_GPIO_PIN10_OFFSET) 396 #define GPIO_PIN11_OFFSET \ 397 (scn->targetdef->d_GPIO_PIN11_OFFSET) 398 #define GPIO_PIN12_OFFSET \ 399 (scn->targetdef->d_GPIO_PIN12_OFFSET) 400 #define GPIO_PIN13_OFFSET \ 401 (scn->targetdef->d_GPIO_PIN13_OFFSET) 402 #define CLOCK_GPIO_OFFSET \ 403 (scn->targetdef->d_CLOCK_GPIO_OFFSET) 404 #define CPU_CLOCK_STANDARD_LSB \ 405 (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB) 406 #define CPU_CLOCK_STANDARD_MASK \ 407 (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK) 408 #define LPO_CAL_ENABLE_LSB \ 409 (scn->targetdef->d_LPO_CAL_ENABLE_LSB) 410 #define LPO_CAL_ENABLE_MASK \ 411 (scn->targetdef->d_LPO_CAL_ENABLE_MASK) 412 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \ 413 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB) 414 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \ 415 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 416 #define ANALOG_INTF_BASE_ADDRESS \ 417 (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS) 418 #define WLAN_MAC_BASE_ADDRESS \ 419 (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS) 420 #define CE0_BASE_ADDRESS \ 421 (scn->targetdef->d_CE0_BASE_ADDRESS) 422 #define CE1_BASE_ADDRESS \ 423 (scn->targetdef->d_CE1_BASE_ADDRESS) 424 #define FW_INDICATOR_ADDRESS \ 425 (scn->targetdef->d_FW_INDICATOR_ADDRESS) 426 #define DRAM_BASE_ADDRESS \ 427 (scn->targetdef->d_DRAM_BASE_ADDRESS) 428 #define SOC_CORE_BASE_ADDRESS \ 429 (scn->targetdef->d_SOC_CORE_BASE_ADDRESS) 430 #define CORE_CTRL_ADDRESS \ 431 (scn->targetdef->d_CORE_CTRL_ADDRESS) 432 #define CE_COUNT \ 433 (scn->targetdef->d_CE_COUNT) 434 #define PCIE_INTR_ENABLE_ADDRESS \ 435 (scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS) 436 #define PCIE_INTR_CLR_ADDRESS \ 437 (scn->targetdef->d_PCIE_INTR_CLR_ADDRESS) 438 #define PCIE_INTR_FIRMWARE_MASK \ 439 (scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK) 440 #define PCIE_INTR_CE_MASK_ALL \ 441 (scn->targetdef->d_PCIE_INTR_CE_MASK_ALL) 442 #define CORE_CTRL_CPU_INTR_MASK \ 443 (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK) 444 #define PCIE_INTR_CAUSE_ADDRESS \ 445 (scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS) 446 #define SOC_RESET_CONTROL_ADDRESS \ 447 (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS) 448 #define SOC_RESET_CONTROL_CE_RST_MASK \ 449 (scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK) 450 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK\ 451 (scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK) 452 #define CPU_INTR_ADDRESS \ 453 (scn->targetdef->d_CPU_INTR_ADDRESS) 454 #define SOC_LF_TIMER_CONTROL0_ADDRESS \ 455 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS) 456 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \ 457 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK) 458 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB \ 459 (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) 460 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK \ 461 (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) 462 463 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) \ 464 (((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> \ 465 SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) 466 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) \ 467 (((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & \ 468 SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) 469 470 /* hif_pci.c */ 471 #define CHIP_ID_ADDRESS \ 472 (scn->targetdef->d_SOC_CHIP_ID_ADDRESS) 473 #define SOC_CHIP_ID_REVISION_MASK \ 474 (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK) 475 #define SOC_CHIP_ID_REVISION_LSB \ 476 (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB) 477 #define SOC_CHIP_ID_VERSION_MASK \ 478 (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK) 479 #define SOC_CHIP_ID_VERSION_LSB \ 480 (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB) 481 #define CHIP_ID_REVISION_GET(x) \ 482 (((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB) 483 #define CHIP_ID_VERSION_GET(x) \ 484 (((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB) 485 /* hif_pci.c end */ 486 487 /* misc */ 488 #define SR_WR_INDEX_ADDRESS \ 489 (scn->targetdef->d_SR_WR_INDEX_ADDRESS) 490 #define DST_WATERMARK_ADDRESS \ 491 (scn->targetdef->d_DST_WATERMARK_ADDRESS) 492 #define SOC_POWER_REG_OFFSET \ 493 (scn->targetdef->d_SOC_POWER_REG_OFFSET) 494 /* end */ 495 496 /* htt_rx.c */ 497 #define RX_MSDU_END_4_FIRST_MSDU_MASK \ 498 (pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_MASK) 499 #define RX_MSDU_END_4_FIRST_MSDU_LSB \ 500 (pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_LSB) 501 #define RX_MPDU_START_0_RETRY_LSB \ 502 (pdev->targetdef->d_RX_MPDU_START_0_RETRY_LSB) 503 #define RX_MPDU_START_0_RETRY_MASK \ 504 (pdev->targetdef->d_RX_MPDU_START_0_RETRY_MASK) 505 #define RX_MPDU_START_0_SEQ_NUM_MASK \ 506 (pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_MASK) 507 #define RX_MPDU_START_0_SEQ_NUM_LSB \ 508 (pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_LSB) 509 #define RX_MPDU_START_2_PN_47_32_LSB \ 510 (pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_LSB) 511 #define RX_MPDU_START_2_PN_47_32_MASK \ 512 (pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_MASK) 513 #define RX_MPDU_START_2_TID_LSB \ 514 (pdev->targetdef->d_RX_MPDU_START_2_TID_LSB) 515 #define RX_MPDU_START_2_TID_MASK \ 516 (pdev->targetdef->d_RX_MPDU_START_2_TID_MASK) 517 #define RX_MSDU_END_1_KEY_ID_OCT_MASK \ 518 (pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_MASK) 519 #define RX_MSDU_END_1_KEY_ID_OCT_LSB \ 520 (pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_LSB) 521 #define RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK \ 522 (pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK) 523 #define RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB\ 524 (pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB) 525 #define RX_MSDU_END_4_LAST_MSDU_MASK \ 526 (pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_MASK) 527 #define RX_MSDU_END_4_LAST_MSDU_LSB \ 528 (pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_LSB) 529 #define RX_ATTENTION_0_MCAST_BCAST_MASK \ 530 (pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_MASK) 531 #define RX_ATTENTION_0_MCAST_BCAST_LSB \ 532 (pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_LSB) 533 #define RX_ATTENTION_0_FRAGMENT_MASK \ 534 (pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_MASK) 535 #define RX_ATTENTION_0_FRAGMENT_LSB \ 536 (pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_LSB) 537 #define RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK\ 538 (pdev->targetdef->d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK) 539 #define RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK \ 540 (pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK) 541 #define RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB\ 542 (pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB) 543 #define RX_MSDU_START_0_MSDU_LENGTH_MASK \ 544 (pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_MASK) 545 #define RX_MSDU_START_0_MSDU_LENGTH_LSB \ 546 (pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_LSB) 547 #define RX_MSDU_START_2_DECAP_FORMAT_OFFSET\ 548 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET) 549 #define RX_MSDU_START_2_DECAP_FORMAT_MASK \ 550 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_MASK) 551 #define RX_MSDU_START_2_DECAP_FORMAT_LSB \ 552 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_LSB) 553 #define RX_MPDU_START_0_ENCRYPTED_MASK \ 554 (pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_MASK) 555 #define RX_MPDU_START_0_ENCRYPTED_LSB \ 556 (pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_LSB) 557 #define RX_ATTENTION_0_MORE_DATA_MASK \ 558 (pdev->targetdef->d_RX_ATTENTION_0_MORE_DATA_MASK) 559 #define RX_ATTENTION_0_MSDU_DONE_MASK \ 560 (pdev->targetdef->d_RX_ATTENTION_0_MSDU_DONE_MASK) 561 #define RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK \ 562 (pdev->targetdef->d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK) 563 /* end */ 564 565 /* copy_engine.c */ 566 #define DST_WR_INDEX_ADDRESS \ 567 (scn->targetdef->d_DST_WR_INDEX_ADDRESS) 568 #define SRC_WATERMARK_ADDRESS \ 569 (scn->targetdef->d_SRC_WATERMARK_ADDRESS) 570 #define SRC_WATERMARK_LOW_MASK \ 571 (scn->targetdef->d_SRC_WATERMARK_LOW_MASK) 572 #define SRC_WATERMARK_HIGH_MASK \ 573 (scn->targetdef->d_SRC_WATERMARK_HIGH_MASK) 574 #define DST_WATERMARK_LOW_MASK \ 575 (scn->targetdef->d_DST_WATERMARK_LOW_MASK) 576 #define DST_WATERMARK_HIGH_MASK \ 577 (scn->targetdef->d_DST_WATERMARK_HIGH_MASK) 578 #define CURRENT_SRRI_ADDRESS \ 579 (scn->targetdef->d_CURRENT_SRRI_ADDRESS) 580 #define CURRENT_DRRI_ADDRESS \ 581 (scn->targetdef->d_CURRENT_DRRI_ADDRESS) 582 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \ 583 (scn->targetdef->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK) 584 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK\ 585 (scn->targetdef->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK) 586 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK \ 587 (scn->targetdef->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK) 588 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK\ 589 (scn->targetdef->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK) 590 #define HOST_IS_ADDRESS \ 591 (scn->targetdef->d_HOST_IS_ADDRESS) 592 #define HOST_IS_COPY_COMPLETE_MASK \ 593 (scn->targetdef->d_HOST_IS_COPY_COMPLETE_MASK) 594 #define CE_WRAPPER_BASE_ADDRESS \ 595 (scn->targetdef->d_CE_WRAPPER_BASE_ADDRESS) 596 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS \ 597 (scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS) 598 #define HOST_IE_ADDRESS \ 599 (scn->targetdef->d_HOST_IE_ADDRESS) 600 #define HOST_IE_COPY_COMPLETE_MASK \ 601 (scn->targetdef->d_HOST_IE_COPY_COMPLETE_MASK) 602 #define SR_BA_ADDRESS \ 603 (scn->targetdef->d_SR_BA_ADDRESS) 604 #define SR_SIZE_ADDRESS \ 605 (scn->targetdef->d_SR_SIZE_ADDRESS) 606 #define CE_CTRL1_ADDRESS \ 607 (scn->targetdef->d_CE_CTRL1_ADDRESS) 608 #define CE_CTRL1_DMAX_LENGTH_MASK \ 609 (scn->targetdef->d_CE_CTRL1_DMAX_LENGTH_MASK) 610 #define DR_BA_ADDRESS \ 611 (scn->targetdef->d_DR_BA_ADDRESS) 612 #define DR_SIZE_ADDRESS \ 613 (scn->targetdef->d_DR_SIZE_ADDRESS) 614 #define MISC_IE_ADDRESS \ 615 (scn->targetdef->d_MISC_IE_ADDRESS) 616 #define MISC_IS_AXI_ERR_MASK \ 617 (scn->targetdef->d_MISC_IS_AXI_ERR_MASK) 618 #define MISC_IS_DST_ADDR_ERR_MASK \ 619 (scn->targetdef->d_MISC_IS_DST_ADDR_ERR_MASK) 620 #define MISC_IS_SRC_LEN_ERR_MASK \ 621 (scn->targetdef->d_MISC_IS_SRC_LEN_ERR_MASK) 622 #define MISC_IS_DST_MAX_LEN_VIO_MASK \ 623 (scn->targetdef->d_MISC_IS_DST_MAX_LEN_VIO_MASK) 624 #define MISC_IS_DST_RING_OVERFLOW_MASK \ 625 (scn->targetdef->d_MISC_IS_DST_RING_OVERFLOW_MASK) 626 #define MISC_IS_SRC_RING_OVERFLOW_MASK \ 627 (scn->targetdef->d_MISC_IS_SRC_RING_OVERFLOW_MASK) 628 #define SRC_WATERMARK_LOW_LSB \ 629 (scn->targetdef->d_SRC_WATERMARK_LOW_LSB) 630 #define SRC_WATERMARK_HIGH_LSB \ 631 (scn->targetdef->d_SRC_WATERMARK_HIGH_LSB) 632 #define DST_WATERMARK_LOW_LSB \ 633 (scn->targetdef->d_DST_WATERMARK_LOW_LSB) 634 #define DST_WATERMARK_HIGH_LSB \ 635 (scn->targetdef->d_DST_WATERMARK_HIGH_LSB) 636 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \ 637 (scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) 638 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ 639 (scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 640 #define CE_CTRL1_DMAX_LENGTH_LSB \ 641 (scn->targetdef->d_CE_CTRL1_DMAX_LENGTH_LSB) 642 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK\ 643 (scn->targetdef->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 644 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK\ 645 (scn->targetdef->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 646 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \ 647 (scn->targetdef->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) 648 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \ 649 (scn->targetdef->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) 650 #define WLAN_DEBUG_INPUT_SEL_OFFSET \ 651 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET) 652 #define WLAN_DEBUG_INPUT_SEL_SRC_MSB \ 653 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB) 654 #define WLAN_DEBUG_INPUT_SEL_SRC_LSB \ 655 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB) 656 #define WLAN_DEBUG_INPUT_SEL_SRC_MASK \ 657 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK) 658 #define WLAN_DEBUG_CONTROL_OFFSET \ 659 (scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET) 660 #define WLAN_DEBUG_CONTROL_ENABLE_MSB \ 661 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB) 662 #define WLAN_DEBUG_CONTROL_ENABLE_LSB \ 663 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB) 664 #define WLAN_DEBUG_CONTROL_ENABLE_MASK \ 665 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK) 666 #define WLAN_DEBUG_OUT_OFFSET \ 667 (scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET) 668 #define WLAN_DEBUG_OUT_DATA_MSB \ 669 (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB) 670 #define WLAN_DEBUG_OUT_DATA_LSB \ 671 (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB) 672 #define WLAN_DEBUG_OUT_DATA_MASK \ 673 (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK) 674 #define AMBA_DEBUG_BUS_OFFSET \ 675 (scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET) 676 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB \ 677 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB) 678 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB \ 679 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) 680 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK \ 681 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) 682 #define AMBA_DEBUG_BUS_SEL_MSB \ 683 (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB) 684 #define AMBA_DEBUG_BUS_SEL_LSB \ 685 (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB) 686 #define AMBA_DEBUG_BUS_SEL_MASK \ 687 (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK) 688 #define CE_WRAPPER_DEBUG_OFFSET \ 689 (scn->targetdef->d_CE_WRAPPER_DEBUG_OFFSET) 690 #define CE_WRAPPER_DEBUG_SEL_MSB \ 691 (scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_MSB) 692 #define CE_WRAPPER_DEBUG_SEL_LSB \ 693 (scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_LSB) 694 #define CE_WRAPPER_DEBUG_SEL_MASK \ 695 (scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_MASK) 696 #define CE_DEBUG_OFFSET \ 697 (scn->targetdef->d_CE_DEBUG_OFFSET) 698 #define CE_DEBUG_SEL_MSB \ 699 (scn->targetdef->d_CE_DEBUG_SEL_MSB) 700 #define CE_DEBUG_SEL_LSB \ 701 (scn->targetdef->d_CE_DEBUG_SEL_LSB) 702 #define CE_DEBUG_SEL_MASK \ 703 (scn->targetdef->d_CE_DEBUG_SEL_MASK) 704 /* end */ 705 /* PLL start */ 706 #define EFUSE_OFFSET \ 707 (scn->targetdef->d_EFUSE_OFFSET) 708 #define EFUSE_XTAL_SEL_MSB \ 709 (scn->targetdef->d_EFUSE_XTAL_SEL_MSB) 710 #define EFUSE_XTAL_SEL_LSB \ 711 (scn->targetdef->d_EFUSE_XTAL_SEL_LSB) 712 #define EFUSE_XTAL_SEL_MASK \ 713 (scn->targetdef->d_EFUSE_XTAL_SEL_MASK) 714 #define BB_PLL_CONFIG_OFFSET \ 715 (scn->targetdef->d_BB_PLL_CONFIG_OFFSET) 716 #define BB_PLL_CONFIG_OUTDIV_MSB \ 717 (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB) 718 #define BB_PLL_CONFIG_OUTDIV_LSB \ 719 (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB) 720 #define BB_PLL_CONFIG_OUTDIV_MASK \ 721 (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK) 722 #define BB_PLL_CONFIG_FRAC_MSB \ 723 (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB) 724 #define BB_PLL_CONFIG_FRAC_LSB \ 725 (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB) 726 #define BB_PLL_CONFIG_FRAC_MASK \ 727 (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK) 728 #define WLAN_PLL_SETTLE_TIME_MSB \ 729 (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB) 730 #define WLAN_PLL_SETTLE_TIME_LSB \ 731 (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB) 732 #define WLAN_PLL_SETTLE_TIME_MASK \ 733 (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK) 734 #define WLAN_PLL_SETTLE_OFFSET \ 735 (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET) 736 #define WLAN_PLL_SETTLE_SW_MASK \ 737 (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK) 738 #define WLAN_PLL_SETTLE_RSTMASK \ 739 (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK) 740 #define WLAN_PLL_SETTLE_RESET \ 741 (scn->targetdef->d_WLAN_PLL_SETTLE_RESET) 742 #define WLAN_PLL_CONTROL_NOPWD_MSB \ 743 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB) 744 #define WLAN_PLL_CONTROL_NOPWD_LSB \ 745 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB) 746 #define WLAN_PLL_CONTROL_NOPWD_MASK \ 747 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK) 748 #define WLAN_PLL_CONTROL_BYPASS_MSB \ 749 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB) 750 #define WLAN_PLL_CONTROL_BYPASS_LSB \ 751 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB) 752 #define WLAN_PLL_CONTROL_BYPASS_MASK \ 753 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK) 754 #define WLAN_PLL_CONTROL_BYPASS_RESET \ 755 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET) 756 #define WLAN_PLL_CONTROL_CLK_SEL_MSB \ 757 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB) 758 #define WLAN_PLL_CONTROL_CLK_SEL_LSB \ 759 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB) 760 #define WLAN_PLL_CONTROL_CLK_SEL_MASK \ 761 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK) 762 #define WLAN_PLL_CONTROL_CLK_SEL_RESET \ 763 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET) 764 #define WLAN_PLL_CONTROL_REFDIV_MSB \ 765 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB) 766 #define WLAN_PLL_CONTROL_REFDIV_LSB \ 767 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB) 768 #define WLAN_PLL_CONTROL_REFDIV_MASK \ 769 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK) 770 #define WLAN_PLL_CONTROL_REFDIV_RESET \ 771 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET) 772 #define WLAN_PLL_CONTROL_DIV_MSB \ 773 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB) 774 #define WLAN_PLL_CONTROL_DIV_LSB \ 775 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB) 776 #define WLAN_PLL_CONTROL_DIV_MASK \ 777 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK) 778 #define WLAN_PLL_CONTROL_DIV_RESET \ 779 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET) 780 #define WLAN_PLL_CONTROL_OFFSET \ 781 (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET) 782 #define WLAN_PLL_CONTROL_SW_MASK \ 783 (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK) 784 #define WLAN_PLL_CONTROL_RSTMASK \ 785 (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK) 786 #define WLAN_PLL_CONTROL_RESET \ 787 (scn->targetdef->d_WLAN_PLL_CONTROL_RESET) 788 #define SOC_CORE_CLK_CTRL_OFFSET \ 789 (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET) 790 #define SOC_CORE_CLK_CTRL_DIV_MSB \ 791 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB) 792 #define SOC_CORE_CLK_CTRL_DIV_LSB \ 793 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB) 794 #define SOC_CORE_CLK_CTRL_DIV_MASK \ 795 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK) 796 #define RTC_SYNC_STATUS_PLL_CHANGING_MSB \ 797 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB) 798 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB \ 799 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB) 800 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK \ 801 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK) 802 #define RTC_SYNC_STATUS_PLL_CHANGING_RESET \ 803 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET) 804 #define RTC_SYNC_STATUS_OFFSET \ 805 (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET) 806 #define SOC_CPU_CLOCK_OFFSET \ 807 (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET) 808 #define SOC_CPU_CLOCK_STANDARD_MSB \ 809 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB) 810 #define SOC_CPU_CLOCK_STANDARD_LSB \ 811 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB) 812 #define SOC_CPU_CLOCK_STANDARD_MASK \ 813 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK) 814 /* PLL end */ 815 816 /* SET macros */ 817 #define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \ 818 (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \ 819 WLAN_SYSTEM_SLEEP_DISABLE_MASK) 820 #define SI_CONFIG_BIDIR_OD_DATA_SET(x) \ 821 (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & \ 822 SI_CONFIG_BIDIR_OD_DATA_MASK) 823 #define SI_CONFIG_I2C_SET(x) \ 824 (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) 825 #define SI_CONFIG_POS_SAMPLE_SET(x) \ 826 (((x) << SI_CONFIG_POS_SAMPLE_LSB) & \ 827 SI_CONFIG_POS_SAMPLE_MASK) 828 #define SI_CONFIG_INACTIVE_CLK_SET(x) \ 829 (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & \ 830 SI_CONFIG_INACTIVE_CLK_MASK) 831 #define SI_CONFIG_INACTIVE_DATA_SET(x) \ 832 (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & \ 833 SI_CONFIG_INACTIVE_DATA_MASK) 834 #define SI_CONFIG_DIVIDER_SET(x) \ 835 (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) 836 #define SI_CS_START_SET(x) \ 837 (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) 838 #define SI_CS_RX_CNT_SET(x) \ 839 (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) 840 #define SI_CS_TX_CNT_SET(x) \ 841 (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) 842 #define LPO_CAL_ENABLE_SET(x) \ 843 (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) 844 #define CPU_CLOCK_STANDARD_SET(x) \ 845 (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) 846 #define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \ 847 (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & \ 848 CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 849 /* copy_engine.c */ 850 #define SRC_WATERMARK_LOW_SET(x) \ 851 (((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK) 852 #define SRC_WATERMARK_HIGH_SET(x) \ 853 (((x) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK) 854 #define DST_WATERMARK_LOW_SET(x) \ 855 (((x) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK) 856 #define DST_WATERMARK_HIGH_SET(x) \ 857 (((x) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK) 858 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) (((x) & \ 859 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \ 860 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 861 #define CE_CTRL1_DMAX_LENGTH_SET(x) \ 862 (((x) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK) 863 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \ 864 (((x) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \ 865 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 866 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \ 867 (((x) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \ 868 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 869 #define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) \ 870 (((x) & \ 871 WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> \ 872 WLAN_DEBUG_INPUT_SEL_SRC_LSB) 873 #define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) \ 874 (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & \ 875 WLAN_DEBUG_INPUT_SEL_SRC_MASK) 876 #define WLAN_DEBUG_CONTROL_ENABLE_GET(x) \ 877 (((x) & \ 878 WLAN_DEBUG_CONTROL_ENABLE_MASK) >> \ 879 WLAN_DEBUG_CONTROL_ENABLE_LSB) 880 #define WLAN_DEBUG_CONTROL_ENABLE_SET(x) \ 881 (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & \ 882 WLAN_DEBUG_CONTROL_ENABLE_MASK) 883 #define WLAN_DEBUG_OUT_DATA_GET(x) \ 884 (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB) 885 #define WLAN_DEBUG_OUT_DATA_SET(x) \ 886 (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK) 887 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_GET(x) \ 888 (((x) & \ 889 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) >> \ 890 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) 891 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(x) \ 892 (((x) << AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) & \ 893 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) 894 #define AMBA_DEBUG_BUS_SEL_GET(x) \ 895 (((x) & AMBA_DEBUG_BUS_SEL_MASK) >> AMBA_DEBUG_BUS_SEL_LSB) 896 #define AMBA_DEBUG_BUS_SEL_SET(x) \ 897 (((x) << AMBA_DEBUG_BUS_SEL_LSB) & AMBA_DEBUG_BUS_SEL_MASK) 898 #define CE_WRAPPER_DEBUG_SEL_GET(x) \ 899 (((x) & CE_WRAPPER_DEBUG_SEL_MASK) >> CE_WRAPPER_DEBUG_SEL_LSB) 900 #define CE_WRAPPER_DEBUG_SEL_SET(x) \ 901 (((x) << CE_WRAPPER_DEBUG_SEL_LSB) & CE_WRAPPER_DEBUG_SEL_MASK) 902 #define CE_DEBUG_SEL_GET(x) \ 903 (((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB) 904 #define CE_DEBUG_SEL_SET(x) \ 905 (((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK) 906 /* end */ 907 /* PLL start */ 908 #define EFUSE_XTAL_SEL_GET(x) \ 909 (((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB) 910 #define EFUSE_XTAL_SEL_SET(x) \ 911 (((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK) 912 #define BB_PLL_CONFIG_OUTDIV_GET(x) \ 913 (((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB) 914 #define BB_PLL_CONFIG_OUTDIV_SET(x) \ 915 (((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK) 916 #define BB_PLL_CONFIG_FRAC_GET(x) \ 917 (((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB) 918 #define BB_PLL_CONFIG_FRAC_SET(x) \ 919 (((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK) 920 #define WLAN_PLL_SETTLE_TIME_GET(x) \ 921 (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB) 922 #define WLAN_PLL_SETTLE_TIME_SET(x) \ 923 (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK) 924 #define WLAN_PLL_CONTROL_NOPWD_GET(x) \ 925 (((x) & \ 926 WLAN_PLL_CONTROL_NOPWD_MASK) >> \ 927 WLAN_PLL_CONTROL_NOPWD_LSB) 928 #define WLAN_PLL_CONTROL_NOPWD_SET(x) \ 929 (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & \ 930 WLAN_PLL_CONTROL_NOPWD_MASK) 931 #define WLAN_PLL_CONTROL_BYPASS_GET(x) \ 932 (((x) & \ 933 WLAN_PLL_CONTROL_BYPASS_MASK) >> \ 934 WLAN_PLL_CONTROL_BYPASS_LSB) 935 #define WLAN_PLL_CONTROL_BYPASS_SET(x) \ 936 (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & \ 937 WLAN_PLL_CONTROL_BYPASS_MASK) 938 #define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \ 939 (((x) & \ 940 WLAN_PLL_CONTROL_CLK_SEL_MASK) >> \ 941 WLAN_PLL_CONTROL_CLK_SEL_LSB) 942 #define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \ 943 (((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & \ 944 WLAN_PLL_CONTROL_CLK_SEL_MASK) 945 #define WLAN_PLL_CONTROL_REFDIV_GET(x) \ 946 (((x) & \ 947 WLAN_PLL_CONTROL_REFDIV_MASK) >> \ 948 WLAN_PLL_CONTROL_REFDIV_LSB) 949 #define WLAN_PLL_CONTROL_REFDIV_SET(x) \ 950 (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & \ 951 WLAN_PLL_CONTROL_REFDIV_MASK) 952 #define WLAN_PLL_CONTROL_DIV_GET(x) \ 953 (((x) & \ 954 WLAN_PLL_CONTROL_DIV_MASK) >> \ 955 WLAN_PLL_CONTROL_DIV_LSB) 956 #define WLAN_PLL_CONTROL_DIV_SET(x) \ 957 (((x) << WLAN_PLL_CONTROL_DIV_LSB) & \ 958 WLAN_PLL_CONTROL_DIV_MASK) 959 #define SOC_CORE_CLK_CTRL_DIV_GET(x) \ 960 (((x) & \ 961 SOC_CORE_CLK_CTRL_DIV_MASK) >> \ 962 SOC_CORE_CLK_CTRL_DIV_LSB) 963 #define SOC_CORE_CLK_CTRL_DIV_SET(x) \ 964 (((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & \ 965 SOC_CORE_CLK_CTRL_DIV_MASK) 966 #define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \ 967 (((x) & \ 968 RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \ 969 RTC_SYNC_STATUS_PLL_CHANGING_LSB) 970 #define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \ 971 (((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \ 972 RTC_SYNC_STATUS_PLL_CHANGING_MASK) 973 #define SOC_CPU_CLOCK_STANDARD_GET(x) \ 974 (((x) & \ 975 SOC_CPU_CLOCK_STANDARD_MASK) >> \ 976 SOC_CPU_CLOCK_STANDARD_LSB) 977 #define SOC_CPU_CLOCK_STANDARD_SET(x) \ 978 (((x) << SOC_CPU_CLOCK_STANDARD_LSB) & \ 979 SOC_CPU_CLOCK_STANDARD_MASK) 980 /* PLL end */ 981 982 struct hostdef_s { 983 uint32_t d_INT_STATUS_ENABLE_ERROR_LSB; 984 uint32_t d_INT_STATUS_ENABLE_ERROR_MASK; 985 uint32_t d_INT_STATUS_ENABLE_CPU_LSB; 986 uint32_t d_INT_STATUS_ENABLE_CPU_MASK; 987 uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB; 988 uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK; 989 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB; 990 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK; 991 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB; 992 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK; 993 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB; 994 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK; 995 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB; 996 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK; 997 uint32_t d_INT_STATUS_ENABLE_ADDRESS; 998 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB; 999 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK; 1000 uint32_t d_HOST_INT_STATUS_ADDRESS; 1001 uint32_t d_CPU_INT_STATUS_ADDRESS; 1002 uint32_t d_ERROR_INT_STATUS_ADDRESS; 1003 uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK; 1004 uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB; 1005 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK; 1006 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB; 1007 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK; 1008 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB; 1009 uint32_t d_COUNT_DEC_ADDRESS; 1010 uint32_t d_HOST_INT_STATUS_CPU_MASK; 1011 uint32_t d_HOST_INT_STATUS_CPU_LSB; 1012 uint32_t d_HOST_INT_STATUS_ERROR_MASK; 1013 uint32_t d_HOST_INT_STATUS_ERROR_LSB; 1014 uint32_t d_HOST_INT_STATUS_COUNTER_MASK; 1015 uint32_t d_HOST_INT_STATUS_COUNTER_LSB; 1016 uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS; 1017 uint32_t d_WINDOW_DATA_ADDRESS; 1018 uint32_t d_WINDOW_READ_ADDR_ADDRESS; 1019 uint32_t d_WINDOW_WRITE_ADDR_ADDRESS; 1020 uint32_t d_SOC_GLOBAL_RESET_ADDRESS; 1021 uint32_t d_RTC_STATE_ADDRESS; 1022 uint32_t d_RTC_STATE_COLD_RESET_MASK; 1023 uint32_t d_PCIE_LOCAL_BASE_ADDRESS; 1024 uint32_t d_PCIE_SOC_WAKE_RESET; 1025 uint32_t d_PCIE_SOC_WAKE_ADDRESS; 1026 uint32_t d_PCIE_SOC_WAKE_V_MASK; 1027 uint32_t d_RTC_STATE_V_MASK; 1028 uint32_t d_RTC_STATE_V_LSB; 1029 uint32_t d_FW_IND_EVENT_PENDING; 1030 uint32_t d_FW_IND_INITIALIZED; 1031 uint32_t d_RTC_STATE_V_ON; 1032 #if defined(SDIO_3_0) 1033 uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK; 1034 uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB; 1035 #endif 1036 uint32_t d_PCIE_SOC_RDY_STATUS_ADDRESS; 1037 uint32_t d_PCIE_SOC_RDY_STATUS_BAR_MASK; 1038 uint32_t d_SOC_PCIE_BASE_ADDRESS; 1039 uint32_t d_MSI_MAGIC_ADR_ADDRESS; 1040 uint32_t d_MSI_MAGIC_ADDRESS; 1041 }; 1042 1043 #define INT_STATUS_ENABLE_ERROR_LSB \ 1044 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB) 1045 #define INT_STATUS_ENABLE_ERROR_MASK \ 1046 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK) 1047 #define INT_STATUS_ENABLE_CPU_LSB \ 1048 (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB) 1049 #define INT_STATUS_ENABLE_CPU_MASK \ 1050 (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK) 1051 #define INT_STATUS_ENABLE_COUNTER_LSB \ 1052 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB) 1053 #define INT_STATUS_ENABLE_COUNTER_MASK \ 1054 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK) 1055 #define INT_STATUS_ENABLE_MBOX_DATA_LSB \ 1056 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB) 1057 #define INT_STATUS_ENABLE_MBOX_DATA_MASK \ 1058 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK) 1059 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \ 1060 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) 1061 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \ 1062 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 1063 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB\ 1064 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) 1065 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \ 1066 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 1067 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB \ 1068 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB) 1069 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK \ 1070 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK) 1071 #define INT_STATUS_ENABLE_ADDRESS \ 1072 (scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS) 1073 #define CPU_INT_STATUS_ENABLE_BIT_LSB \ 1074 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB) 1075 #define CPU_INT_STATUS_ENABLE_BIT_MASK \ 1076 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK) 1077 #define HOST_INT_STATUS_ADDRESS \ 1078 (scn->hostdef->d_HOST_INT_STATUS_ADDRESS) 1079 #define CPU_INT_STATUS_ADDRESS \ 1080 (scn->hostdef->d_CPU_INT_STATUS_ADDRESS) 1081 #define ERROR_INT_STATUS_ADDRESS \ 1082 (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS) 1083 #define ERROR_INT_STATUS_WAKEUP_MASK \ 1084 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK) 1085 #define ERROR_INT_STATUS_WAKEUP_LSB \ 1086 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB) 1087 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \ 1088 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK) 1089 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \ 1090 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 1091 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK \ 1092 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK) 1093 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB \ 1094 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB) 1095 #define COUNT_DEC_ADDRESS \ 1096 (scn->hostdef->d_COUNT_DEC_ADDRESS) 1097 #define HOST_INT_STATUS_CPU_MASK \ 1098 (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK) 1099 #define HOST_INT_STATUS_CPU_LSB \ 1100 (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB) 1101 #define HOST_INT_STATUS_ERROR_MASK \ 1102 (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK) 1103 #define HOST_INT_STATUS_ERROR_LSB \ 1104 (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB) 1105 #define HOST_INT_STATUS_COUNTER_MASK \ 1106 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK) 1107 #define HOST_INT_STATUS_COUNTER_LSB \ 1108 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB) 1109 #define RX_LOOKAHEAD_VALID_ADDRESS \ 1110 (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS) 1111 #define WINDOW_DATA_ADDRESS \ 1112 (scn->hostdef->d_WINDOW_DATA_ADDRESS) 1113 #define WINDOW_READ_ADDR_ADDRESS \ 1114 (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS) 1115 #define WINDOW_WRITE_ADDR_ADDRESS \ 1116 (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS) 1117 #define SOC_GLOBAL_RESET_ADDRESS \ 1118 (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS) 1119 #define RTC_STATE_ADDRESS \ 1120 (scn->hostdef->d_RTC_STATE_ADDRESS) 1121 #define RTC_STATE_COLD_RESET_MASK \ 1122 (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK) 1123 #define PCIE_LOCAL_BASE_ADDRESS \ 1124 (scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS) 1125 #define PCIE_SOC_WAKE_RESET \ 1126 (scn->hostdef->d_PCIE_SOC_WAKE_RESET) 1127 #define PCIE_SOC_WAKE_ADDRESS \ 1128 (scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS) 1129 #define PCIE_SOC_WAKE_V_MASK \ 1130 (scn->hostdef->d_PCIE_SOC_WAKE_V_MASK) 1131 #define RTC_STATE_V_MASK \ 1132 (scn->hostdef->d_RTC_STATE_V_MASK) 1133 #define RTC_STATE_V_LSB \ 1134 (scn->hostdef->d_RTC_STATE_V_LSB) 1135 #define FW_IND_EVENT_PENDING \ 1136 (scn->hostdef->d_FW_IND_EVENT_PENDING) 1137 #define FW_IND_INITIALIZED \ 1138 (scn->hostdef->d_FW_IND_INITIALIZED) 1139 #define RTC_STATE_V_ON \ 1140 (scn->hostdef->d_RTC_STATE_V_ON) 1141 #if defined(SDIO_3_0) 1142 #define HOST_INT_STATUS_MBOX_DATA_MASK \ 1143 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK) 1144 #define HOST_INT_STATUS_MBOX_DATA_LSB \ 1145 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB) 1146 #endif 1147 1148 #if !defined(SOC_PCIE_BASE_ADDRESS) 1149 #define SOC_PCIE_BASE_ADDRESS 0 1150 #endif 1151 1152 #if !defined(PCIE_SOC_RDY_STATUS_ADDRESS) 1153 #define PCIE_SOC_RDY_STATUS_ADDRESS 0 1154 #define PCIE_SOC_RDY_STATUS_BAR_MASK 0 1155 #endif 1156 1157 #if !defined(MSI_MAGIC_ADR_ADDRESS) 1158 #define MSI_MAGIC_ADR_ADDRESS 0 1159 #define MSI_MAGIC_ADDRESS 0 1160 #endif 1161 1162 /* SET/GET macros */ 1163 #define INT_STATUS_ENABLE_ERROR_SET(x) \ 1164 (((x) << INT_STATUS_ENABLE_ERROR_LSB) & \ 1165 INT_STATUS_ENABLE_ERROR_MASK) 1166 #define INT_STATUS_ENABLE_CPU_SET(x) \ 1167 (((x) << INT_STATUS_ENABLE_CPU_LSB) & \ 1168 INT_STATUS_ENABLE_CPU_MASK) 1169 #define INT_STATUS_ENABLE_COUNTER_SET(x) \ 1170 (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \ 1171 INT_STATUS_ENABLE_COUNTER_MASK) 1172 #define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \ 1173 (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \ 1174 INT_STATUS_ENABLE_MBOX_DATA_MASK) 1175 #define CPU_INT_STATUS_ENABLE_BIT_SET(x) \ 1176 (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \ 1177 CPU_INT_STATUS_ENABLE_BIT_MASK) 1178 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \ 1179 (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \ 1180 ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 1181 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x)\ 1182 (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \ 1183 ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 1184 #define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \ 1185 (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \ 1186 COUNTER_INT_STATUS_ENABLE_BIT_MASK) 1187 #define ERROR_INT_STATUS_WAKEUP_GET(x) \ 1188 (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \ 1189 ERROR_INT_STATUS_WAKEUP_LSB) 1190 #define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \ 1191 (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \ 1192 ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 1193 #define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \ 1194 (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \ 1195 ERROR_INT_STATUS_TX_OVERFLOW_LSB) 1196 #define HOST_INT_STATUS_CPU_GET(x) \ 1197 (((x) & HOST_INT_STATUS_CPU_MASK) >> \ 1198 HOST_INT_STATUS_CPU_LSB) 1199 #define HOST_INT_STATUS_ERROR_GET(x) \ 1200 (((x) & HOST_INT_STATUS_ERROR_MASK) >> \ 1201 HOST_INT_STATUS_ERROR_LSB) 1202 #define HOST_INT_STATUS_COUNTER_GET(x) \ 1203 (((x) & HOST_INT_STATUS_COUNTER_MASK) >> \ 1204 HOST_INT_STATUS_COUNTER_LSB) 1205 #define RTC_STATE_V_GET(x) \ 1206 (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 1207 #if defined(SDIO_3_0) 1208 #define HOST_INT_STATUS_MBOX_DATA_GET(x) \ 1209 (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \ 1210 HOST_INT_STATUS_MBOX_DATA_LSB) 1211 #endif 1212 1213 #define INVALID_REG_LOC_DUMMY_DATA 0xAA 1214 1215 1216 1217 #define ROME_USB_RTC_SOC_BASE_ADDRESS 0x00000800 1218 #define ROME_USB_SOC_RESET_CONTROL_COLD_RST_LSB 0x0 1219 #define SOC_RESET_CONTROL_COLD_RST_LSB 8 1220 #define SOC_RESET_CONTROL_COLD_RST_MASK 0x00000100 1221 #define SOC_RESET_CONTROL_COLD_RST_SET(x) \ 1222 (((x) << SOC_RESET_CONTROL_COLD_RST_LSB) & \ 1223 SOC_RESET_CONTROL_COLD_RST_MASK) 1224 1225 #define AR6320_CORE_CLK_DIV_ADDR 0x403fa8 1226 #define AR6320_CPU_PLL_INIT_DONE_ADDR 0x403fd0 1227 #define AR6320_CPU_SPEED_ADDR 0x403fa4 1228 #define AR6320V2_CORE_CLK_DIV_ADDR 0x403fd8 1229 #define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0 1230 #define AR6320V2_CPU_SPEED_ADDR 0x403fd4 1231 #define AR6320V3_CORE_CLK_DIV_ADDR 0x404028 1232 #define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020 1233 #define AR6320V3_CPU_SPEED_ADDR 0x404024 1234 1235 enum a_refclk_speed_t { 1236 /* Unsupported ref clock -- use PLL Bypass */ 1237 SOC_REFCLK_UNKNOWN = -1, 1238 SOC_REFCLK_48_MHZ = 0, 1239 SOC_REFCLK_19_2_MHZ = 1, 1240 SOC_REFCLK_24_MHZ = 2, 1241 SOC_REFCLK_26_MHZ = 3, 1242 SOC_REFCLK_37_4_MHZ = 4, 1243 SOC_REFCLK_38_4_MHZ = 5, 1244 SOC_REFCLK_40_MHZ = 6, 1245 SOC_REFCLK_52_MHZ = 7, 1246 }; 1247 1248 #define A_REFCLK_UNKNOWN SOC_REFCLK_UNKNOWN 1249 #define A_REFCLK_48_MHZ SOC_REFCLK_48_MHZ 1250 #define A_REFCLK_19_2_MHZ SOC_REFCLK_19_2_MHZ 1251 #define A_REFCLK_24_MHZ SOC_REFCLK_24_MHZ 1252 #define A_REFCLK_26_MHZ SOC_REFCLK_26_MHZ 1253 #define A_REFCLK_37_4_MHZ SOC_REFCLK_37_4_MHZ 1254 #define A_REFCLK_38_4_MHZ SOC_REFCLK_38_4_MHZ 1255 #define A_REFCLK_40_MHZ SOC_REFCLK_40_MHZ 1256 #define A_REFCLK_52_MHZ SOC_REFCLK_52_MHZ 1257 1258 #define TARGET_CPU_FREQ 176000000 1259 1260 struct wlan_pll_s { 1261 u_int32_t refdiv; 1262 u_int32_t div; 1263 u_int32_t rnfrac; 1264 u_int32_t outdiv; 1265 }; 1266 1267 struct cmnos_clock_s { 1268 enum a_refclk_speed_t refclk_speed; 1269 u_int32_t refclk_hz; 1270 u_int32_t pll_settling_time; /* 50us */ 1271 struct wlan_pll_s wlan_pll; 1272 }; 1273 1274 struct tgt_reg_section { 1275 u_int32_t start_addr; 1276 u_int32_t end_addr; 1277 }; 1278 1279 struct tgt_reg_table { 1280 const struct tgt_reg_section *section; 1281 u_int32_t section_size; 1282 }; 1283 1284 void target_register_tbl_attach(struct hif_softc *scn, 1285 uint32_t target_type); 1286 void hif_register_tbl_attach(struct hif_softc *scn, 1287 uint32_t target_type); 1288 #endif 1289