1 /* 2 * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /** 20 * DOC: if_ahb.c 21 * 22 * c file for ahb specific implementations. 23 */ 24 25 #include "hif.h" 26 #include "target_type.h" 27 #include "hif_main.h" 28 #include "hif_debug.h" 29 #include "hif_io32.h" 30 #include "ce_main.h" 31 #include "ce_api.h" 32 #include "ce_tasklet.h" 33 #include "if_ahb.h" 34 #include "if_pci.h" 35 #include "ahb_api.h" 36 #include "pci_api.h" 37 #include "hif_napi.h" 38 #include "qal_vbus_dev.h" 39 40 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) 41 #define IRQF_DISABLED 0x00000020 42 #endif 43 44 #define HIF_IC_CE0_IRQ_OFFSET 4 45 #define HIF_IC_MAX_IRQ 52 46 47 static uint8_t ic_irqnum[HIF_IC_MAX_IRQ]; 48 /* integrated chip irq names */ 49 const char *ic_irqname[HIF_IC_MAX_IRQ] = { 50 "misc-pulse1", 51 "misc-latch", 52 "sw-exception", 53 "watchdog", 54 "ce0", 55 "ce1", 56 "ce2", 57 "ce3", 58 "ce4", 59 "ce5", 60 "ce6", 61 "ce7", 62 "ce8", 63 "ce9", 64 "ce10", 65 "ce11", 66 "host2wbm-desc-feed", 67 "host2reo-re-injection", 68 "host2reo-command", 69 "host2rxdma-monitor-ring3", 70 "host2rxdma-monitor-ring2", 71 "host2rxdma-monitor-ring1", 72 "reo2ost-exception", 73 "wbm2host-rx-release", 74 "reo2host-status", 75 "reo2host-destination-ring4", 76 "reo2host-destination-ring3", 77 "reo2host-destination-ring2", 78 "reo2host-destination-ring1", 79 "rxdma2host-monitor-destination-mac3", 80 "rxdma2host-monitor-destination-mac2", 81 "rxdma2host-monitor-destination-mac1", 82 "ppdu-end-interrupts-mac3", 83 "ppdu-end-interrupts-mac2", 84 "ppdu-end-interrupts-mac1", 85 "rxdma2host-monitor-status-ring-mac3", 86 "rxdma2host-monitor-status-ring-mac2", 87 "rxdma2host-monitor-status-ring-mac1", 88 "host2rxdma-host-buf-ring-mac3", 89 "host2rxdma-host-buf-ring-mac2", 90 "host2rxdma-host-buf-ring-mac1", 91 "rxdma2host-destination-ring-mac3", 92 "rxdma2host-destination-ring-mac2", 93 "rxdma2host-destination-ring-mac1", 94 "host2tcl-input-ring4", 95 "host2tcl-input-ring3", 96 "host2tcl-input-ring2", 97 "host2tcl-input-ring1", 98 "wbm2host-tx-completions-ring3", 99 "wbm2host-tx-completions-ring2", 100 "wbm2host-tx-completions-ring1", 101 "tcl2host-status-ring", 102 }; 103 104 /** hif_ahb_get_irq_name() - get irqname 105 * This function gives irqnumber to irqname 106 * mapping. 107 * 108 * @irq_no: irq number 109 * 110 * Return: irq name 111 */ 112 const char *hif_ahb_get_irq_name(int irq_no) 113 { 114 return ic_irqname[irq_no]; 115 } 116 117 /** 118 * hif_disable_isr() - disable isr 119 * 120 * This function disables isr and kills tasklets 121 * 122 * @hif_ctx: struct hif_softc 123 * 124 * Return: void 125 */ 126 void hif_ahb_disable_isr(struct hif_softc *scn) 127 { 128 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 129 130 hif_exec_kill(&scn->osc); 131 hif_nointrs(scn); 132 ce_tasklet_kill(scn); 133 tasklet_kill(&sc->intr_tq); 134 qdf_atomic_set(&scn->active_tasklet_cnt, 0); 135 qdf_atomic_set(&scn->active_grp_tasklet_cnt, 0); 136 } 137 138 /** 139 * hif_dump_registers() - dump bus debug registers 140 * @scn: struct hif_opaque_softc 141 * 142 * This function dumps hif bus debug registers 143 * 144 * Return: 0 for success or error code 145 */ 146 int hif_ahb_dump_registers(struct hif_softc *hif_ctx) 147 { 148 int status; 149 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 150 151 status = hif_dump_ce_registers(scn); 152 if (status) 153 HIF_ERROR("%s: Dump CE Registers Failed status %d", __func__, 154 status); 155 156 return 0; 157 } 158 159 /** 160 * hif_ahb_close() - hif_bus_close 161 * @scn: pointer to the hif context. 162 * 163 * This is a callback function for hif_bus_close. 164 * 165 * 166 * Return: n/a 167 */ 168 void hif_ahb_close(struct hif_softc *scn) 169 { 170 hif_ce_close(scn); 171 } 172 173 /** 174 * hif_bus_open() - hif_ahb open 175 * @hif_ctx: hif context 176 * @bus_type: bus type 177 * 178 * This is a callback function for hif_bus_open. 179 * 180 * Return: n/a 181 */ 182 QDF_STATUS hif_ahb_open(struct hif_softc *hif_ctx, enum qdf_bus_type bus_type) 183 { 184 185 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_ctx); 186 187 qdf_spinlock_create(&sc->irq_lock); 188 return hif_ce_open(hif_ctx); 189 } 190 191 /** 192 * hif_bus_configure() - Configure the bus 193 * @scn: pointer to the hif context. 194 * 195 * This function configure the ahb bus 196 * 197 * return: 0 for success. nonzero for failure. 198 */ 199 int hif_ahb_bus_configure(struct hif_softc *scn) 200 { 201 return hif_pci_bus_configure(scn); 202 } 203 204 /** 205 * hif_configure_msi_ahb - Configure MSI interrupts 206 * @sc : pointer to the hif context 207 * 208 * return: 0 for success. nonzero for failure. 209 */ 210 211 int hif_configure_msi_ahb(struct hif_pci_softc *sc) 212 { 213 return 0; 214 } 215 216 /** 217 * hif_ahb_configure_legacy_irq() - Configure Legacy IRQ 218 * @sc: pointer to the hif context. 219 * 220 * This function registers the irq handler and enables legacy interrupts 221 * 222 * return: 0 for success. nonzero for failure. 223 */ 224 int hif_ahb_configure_legacy_irq(struct hif_pci_softc *sc) 225 { 226 int ret = 0; 227 struct hif_softc *scn = HIF_GET_SOFTC(sc); 228 struct platform_device *pdev = (struct platform_device *)sc->pdev; 229 int irq = 0; 230 231 /* do not support MSI or MSI IRQ failed */ 232 tasklet_init(&sc->intr_tq, wlan_tasklet, (unsigned long)sc); 233 qal_vbus_get_irq((struct qdf_pfm_hndl *)pdev, "legacy", &irq); 234 if (irq < 0) { 235 dev_err(&pdev->dev, "Unable to get irq\n"); 236 ret = -1; 237 goto end; 238 } 239 ret = request_irq(irq, hif_pci_legacy_ce_interrupt_handler, 240 IRQF_DISABLED, "wlan_ahb", sc); 241 if (ret) { 242 dev_err(&pdev->dev, "ath_request_irq failed\n"); 243 ret = -1; 244 goto end; 245 } 246 sc->irq = irq; 247 248 /* Use Legacy PCI Interrupts */ 249 hif_write32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS | 250 PCIE_INTR_ENABLE_ADDRESS), 251 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 252 /* read once to flush */ 253 hif_read32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS | 254 PCIE_INTR_ENABLE_ADDRESS)); 255 256 end: 257 return ret; 258 } 259 260 int hif_ahb_configure_irq(struct hif_pci_softc *sc) 261 { 262 int ret = 0; 263 struct hif_softc *scn = HIF_GET_SOFTC(sc); 264 struct platform_device *pdev = (struct platform_device *)sc->pdev; 265 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 266 struct CE_attr *host_ce_conf = hif_state->host_ce_config; 267 int irq = 0; 268 int i; 269 270 /* configure per CE interrupts */ 271 for (i = 0; i < scn->ce_count; i++) { 272 if (host_ce_conf[i].flags & CE_ATTR_DISABLE_INTR) 273 continue; 274 qal_vbus_get_irq((struct qdf_pfm_hndl *)pdev, 275 ic_irqname[HIF_IC_CE0_IRQ_OFFSET + i], &irq); 276 ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i] = irq; 277 ret = request_irq(irq , 278 hif_ahb_interrupt_handler, 279 IRQF_TRIGGER_RISING, ic_irqname[HIF_IC_CE0_IRQ_OFFSET + i], 280 &hif_state->tasklets[i]); 281 if (ret) { 282 dev_err(&pdev->dev, "ath_request_irq failed\n"); 283 ret = -1; 284 goto end; 285 } 286 hif_ahb_irq_enable(scn, i); 287 } 288 289 end: 290 return ret; 291 } 292 293 int hif_ahb_configure_grp_irq(struct hif_softc *scn, 294 struct hif_exec_context *hif_ext_group) 295 { 296 int ret = 0; 297 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 298 struct platform_device *pdev = (struct platform_device *)sc->pdev; 299 int irq = 0; 300 int j; 301 302 /* configure external interrupts */ 303 hif_ext_group->irq_enable = &hif_ahb_exec_grp_irq_enable; 304 hif_ext_group->irq_disable = &hif_ahb_exec_grp_irq_disable; 305 hif_ext_group->irq_name = &hif_ahb_get_irq_name; 306 hif_ext_group->work_complete = &hif_dummy_grp_done; 307 308 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 309 310 for (j = 0; j < hif_ext_group->numirq; j++) { 311 qal_vbus_get_irq((struct qdf_pfm_hndl *)pdev, 312 ic_irqname[hif_ext_group->irq[j]], &irq); 313 314 ic_irqnum[hif_ext_group->irq[j]] = irq; 315 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); 316 ret = request_irq(irq, hif_ext_group_interrupt_handler, 317 IRQF_TRIGGER_RISING, 318 ic_irqname[hif_ext_group->irq[j]], 319 hif_ext_group); 320 if (ret) { 321 dev_err(&pdev->dev, 322 "ath_request_irq failed\n"); 323 ret = -1; 324 goto end; 325 } 326 hif_ext_group->os_irq[j] = irq; 327 } 328 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 329 330 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 331 hif_ext_group->irq_requested = true; 332 333 end: 334 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 335 return ret; 336 } 337 338 void hif_ahb_deconfigure_grp_irq(struct hif_softc *scn) 339 { 340 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 341 struct hif_exec_context *hif_ext_group; 342 int i, j; 343 int irq = 0; 344 345 /* configure external interrupts */ 346 for (i = 0; i < hif_state->hif_num_extgroup; i++) { 347 hif_ext_group = hif_state->hif_ext_group[i]; 348 if (hif_ext_group->irq_requested == true) { 349 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 350 hif_ext_group->irq_requested = false; 351 for (j = 0; j < hif_ext_group->numirq; j++) { 352 irq = hif_ext_group->os_irq[j]; 353 irq_clear_status_flags(irq, 354 IRQ_DISABLE_UNLAZY); 355 free_irq(irq, hif_ext_group); 356 } 357 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 358 } 359 } 360 } 361 362 irqreturn_t hif_ahb_interrupt_handler(int irq, void *context) 363 { 364 struct ce_tasklet_entry *tasklet_entry = context; 365 return ce_dispatch_interrupt(tasklet_entry->ce_id, tasklet_entry); 366 } 367 368 /** 369 * hif_target_sync() : ensure the target is ready 370 * @scn: hif control structure 371 * 372 * Informs fw that we plan to use legacy interupts so that 373 * it can begin booting. Ensures that the fw finishes booting 374 * before continuing. Should be called before trying to write 375 * to the targets other registers for the first time. 376 * 377 * Return: none 378 */ 379 int hif_target_sync_ahb(struct hif_softc *scn) 380 { 381 int val = 0; 382 int limit = 0; 383 384 while (limit < 50) { 385 hif_write32_mb(scn, scn->mem + 386 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS), 387 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 388 qdf_mdelay(10); 389 val = hif_read32_mb(scn, scn->mem + 390 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS)); 391 if (val == 0) 392 break; 393 limit++; 394 } 395 hif_write32_mb(scn, scn->mem + 396 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS), 397 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 398 hif_write32_mb(scn, scn->mem + FW_INDICATOR_ADDRESS, FW_IND_HOST_READY); 399 if (HAS_FW_INDICATOR) { 400 int wait_limit = 500; 401 int fw_ind = 0; 402 403 while (1) { 404 fw_ind = hif_read32_mb(scn, scn->mem + 405 FW_INDICATOR_ADDRESS); 406 if (fw_ind & FW_IND_INITIALIZED) 407 break; 408 if (wait_limit-- < 0) 409 break; 410 hif_write32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS | 411 PCIE_INTR_ENABLE_ADDRESS), 412 PCIE_INTR_FIRMWARE_MASK); 413 qdf_mdelay(10); 414 } 415 if (wait_limit < 0) { 416 HIF_TRACE("%s: FW signal timed out", __func__); 417 return -EIO; 418 } 419 HIF_TRACE("%s: Got FW signal, retries = %x", __func__, 420 500-wait_limit); 421 } 422 423 return 0; 424 } 425 426 /** 427 * hif_disable_bus() - Disable the bus 428 * @scn : pointer to the hif context 429 * 430 * This function disables the bus and helds the target in reset state 431 * 432 * Return: none 433 */ 434 void hif_ahb_disable_bus(struct hif_softc *scn) 435 { 436 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 437 void __iomem *mem; 438 struct platform_device *pdev = (struct platform_device *)sc->pdev; 439 struct resource *memres = NULL; 440 int mem_pa_size = 0; 441 struct hif_target_info *tgt_info = NULL; 442 struct qdf_vbus_resource *vmres = NULL; 443 444 tgt_info = &scn->target_info; 445 /*Disable WIFI clock input*/ 446 if (sc->mem) { 447 qal_vbus_get_resource((struct qdf_pfm_hndl *)pdev, &vmres, 448 IORESOURCE_MEM, 0); 449 memres = (struct resource *)vmres; 450 if (!memres) { 451 HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", 452 __func__); 453 return; 454 } 455 mem_pa_size = memres->end - memres->start + 1; 456 457 /* Should not be executed on 8074 platform */ 458 if ((tgt_info->target_type != TARGET_TYPE_QCA8074) && 459 (tgt_info->target_type != TARGET_TYPE_QCA8074V2) && 460 (tgt_info->target_type != TARGET_TYPE_QCA6018)) { 461 hif_ahb_clk_enable_disable(&pdev->dev, 0); 462 463 hif_ahb_device_reset(scn); 464 } 465 mem = (void __iomem *)sc->mem; 466 if (mem) { 467 devm_iounmap(&pdev->dev, mem); 468 devm_release_mem_region(&pdev->dev, scn->mem_pa, 469 mem_pa_size); 470 sc->mem = NULL; 471 } 472 } 473 scn->mem = NULL; 474 } 475 476 /** 477 * hif_enable_bus() - Enable the bus 478 * @dev: dev 479 * @bdev: bus dev 480 * @bid: bus id 481 * @type: bus type 482 * 483 * This function enables the radio bus by enabling necessary 484 * clocks and waits for the target to get ready to proceed futher 485 * 486 * Return: QDF_STATUS 487 */ 488 QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc, 489 struct device *dev, void *bdev, 490 const struct hif_bus_id *bid, 491 enum hif_enable_type type) 492 { 493 int ret = 0; 494 int hif_type; 495 int target_type; 496 const struct platform_device_id *id = (struct platform_device_id *)bid; 497 struct platform_device *pdev = bdev; 498 struct hif_target_info *tgt_info = NULL; 499 struct resource *memres = NULL; 500 void __iomem *mem = NULL; 501 uint32_t revision_id = 0; 502 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(ol_sc); 503 504 sc->pdev = (struct pci_dev *)pdev; 505 sc->dev = &pdev->dev; 506 sc->devid = id->driver_data; 507 508 ret = hif_get_device_type(id->driver_data, revision_id, 509 &hif_type, &target_type); 510 if (ret < 0) { 511 HIF_ERROR("%s: invalid device ret %d id %d revision_id %d", 512 __func__, ret, (int)id->driver_data, revision_id); 513 return QDF_STATUS_E_FAILURE; 514 } 515 516 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 517 if (!memres) { 518 HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", __func__); 519 return -EIO; 520 } 521 522 ret = dma_set_mask(dev, DMA_BIT_MASK(32)); 523 if (ret) { 524 HIF_INFO("ath: 32-bit DMA not available\n"); 525 goto err_cleanup1; 526 } 527 528 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) 529 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 530 #else 531 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); 532 #endif 533 if (ret) { 534 HIF_ERROR("%s: failed to set dma mask error = %d", 535 __func__, ret); 536 return ret; 537 } 538 539 /* Arrange for access to Target SoC registers. */ 540 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) 541 mem = devm_ioremap_resource(&pdev->dev, memres); 542 #else 543 mem = devm_request_and_ioremap(&pdev->dev, memres); 544 #endif 545 if (IS_ERR(mem)) { 546 HIF_INFO("ath: ioremap error\n"); 547 ret = PTR_ERR(mem); 548 goto err_cleanup1; 549 } 550 551 sc->mem = mem; 552 ol_sc->mem = mem; 553 ol_sc->mem_pa = memres->start; 554 555 tgt_info = hif_get_target_info_handle((struct hif_opaque_softc *)ol_sc); 556 557 tgt_info->target_type = target_type; 558 hif_register_tbl_attach(ol_sc, hif_type); 559 hif_target_register_tbl_attach(ol_sc, target_type); 560 561 /* QCA_WIFI_QCA8074_VP:Should not be executed on 8074 VP platform */ 562 if ((tgt_info->target_type != TARGET_TYPE_QCA8074) && 563 (tgt_info->target_type != TARGET_TYPE_QCA8074V2) && 564 (tgt_info->target_type != TARGET_TYPE_QCA6018)) { 565 if (hif_ahb_enable_radio(sc, pdev, id) != 0) { 566 HIF_INFO("error in enabling soc\n"); 567 return -EIO; 568 } 569 570 if (hif_target_sync_ahb(ol_sc) < 0) { 571 ret = -EIO; 572 goto err_target_sync; 573 } 574 } 575 HIF_TRACE("%s: X - hif_type = 0x%x, target_type = 0x%x", 576 __func__, hif_type, target_type); 577 578 return QDF_STATUS_SUCCESS; 579 err_target_sync: 580 /* QCA_WIFI_QCA8074_VP:Should not be executed on 8074 VP platform */ 581 if ((tgt_info->target_type != TARGET_TYPE_QCA8074) && 582 (tgt_info->target_type != TARGET_TYPE_QCA8074V2) && 583 (tgt_info->target_type != TARGET_TYPE_QCA6018)) { 584 HIF_INFO("Error: Disabling target\n"); 585 hif_ahb_disable_bus(ol_sc); 586 } 587 err_cleanup1: 588 return ret; 589 } 590 591 592 /** 593 * hif_reset_soc() - reset soc 594 * 595 * @hif_ctx: HIF context 596 * 597 * This function resets soc and helds the 598 * target in reset state 599 * 600 * Return: void 601 */ 602 /* Function to reset SoC */ 603 void hif_ahb_reset_soc(struct hif_softc *hif_ctx) 604 { 605 hif_ahb_device_reset(hif_ctx); 606 } 607 608 609 /** 610 * hif_nointrs() - disable IRQ 611 * 612 * @scn: struct hif_softc 613 * 614 * This function stops interrupt(s) 615 * 616 * Return: none 617 */ 618 void hif_ahb_nointrs(struct hif_softc *scn) 619 { 620 int i; 621 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 622 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 623 struct CE_attr *host_ce_conf = hif_state->host_ce_config; 624 625 ce_unregister_irq(hif_state, CE_ALL_BITMAP); 626 627 if (scn->request_irq_done == false) 628 return; 629 630 if (sc->num_msi_intrs > 0) { 631 /* MSI interrupt(s) */ 632 for (i = 0; i < sc->num_msi_intrs; i++) { 633 free_irq(sc->irq + i, sc); 634 } 635 sc->num_msi_intrs = 0; 636 } else { 637 if (!scn->per_ce_irq) { 638 free_irq(sc->irq, sc); 639 } else { 640 for (i = 0; i < scn->ce_count; i++) { 641 if (host_ce_conf[i].flags 642 & CE_ATTR_DISABLE_INTR) 643 continue; 644 645 free_irq(ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i], 646 &hif_state->tasklets[i]); 647 } 648 hif_ahb_deconfigure_grp_irq(scn); 649 } 650 } 651 scn->request_irq_done = false; 652 653 } 654 655 /** 656 * ce_irq_enable() - enable copy engine IRQ 657 * @scn: struct hif_softc 658 * @ce_id: ce_id 659 * 660 * This function enables the interrupt for the radio. 661 * 662 * Return: N/A 663 */ 664 void hif_ahb_irq_enable(struct hif_softc *scn, int ce_id) 665 { 666 uint32_t regval; 667 uint32_t reg_offset = 0; 668 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 669 struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id]; 670 struct hif_target_info *tgt_info = &scn->target_info; 671 672 if (scn->per_ce_irq) { 673 if (target_ce_conf->pipedir & PIPEDIR_OUT) { 674 reg_offset = HOST_IE_ADDRESS; 675 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 676 regval = hif_read32_mb(scn, scn->mem + reg_offset); 677 regval |= HOST_IE_REG1_CE_BIT(ce_id); 678 hif_write32_mb(scn, scn->mem + reg_offset, regval); 679 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 680 } 681 if (target_ce_conf->pipedir & PIPEDIR_IN) { 682 reg_offset = HOST_IE_ADDRESS_2; 683 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 684 regval = hif_read32_mb(scn, scn->mem + reg_offset); 685 regval |= HOST_IE_REG2_CE_BIT(ce_id); 686 hif_write32_mb(scn, scn->mem + reg_offset, regval); 687 if (tgt_info->target_type == TARGET_TYPE_QCA8074 || 688 tgt_info->target_type == TARGET_TYPE_QCA8074V2 || 689 tgt_info->target_type == TARGET_TYPE_QCA6018) { 690 /* Enable destination ring interrupts for 691 * 8074, 8074V2 and 6018 692 */ 693 regval = hif_read32_mb(scn, scn->mem + 694 HOST_IE_ADDRESS_3); 695 regval |= HOST_IE_REG3_CE_BIT(ce_id); 696 697 hif_write32_mb(scn, scn->mem + 698 HOST_IE_ADDRESS_3, regval); 699 } 700 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 701 } 702 } else { 703 hif_pci_irq_enable(scn, ce_id); 704 } 705 } 706 707 /** 708 * ce_irq_disable() - disable copy engine IRQ 709 * @scn: struct hif_softc 710 * @ce_id: ce_id 711 * 712 * Return: N/A 713 */ 714 void hif_ahb_irq_disable(struct hif_softc *scn, int ce_id) 715 { 716 uint32_t regval; 717 uint32_t reg_offset = 0; 718 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 719 struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id]; 720 struct hif_target_info *tgt_info = &scn->target_info; 721 722 if (scn->per_ce_irq) { 723 if (target_ce_conf->pipedir & PIPEDIR_OUT) { 724 reg_offset = HOST_IE_ADDRESS; 725 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 726 regval = hif_read32_mb(scn, scn->mem + reg_offset); 727 regval &= ~HOST_IE_REG1_CE_BIT(ce_id); 728 hif_write32_mb(scn, scn->mem + reg_offset, regval); 729 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 730 } 731 if (target_ce_conf->pipedir & PIPEDIR_IN) { 732 reg_offset = HOST_IE_ADDRESS_2; 733 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 734 regval = hif_read32_mb(scn, scn->mem + reg_offset); 735 regval &= ~HOST_IE_REG2_CE_BIT(ce_id); 736 hif_write32_mb(scn, scn->mem + reg_offset, regval); 737 if (tgt_info->target_type == TARGET_TYPE_QCA8074 || 738 tgt_info->target_type == TARGET_TYPE_QCA8074V2 || 739 tgt_info->target_type == TARGET_TYPE_QCA6018) { 740 /* Disable destination ring interrupts for 741 * 8074, 8074V2 and 6018 742 */ 743 regval = hif_read32_mb(scn, scn->mem + 744 HOST_IE_ADDRESS_3); 745 regval &= ~HOST_IE_REG3_CE_BIT(ce_id); 746 747 hif_write32_mb(scn, scn->mem + 748 HOST_IE_ADDRESS_3, regval); 749 } 750 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 751 } 752 } 753 } 754 755 void hif_ahb_exec_grp_irq_disable(struct hif_exec_context *hif_ext_group) 756 { 757 int i; 758 759 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 760 if (hif_ext_group->irq_enabled) { 761 for (i = 0; i < hif_ext_group->numirq; i++) { 762 disable_irq_nosync(hif_ext_group->os_irq[i]); 763 } 764 hif_ext_group->irq_enabled = false; 765 } 766 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 767 } 768 769 void hif_ahb_exec_grp_irq_enable(struct hif_exec_context *hif_ext_group) 770 { 771 int i; 772 773 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 774 if (!hif_ext_group->irq_enabled) { 775 for (i = 0; i < hif_ext_group->numirq; i++) { 776 enable_irq(hif_ext_group->os_irq[i]); 777 } 778 hif_ext_group->irq_enabled = true; 779 } 780 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 781 } 782 783 /** 784 * hif_ahb_needs_bmi() - return true if the soc needs bmi through the driver 785 * @scn: hif context 786 * 787 * Return: true if soc needs driver bmi otherwise false 788 */ 789 bool hif_ahb_needs_bmi(struct hif_softc *scn) 790 { 791 return !ce_srng_based(scn); 792 } 793