1 /* 2 * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /** 20 * DOC: if_ahb.c 21 * 22 * c file for ahb specific implementations. 23 */ 24 25 #include "hif.h" 26 #include "target_type.h" 27 #include "hif_main.h" 28 #include "hif_debug.h" 29 #include "hif_io32.h" 30 #include "ce_main.h" 31 #include "ce_api.h" 32 #include "ce_tasklet.h" 33 #include "if_ahb.h" 34 #include "if_pci.h" 35 #include "ahb_api.h" 36 #include "pci_api.h" 37 #include "hif_napi.h" 38 39 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) 40 #define IRQF_DISABLED 0x00000020 41 #endif 42 43 #define HIF_IC_CE0_IRQ_OFFSET 4 44 #define HIF_IC_MAX_IRQ 54 45 46 static uint8_t ic_irqnum[HIF_IC_MAX_IRQ]; 47 /* integrated chip irq names */ 48 const char *ic_irqname[HIF_IC_MAX_IRQ] = { 49 "misc-pulse1", 50 "misc-latch", 51 "sw-exception", 52 "watchdog", 53 "ce0", 54 "ce1", 55 "ce2", 56 "ce3", 57 "ce4", 58 "ce5", 59 "ce6", 60 "ce7", 61 "ce8", 62 "ce9", 63 "ce10", 64 "ce11", 65 "ce12", 66 "ce13", 67 "host2wbm-desc-feed", 68 "host2reo-re-injection", 69 "host2reo-command", 70 "host2rxdma-monitor-ring3", 71 "host2rxdma-monitor-ring2", 72 "host2rxdma-monitor-ring1", 73 "reo2ost-exception", 74 "wbm2host-rx-release", 75 "reo2host-status", 76 "reo2host-destination-ring4", 77 "reo2host-destination-ring3", 78 "reo2host-destination-ring2", 79 "reo2host-destination-ring1", 80 "rxdma2host-monitor-destination-mac3", 81 "rxdma2host-monitor-destination-mac2", 82 "rxdma2host-monitor-destination-mac1", 83 "ppdu-end-interrupts-mac3", 84 "ppdu-end-interrupts-mac2", 85 "ppdu-end-interrupts-mac1", 86 "rxdma2host-monitor-status-ring-mac3", 87 "rxdma2host-monitor-status-ring-mac2", 88 "rxdma2host-monitor-status-ring-mac1", 89 "host2rxdma-host-buf-ring-mac3", 90 "host2rxdma-host-buf-ring-mac2", 91 "host2rxdma-host-buf-ring-mac1", 92 "rxdma2host-destination-ring-mac3", 93 "rxdma2host-destination-ring-mac2", 94 "rxdma2host-destination-ring-mac1", 95 "host2tcl-input-ring4", 96 "host2tcl-input-ring3", 97 "host2tcl-input-ring2", 98 "host2tcl-input-ring1", 99 "wbm2host-tx-completions-ring3", 100 "wbm2host-tx-completions-ring2", 101 "wbm2host-tx-completions-ring1", 102 "tcl2host-status-ring", 103 }; 104 105 /** 106 * hif_disable_isr() - disable isr 107 * 108 * This function disables isr and kills tasklets 109 * 110 * @hif_ctx: struct hif_softc 111 * 112 * Return: void 113 */ 114 void hif_ahb_disable_isr(struct hif_softc *scn) 115 { 116 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 117 118 hif_exec_kill(&scn->osc); 119 hif_nointrs(scn); 120 ce_tasklet_kill(scn); 121 tasklet_kill(&sc->intr_tq); 122 qdf_atomic_set(&scn->active_tasklet_cnt, 0); 123 qdf_atomic_set(&scn->active_grp_tasklet_cnt, 0); 124 } 125 126 /** 127 * hif_dump_registers() - dump bus debug registers 128 * @scn: struct hif_opaque_softc 129 * 130 * This function dumps hif bus debug registers 131 * 132 * Return: 0 for success or error code 133 */ 134 int hif_ahb_dump_registers(struct hif_softc *hif_ctx) 135 { 136 int status; 137 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 138 139 status = hif_dump_ce_registers(scn); 140 if (status) 141 HIF_ERROR("%s: Dump CE Registers Failed status %d", __func__, 142 status); 143 144 return 0; 145 } 146 147 /** 148 * hif_ahb_close() - hif_bus_close 149 * @scn: pointer to the hif context. 150 * 151 * This is a callback function for hif_bus_close. 152 * 153 * 154 * Return: n/a 155 */ 156 void hif_ahb_close(struct hif_softc *scn) 157 { 158 hif_ce_close(scn); 159 } 160 161 /** 162 * hif_bus_open() - hif_ahb open 163 * @hif_ctx: hif context 164 * @bus_type: bus type 165 * 166 * This is a callback function for hif_bus_open. 167 * 168 * Return: n/a 169 */ 170 QDF_STATUS hif_ahb_open(struct hif_softc *hif_ctx, enum qdf_bus_type bus_type) 171 { 172 173 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_ctx); 174 175 qdf_spinlock_create(&sc->irq_lock); 176 return hif_ce_open(hif_ctx); 177 } 178 179 /** 180 * hif_bus_configure() - Configure the bus 181 * @scn: pointer to the hif context. 182 * 183 * This function configure the ahb bus 184 * 185 * return: 0 for success. nonzero for failure. 186 */ 187 int hif_ahb_bus_configure(struct hif_softc *scn) 188 { 189 return hif_pci_bus_configure(scn); 190 } 191 192 /** 193 * hif_configure_msi_ahb - Configure MSI interrupts 194 * @sc : pointer to the hif context 195 * 196 * return: 0 for success. nonzero for failure. 197 */ 198 199 int hif_configure_msi_ahb(struct hif_pci_softc *sc) 200 { 201 return 0; 202 } 203 204 /** 205 * hif_ahb_configure_legacy_irq() - Configure Legacy IRQ 206 * @sc: pointer to the hif context. 207 * 208 * This function registers the irq handler and enables legacy interrupts 209 * 210 * return: 0 for success. nonzero for failure. 211 */ 212 int hif_ahb_configure_legacy_irq(struct hif_pci_softc *sc) 213 { 214 int ret = 0; 215 struct hif_softc *scn = HIF_GET_SOFTC(sc); 216 struct platform_device *pdev = (struct platform_device *)sc->pdev; 217 int irq = 0; 218 219 /* do not support MSI or MSI IRQ failed */ 220 tasklet_init(&sc->intr_tq, wlan_tasklet, (unsigned long)sc); 221 irq = platform_get_irq_byname(pdev, "legacy"); 222 if (irq < 0) { 223 dev_err(&pdev->dev, "Unable to get irq\n"); 224 ret = -1; 225 goto end; 226 } 227 ret = request_irq(irq, hif_pci_legacy_ce_interrupt_handler, 228 IRQF_DISABLED, "wlan_ahb", sc); 229 if (ret) { 230 dev_err(&pdev->dev, "ath_request_irq failed\n"); 231 ret = -1; 232 goto end; 233 } 234 sc->irq = irq; 235 236 /* Use Legacy PCI Interrupts */ 237 hif_write32_mb(sc->mem+(SOC_CORE_BASE_ADDRESS | 238 PCIE_INTR_ENABLE_ADDRESS), 239 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 240 /* read once to flush */ 241 hif_read32_mb(sc->mem+(SOC_CORE_BASE_ADDRESS | 242 PCIE_INTR_ENABLE_ADDRESS) 243 ); 244 245 end: 246 return ret; 247 } 248 249 int hif_ahb_configure_irq(struct hif_pci_softc *sc) 250 { 251 int ret = 0; 252 struct hif_softc *scn = HIF_GET_SOFTC(sc); 253 struct platform_device *pdev = (struct platform_device *)sc->pdev; 254 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 255 int irq = 0; 256 int i; 257 258 /* configure per CE interrupts */ 259 for (i = 0; i < scn->ce_count; i++) { 260 irq = platform_get_irq_byname(pdev, ic_irqname[HIF_IC_CE0_IRQ_OFFSET + i]); 261 ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i] = irq; 262 ret = request_irq(irq , 263 hif_ahb_interrupt_handler, 264 IRQF_TRIGGER_RISING, ic_irqname[HIF_IC_CE0_IRQ_OFFSET + i], 265 &hif_state->tasklets[i]); 266 if (ret) { 267 dev_err(&pdev->dev, "ath_request_irq failed\n"); 268 ret = -1; 269 goto end; 270 } 271 hif_ahb_irq_enable(scn, i); 272 } 273 274 end: 275 return ret; 276 } 277 278 int hif_ahb_configure_grp_irq(struct hif_softc *scn, 279 struct hif_exec_context *hif_ext_group) 280 { 281 int ret = 0; 282 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 283 struct platform_device *pdev = (struct platform_device *)sc->pdev; 284 int irq = 0; 285 const char *irq_name; 286 int j; 287 288 /* configure external interrupts */ 289 hif_ext_group->irq_enable = &hif_ahb_exec_grp_irq_enable; 290 hif_ext_group->irq_disable = &hif_ahb_exec_grp_irq_disable; 291 hif_ext_group->work_complete = &hif_dummy_grp_done; 292 293 hif_ext_group->irq_requested = true; 294 295 for (j = 0; j < hif_ext_group->numirq; j++) { 296 irq_name = ic_irqname[hif_ext_group->irq[j]]; 297 irq = platform_get_irq_byname(pdev, irq_name); 298 299 ic_irqnum[hif_ext_group->irq[j]] = irq; 300 ret = request_irq(irq, hif_ext_group_interrupt_handler, 301 IRQF_TRIGGER_RISING, 302 ic_irqname[hif_ext_group->irq[j]], 303 hif_ext_group); 304 if (ret) { 305 dev_err(&pdev->dev, 306 "ath_request_irq failed\n"); 307 ret = -1; 308 goto end; 309 } 310 hif_ext_group->os_irq[j] = irq; 311 } 312 313 end: 314 return ret; 315 } 316 317 void hif_ahb_deconfigure_grp_irq(struct hif_softc *scn) 318 { 319 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 320 struct hif_exec_context *hif_ext_group; 321 int i, j; 322 323 /* configure external interrupts */ 324 for (i = 0; i < hif_state->hif_num_extgroup; i++) { 325 hif_ext_group = hif_state->hif_ext_group[i]; 326 if (hif_ext_group->irq_requested == true) { 327 hif_ext_group->irq_requested = false; 328 for (j = 0; j < hif_ext_group->numirq; j++) { 329 free_irq(hif_ext_group->os_irq[j], 330 hif_ext_group); 331 } 332 } 333 } 334 } 335 336 irqreturn_t hif_ahb_interrupt_handler(int irq, void *context) 337 { 338 struct ce_tasklet_entry *tasklet_entry = context; 339 return ce_dispatch_interrupt(tasklet_entry->ce_id, tasklet_entry); 340 } 341 342 /** 343 * hif_target_sync() : ensure the target is ready 344 * @scn: hif control structure 345 * 346 * Informs fw that we plan to use legacy interupts so that 347 * it can begin booting. Ensures that the fw finishes booting 348 * before continuing. Should be called before trying to write 349 * to the targets other registers for the first time. 350 * 351 * Return: none 352 */ 353 int hif_target_sync_ahb(struct hif_softc *scn) 354 { 355 hif_write32_mb(scn->mem + FW_INDICATOR_ADDRESS, FW_IND_HOST_READY); 356 if (HAS_FW_INDICATOR) { 357 int wait_limit = 500; 358 int fw_ind = 0; 359 360 while (1) { 361 fw_ind = hif_read32_mb(scn->mem + 362 FW_INDICATOR_ADDRESS); 363 if (fw_ind & FW_IND_INITIALIZED) 364 break; 365 if (wait_limit-- < 0) 366 break; 367 hif_write32_mb(scn->mem+(SOC_CORE_BASE_ADDRESS | 368 PCIE_INTR_ENABLE_ADDRESS), 369 PCIE_INTR_FIRMWARE_MASK); 370 qdf_mdelay(10); 371 } 372 if (wait_limit < 0) { 373 HIF_TRACE("%s: FW signal timed out", __func__); 374 return -EIO; 375 } 376 HIF_TRACE("%s: Got FW signal, retries = %x", __func__, 377 500-wait_limit); 378 } 379 380 return 0; 381 } 382 383 /** 384 * hif_disable_bus() - Disable the bus 385 * @scn : pointer to the hif context 386 * 387 * This function disables the bus and helds the target in reset state 388 * 389 * Return: none 390 */ 391 void hif_ahb_disable_bus(struct hif_softc *scn) 392 { 393 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 394 void __iomem *mem; 395 struct platform_device *pdev = (struct platform_device *)sc->pdev; 396 struct resource *memres = NULL; 397 int mem_pa_size = 0; 398 struct hif_target_info *tgt_info = NULL; 399 400 tgt_info = &scn->target_info; 401 /*Disable WIFI clock input*/ 402 if (sc->mem) { 403 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 404 if (!memres) { 405 HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", 406 __func__); 407 return; 408 } 409 mem_pa_size = memres->end - memres->start + 1; 410 411 /* Should not be executed on 8074 platform */ 412 if (tgt_info->target_type != TARGET_TYPE_QCA8074) { 413 hif_ahb_clk_enable_disable(&pdev->dev, 0); 414 415 hif_ahb_device_reset(scn); 416 } 417 mem = (void __iomem *)sc->mem; 418 if (mem) { 419 devm_iounmap(&pdev->dev, mem); 420 devm_release_mem_region(&pdev->dev, scn->mem_pa, 421 mem_pa_size); 422 sc->mem = NULL; 423 } 424 } 425 scn->mem = NULL; 426 } 427 428 /** 429 * hif_enable_bus() - Enable the bus 430 * @dev: dev 431 * @bdev: bus dev 432 * @bid: bus id 433 * @type: bus type 434 * 435 * This function enables the radio bus by enabling necessary 436 * clocks and waits for the target to get ready to proceed futher 437 * 438 * Return: QDF_STATUS 439 */ 440 QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc, 441 struct device *dev, void *bdev, 442 const struct hif_bus_id *bid, 443 enum hif_enable_type type) 444 { 445 int ret = 0; 446 int hif_type; 447 int target_type; 448 const struct platform_device_id *id = (struct platform_device_id *)bid; 449 struct platform_device *pdev = bdev; 450 struct hif_target_info *tgt_info = NULL; 451 struct resource *memres = NULL; 452 void __iomem *mem = NULL; 453 uint32_t revision_id = 0; 454 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(ol_sc); 455 456 sc->pdev = (struct pci_dev *)pdev; 457 sc->dev = &pdev->dev; 458 sc->devid = id->driver_data; 459 460 ret = hif_get_device_type(id->driver_data, revision_id, 461 &hif_type, &target_type); 462 if (ret < 0) { 463 HIF_ERROR("%s: invalid device ret %d id %d revision_id %d", 464 __func__, ret, (int)id->driver_data, revision_id); 465 return QDF_STATUS_E_FAILURE; 466 } 467 468 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 469 if (!memres) { 470 HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", __func__); 471 return -EIO; 472 } 473 474 ret = dma_set_mask(dev, DMA_BIT_MASK(32)); 475 if (ret) { 476 HIF_INFO("ath: 32-bit DMA not available\n"); 477 goto err_cleanup1; 478 } 479 480 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) 481 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 482 #else 483 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); 484 #endif 485 if (ret) { 486 HIF_ERROR("%s: failed to set dma mask error = %d", 487 __func__, ret); 488 return ret; 489 } 490 491 /* Arrange for access to Target SoC registers. */ 492 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) 493 mem = devm_ioremap_resource(&pdev->dev, memres); 494 #else 495 mem = devm_request_and_ioremap(&pdev->dev, memres); 496 #endif 497 if (IS_ERR(mem)) { 498 HIF_INFO("ath: ioremap error\n"); 499 ret = PTR_ERR(mem); 500 goto err_cleanup1; 501 } 502 503 sc->mem = mem; 504 ol_sc->mem = mem; 505 ol_sc->mem_pa = memres->start; 506 507 tgt_info = hif_get_target_info_handle((struct hif_opaque_softc *)ol_sc); 508 509 tgt_info->target_type = target_type; 510 hif_register_tbl_attach(ol_sc, hif_type); 511 hif_target_register_tbl_attach(ol_sc, target_type); 512 513 /* QCA_WIFI_QCA8074_VP:Should not be executed on 8074 VP platform */ 514 if (tgt_info->target_type != TARGET_TYPE_QCA8074) { 515 if (hif_ahb_enable_radio(sc, pdev, id) != 0) { 516 HIF_INFO("error in enabling soc\n"); 517 return -EIO; 518 } 519 520 if (hif_target_sync_ahb(ol_sc) < 0) { 521 ret = -EIO; 522 goto err_target_sync; 523 } 524 } 525 HIF_TRACE("%s: X - hif_type = 0x%x, target_type = 0x%x", 526 __func__, hif_type, target_type); 527 528 return QDF_STATUS_SUCCESS; 529 err_target_sync: 530 /* QCA_WIFI_QCA8074_VP:Should not be executed on 8074 VP platform */ 531 if (tgt_info->target_type != TARGET_TYPE_QCA8074) { 532 HIF_INFO("Error: Disabling target\n"); 533 hif_ahb_disable_bus(ol_sc); 534 } 535 err_cleanup1: 536 return ret; 537 } 538 539 540 /** 541 * hif_reset_soc() - reset soc 542 * 543 * @hif_ctx: HIF context 544 * 545 * This function resets soc and helds the 546 * target in reset state 547 * 548 * Return: void 549 */ 550 /* Function to reset SoC */ 551 void hif_ahb_reset_soc(struct hif_softc *hif_ctx) 552 { 553 hif_ahb_device_reset(hif_ctx); 554 } 555 556 557 /** 558 * hif_nointrs() - disable IRQ 559 * 560 * @scn: struct hif_softc 561 * 562 * This function stops interrupt(s) 563 * 564 * Return: none 565 */ 566 void hif_ahb_nointrs(struct hif_softc *scn) 567 { 568 int i; 569 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 570 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 571 572 ce_unregister_irq(hif_state, CE_ALL_BITMAP); 573 574 if (scn->request_irq_done == false) 575 return; 576 577 if (sc->num_msi_intrs > 0) { 578 /* MSI interrupt(s) */ 579 for (i = 0; i < sc->num_msi_intrs; i++) { 580 free_irq(sc->irq + i, sc); 581 } 582 sc->num_msi_intrs = 0; 583 } else { 584 if (!scn->per_ce_irq) { 585 free_irq(sc->irq, sc); 586 } else { 587 for (i = 0; i < scn->ce_count; i++) { 588 free_irq(ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i], 589 &hif_state->tasklets[i]); 590 } 591 hif_ahb_deconfigure_grp_irq(scn); 592 } 593 } 594 scn->request_irq_done = false; 595 596 } 597 598 /** 599 * ce_irq_enable() - enable copy engine IRQ 600 * @scn: struct hif_softc 601 * @ce_id: ce_id 602 * 603 * This function enables the interrupt for the radio. 604 * 605 * Return: N/A 606 */ 607 void hif_ahb_irq_enable(struct hif_softc *scn, int ce_id) 608 { 609 uint32_t regval; 610 uint32_t reg_offset = 0; 611 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 612 struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id]; 613 struct hif_target_info *tgt_info = &scn->target_info; 614 615 if (scn->per_ce_irq) { 616 if (target_ce_conf->pipedir & PIPEDIR_OUT) { 617 reg_offset = HOST_IE_ADDRESS; 618 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 619 regval = hif_read32_mb(scn->mem + reg_offset); 620 regval |= HOST_IE_REG1_CE_BIT(ce_id); 621 hif_write32_mb(scn->mem + reg_offset, regval); 622 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 623 } 624 if (target_ce_conf->pipedir & PIPEDIR_IN) { 625 reg_offset = HOST_IE_ADDRESS_2; 626 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 627 regval = hif_read32_mb(scn->mem + reg_offset); 628 regval |= HOST_IE_REG2_CE_BIT(ce_id); 629 hif_write32_mb(scn->mem + reg_offset, regval); 630 if (tgt_info->target_type == TARGET_TYPE_QCA8074) { 631 /* Enable destination ring interrupts for 8074 632 * TODO: To be removed in 2.0 HW */ 633 regval = hif_read32_mb(scn->mem + 634 HOST_IE_ADDRESS_3); 635 regval |= HOST_IE_REG3_CE_BIT(ce_id); 636 } 637 hif_write32_mb(scn->mem + HOST_IE_ADDRESS_3, regval); 638 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 639 } 640 } else { 641 hif_pci_irq_enable(scn, ce_id); 642 } 643 } 644 645 /** 646 * ce_irq_disable() - disable copy engine IRQ 647 * @scn: struct hif_softc 648 * @ce_id: ce_id 649 * 650 * Return: N/A 651 */ 652 void hif_ahb_irq_disable(struct hif_softc *scn, int ce_id) 653 { 654 uint32_t regval; 655 uint32_t reg_offset = 0; 656 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 657 struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id]; 658 struct hif_target_info *tgt_info = &scn->target_info; 659 660 if (scn->per_ce_irq) { 661 if (target_ce_conf->pipedir & PIPEDIR_OUT) { 662 reg_offset = HOST_IE_ADDRESS; 663 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 664 regval = hif_read32_mb(scn->mem + reg_offset); 665 regval &= ~HOST_IE_REG1_CE_BIT(ce_id); 666 hif_write32_mb(scn->mem + reg_offset, regval); 667 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 668 } 669 if (target_ce_conf->pipedir & PIPEDIR_IN) { 670 reg_offset = HOST_IE_ADDRESS_2; 671 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 672 regval = hif_read32_mb(scn->mem + reg_offset); 673 regval &= ~HOST_IE_REG2_CE_BIT(ce_id); 674 hif_write32_mb(scn->mem + reg_offset, regval); 675 if (tgt_info->target_type == TARGET_TYPE_QCA8074) { 676 /* Disable destination ring interrupts for 8074 677 * TODO: To be removed in 2.0 HW */ 678 regval = hif_read32_mb(scn->mem + 679 HOST_IE_ADDRESS_3); 680 regval &= ~HOST_IE_REG3_CE_BIT(ce_id); 681 } 682 hif_write32_mb(scn->mem + HOST_IE_ADDRESS_3, regval); 683 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 684 } 685 } 686 } 687 688 void hif_ahb_exec_grp_irq_disable(struct hif_exec_context *hif_ext_group) 689 { 690 int i; 691 692 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 693 if (hif_ext_group->irq_enabled) { 694 for (i = 0; i < hif_ext_group->numirq; i++) { 695 disable_irq_nosync(hif_ext_group->os_irq[i]); 696 } 697 hif_ext_group->irq_enabled = false; 698 } 699 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 700 } 701 702 void hif_ahb_exec_grp_irq_enable(struct hif_exec_context *hif_ext_group) 703 { 704 int i; 705 706 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 707 if (!hif_ext_group->irq_enabled) { 708 for (i = 0; i < hif_ext_group->numirq; i++) { 709 enable_irq(hif_ext_group->os_irq[i]); 710 } 711 hif_ext_group->irq_enabled = true; 712 } 713 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 714 } 715 716 /** 717 * hif_ahb_needs_bmi() - return true if the soc needs bmi through the driver 718 * @scn: hif context 719 * 720 * Return: true if soc needs driver bmi otherwise false 721 */ 722 bool hif_ahb_needs_bmi(struct hif_softc *scn) 723 { 724 return !ce_srng_based(scn); 725 } 726