1 /* 2 * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /** 20 * DOC: if_ahb.c 21 * 22 * c file for ahb specific implementations. 23 */ 24 25 #include "hif.h" 26 #include "target_type.h" 27 #include "hif_main.h" 28 #include "hif_debug.h" 29 #include "hif_io32.h" 30 #include "ce_main.h" 31 #include "ce_api.h" 32 #include "ce_tasklet.h" 33 #include "if_ahb.h" 34 #include "if_pci.h" 35 #include "ahb_api.h" 36 #include "pci_api.h" 37 #include "hif_napi.h" 38 39 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) 40 #define IRQF_DISABLED 0x00000020 41 #endif 42 43 #define HIF_IC_CE0_IRQ_OFFSET 4 44 #define HIF_IC_MAX_IRQ 54 45 46 static uint8_t ic_irqnum[HIF_IC_MAX_IRQ]; 47 /* integrated chip irq names */ 48 const char *ic_irqname[HIF_IC_MAX_IRQ] = { 49 "misc-pulse1", 50 "misc-latch", 51 "sw-exception", 52 "watchdog", 53 "ce0", 54 "ce1", 55 "ce2", 56 "ce3", 57 "ce4", 58 "ce5", 59 "ce6", 60 "ce7", 61 "ce8", 62 "ce9", 63 "ce10", 64 "ce11", 65 "ce12", 66 "ce13", 67 "host2wbm-desc-feed", 68 "host2reo-re-injection", 69 "host2reo-command", 70 "host2rxdma-monitor-ring3", 71 "host2rxdma-monitor-ring2", 72 "host2rxdma-monitor-ring1", 73 "reo2ost-exception", 74 "wbm2host-rx-release", 75 "reo2host-status", 76 "reo2host-destination-ring4", 77 "reo2host-destination-ring3", 78 "reo2host-destination-ring2", 79 "reo2host-destination-ring1", 80 "rxdma2host-monitor-destination-mac3", 81 "rxdma2host-monitor-destination-mac2", 82 "rxdma2host-monitor-destination-mac1", 83 "ppdu-end-interrupts-mac3", 84 "ppdu-end-interrupts-mac2", 85 "ppdu-end-interrupts-mac1", 86 "rxdma2host-monitor-status-ring-mac3", 87 "rxdma2host-monitor-status-ring-mac2", 88 "rxdma2host-monitor-status-ring-mac1", 89 "host2rxdma-host-buf-ring-mac3", 90 "host2rxdma-host-buf-ring-mac2", 91 "host2rxdma-host-buf-ring-mac1", 92 "rxdma2host-destination-ring-mac3", 93 "rxdma2host-destination-ring-mac2", 94 "rxdma2host-destination-ring-mac1", 95 "host2tcl-input-ring4", 96 "host2tcl-input-ring3", 97 "host2tcl-input-ring2", 98 "host2tcl-input-ring1", 99 "wbm2host-tx-completions-ring3", 100 "wbm2host-tx-completions-ring2", 101 "wbm2host-tx-completions-ring1", 102 "tcl2host-status-ring", 103 }; 104 105 /** 106 * hif_disable_isr() - disable isr 107 * 108 * This function disables isr and kills tasklets 109 * 110 * @hif_ctx: struct hif_softc 111 * 112 * Return: void 113 */ 114 void hif_ahb_disable_isr(struct hif_softc *scn) 115 { 116 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 117 118 hif_exec_kill(&scn->osc); 119 hif_nointrs(scn); 120 ce_tasklet_kill(scn); 121 tasklet_kill(&sc->intr_tq); 122 qdf_atomic_set(&scn->active_tasklet_cnt, 0); 123 qdf_atomic_set(&scn->active_grp_tasklet_cnt, 0); 124 } 125 126 /** 127 * hif_dump_registers() - dump bus debug registers 128 * @scn: struct hif_opaque_softc 129 * 130 * This function dumps hif bus debug registers 131 * 132 * Return: 0 for success or error code 133 */ 134 int hif_ahb_dump_registers(struct hif_softc *hif_ctx) 135 { 136 int status; 137 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 138 139 status = hif_dump_ce_registers(scn); 140 if (status) 141 HIF_ERROR("%s: Dump CE Registers Failed status %d", __func__, 142 status); 143 144 return 0; 145 } 146 147 /** 148 * hif_ahb_close() - hif_bus_close 149 * @scn: pointer to the hif context. 150 * 151 * This is a callback function for hif_bus_close. 152 * 153 * 154 * Return: n/a 155 */ 156 void hif_ahb_close(struct hif_softc *scn) 157 { 158 hif_ce_close(scn); 159 } 160 161 /** 162 * hif_bus_open() - hif_ahb open 163 * @hif_ctx: hif context 164 * @bus_type: bus type 165 * 166 * This is a callback function for hif_bus_open. 167 * 168 * Return: n/a 169 */ 170 QDF_STATUS hif_ahb_open(struct hif_softc *hif_ctx, enum qdf_bus_type bus_type) 171 { 172 173 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_ctx); 174 175 qdf_spinlock_create(&sc->irq_lock); 176 return hif_ce_open(hif_ctx); 177 } 178 179 /** 180 * hif_bus_configure() - Configure the bus 181 * @scn: pointer to the hif context. 182 * 183 * This function configure the ahb bus 184 * 185 * return: 0 for success. nonzero for failure. 186 */ 187 int hif_ahb_bus_configure(struct hif_softc *scn) 188 { 189 return hif_pci_bus_configure(scn); 190 } 191 192 /** 193 * hif_configure_msi_ahb - Configure MSI interrupts 194 * @sc : pointer to the hif context 195 * 196 * return: 0 for success. nonzero for failure. 197 */ 198 199 int hif_configure_msi_ahb(struct hif_pci_softc *sc) 200 { 201 return 0; 202 } 203 204 /** 205 * hif_ahb_configure_legacy_irq() - Configure Legacy IRQ 206 * @sc: pointer to the hif context. 207 * 208 * This function registers the irq handler and enables legacy interrupts 209 * 210 * return: 0 for success. nonzero for failure. 211 */ 212 int hif_ahb_configure_legacy_irq(struct hif_pci_softc *sc) 213 { 214 int ret = 0; 215 struct hif_softc *scn = HIF_GET_SOFTC(sc); 216 struct platform_device *pdev = (struct platform_device *)sc->pdev; 217 int irq = 0; 218 219 /* do not support MSI or MSI IRQ failed */ 220 tasklet_init(&sc->intr_tq, wlan_tasklet, (unsigned long)sc); 221 irq = platform_get_irq_byname(pdev, "legacy"); 222 if (irq < 0) { 223 dev_err(&pdev->dev, "Unable to get irq\n"); 224 ret = -1; 225 goto end; 226 } 227 ret = request_irq(irq, hif_pci_legacy_ce_interrupt_handler, 228 IRQF_DISABLED, "wlan_ahb", sc); 229 if (ret) { 230 dev_err(&pdev->dev, "ath_request_irq failed\n"); 231 ret = -1; 232 goto end; 233 } 234 sc->irq = irq; 235 236 /* Use Legacy PCI Interrupts */ 237 hif_write32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS | 238 PCIE_INTR_ENABLE_ADDRESS), 239 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 240 /* read once to flush */ 241 hif_read32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS | 242 PCIE_INTR_ENABLE_ADDRESS)); 243 244 end: 245 return ret; 246 } 247 248 int hif_ahb_configure_irq(struct hif_pci_softc *sc) 249 { 250 int ret = 0; 251 struct hif_softc *scn = HIF_GET_SOFTC(sc); 252 struct platform_device *pdev = (struct platform_device *)sc->pdev; 253 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 254 struct CE_attr *host_ce_conf = hif_state->host_ce_config; 255 int irq = 0; 256 int i; 257 258 /* configure per CE interrupts */ 259 for (i = 0; i < scn->ce_count; i++) { 260 if (host_ce_conf[i].flags & CE_ATTR_DISABLE_INTR) 261 continue; 262 irq = platform_get_irq_byname(pdev, ic_irqname[HIF_IC_CE0_IRQ_OFFSET + i]); 263 ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i] = irq; 264 ret = request_irq(irq , 265 hif_ahb_interrupt_handler, 266 IRQF_TRIGGER_RISING, ic_irqname[HIF_IC_CE0_IRQ_OFFSET + i], 267 &hif_state->tasklets[i]); 268 if (ret) { 269 dev_err(&pdev->dev, "ath_request_irq failed\n"); 270 ret = -1; 271 goto end; 272 } 273 hif_ahb_irq_enable(scn, i); 274 } 275 276 end: 277 return ret; 278 } 279 280 int hif_ahb_configure_grp_irq(struct hif_softc *scn, 281 struct hif_exec_context *hif_ext_group) 282 { 283 int ret = 0; 284 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 285 struct platform_device *pdev = (struct platform_device *)sc->pdev; 286 int irq = 0; 287 const char *irq_name; 288 int j; 289 290 /* configure external interrupts */ 291 hif_ext_group->irq_enable = &hif_ahb_exec_grp_irq_enable; 292 hif_ext_group->irq_disable = &hif_ahb_exec_grp_irq_disable; 293 hif_ext_group->work_complete = &hif_dummy_grp_done; 294 295 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 296 hif_ext_group->irq_requested = true; 297 298 for (j = 0; j < hif_ext_group->numirq; j++) { 299 irq_name = ic_irqname[hif_ext_group->irq[j]]; 300 irq = platform_get_irq_byname(pdev, irq_name); 301 302 ic_irqnum[hif_ext_group->irq[j]] = irq; 303 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); 304 ret = request_irq(irq, hif_ext_group_interrupt_handler, 305 IRQF_TRIGGER_RISING, 306 ic_irqname[hif_ext_group->irq[j]], 307 hif_ext_group); 308 if (ret) { 309 dev_err(&pdev->dev, 310 "ath_request_irq failed\n"); 311 ret = -1; 312 goto end; 313 } 314 hif_ext_group->os_irq[j] = irq; 315 } 316 317 end: 318 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 319 return ret; 320 } 321 322 void hif_ahb_deconfigure_grp_irq(struct hif_softc *scn) 323 { 324 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 325 struct hif_exec_context *hif_ext_group; 326 int i, j; 327 int irq = 0; 328 329 /* configure external interrupts */ 330 for (i = 0; i < hif_state->hif_num_extgroup; i++) { 331 hif_ext_group = hif_state->hif_ext_group[i]; 332 if (hif_ext_group->irq_requested == true) { 333 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 334 hif_ext_group->irq_requested = false; 335 for (j = 0; j < hif_ext_group->numirq; j++) { 336 irq = hif_ext_group->os_irq[j]; 337 irq_clear_status_flags(irq, 338 IRQ_DISABLE_UNLAZY); 339 free_irq(irq, hif_ext_group); 340 } 341 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 342 } 343 } 344 } 345 346 irqreturn_t hif_ahb_interrupt_handler(int irq, void *context) 347 { 348 struct ce_tasklet_entry *tasklet_entry = context; 349 return ce_dispatch_interrupt(tasklet_entry->ce_id, tasklet_entry); 350 } 351 352 /** 353 * hif_target_sync() : ensure the target is ready 354 * @scn: hif control structure 355 * 356 * Informs fw that we plan to use legacy interupts so that 357 * it can begin booting. Ensures that the fw finishes booting 358 * before continuing. Should be called before trying to write 359 * to the targets other registers for the first time. 360 * 361 * Return: none 362 */ 363 int hif_target_sync_ahb(struct hif_softc *scn) 364 { 365 int val = 0; 366 int limit = 0; 367 368 while (limit < 50) { 369 hif_write32_mb(scn, scn->mem + 370 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS), 371 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 372 qdf_mdelay(10); 373 val = hif_read32_mb(scn, scn->mem + 374 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS)); 375 if (val == 0) 376 break; 377 limit++; 378 } 379 hif_write32_mb(scn, scn->mem + 380 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS), 381 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 382 hif_write32_mb(scn, scn->mem + FW_INDICATOR_ADDRESS, FW_IND_HOST_READY); 383 if (HAS_FW_INDICATOR) { 384 int wait_limit = 500; 385 int fw_ind = 0; 386 387 while (1) { 388 fw_ind = hif_read32_mb(scn, scn->mem + 389 FW_INDICATOR_ADDRESS); 390 if (fw_ind & FW_IND_INITIALIZED) 391 break; 392 if (wait_limit-- < 0) 393 break; 394 hif_write32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS | 395 PCIE_INTR_ENABLE_ADDRESS), 396 PCIE_INTR_FIRMWARE_MASK); 397 qdf_mdelay(10); 398 } 399 if (wait_limit < 0) { 400 HIF_TRACE("%s: FW signal timed out", __func__); 401 return -EIO; 402 } 403 HIF_TRACE("%s: Got FW signal, retries = %x", __func__, 404 500-wait_limit); 405 } 406 407 return 0; 408 } 409 410 /** 411 * hif_disable_bus() - Disable the bus 412 * @scn : pointer to the hif context 413 * 414 * This function disables the bus and helds the target in reset state 415 * 416 * Return: none 417 */ 418 void hif_ahb_disable_bus(struct hif_softc *scn) 419 { 420 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 421 void __iomem *mem; 422 struct platform_device *pdev = (struct platform_device *)sc->pdev; 423 struct resource *memres = NULL; 424 int mem_pa_size = 0; 425 struct hif_target_info *tgt_info = NULL; 426 427 tgt_info = &scn->target_info; 428 /*Disable WIFI clock input*/ 429 if (sc->mem) { 430 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 431 if (!memres) { 432 HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", 433 __func__); 434 return; 435 } 436 mem_pa_size = memres->end - memres->start + 1; 437 438 /* Should not be executed on 8074 platform */ 439 if (tgt_info->target_type != TARGET_TYPE_QCA8074) { 440 hif_ahb_clk_enable_disable(&pdev->dev, 0); 441 442 hif_ahb_device_reset(scn); 443 } 444 mem = (void __iomem *)sc->mem; 445 if (mem) { 446 devm_iounmap(&pdev->dev, mem); 447 devm_release_mem_region(&pdev->dev, scn->mem_pa, 448 mem_pa_size); 449 sc->mem = NULL; 450 } 451 } 452 scn->mem = NULL; 453 } 454 455 /** 456 * hif_enable_bus() - Enable the bus 457 * @dev: dev 458 * @bdev: bus dev 459 * @bid: bus id 460 * @type: bus type 461 * 462 * This function enables the radio bus by enabling necessary 463 * clocks and waits for the target to get ready to proceed futher 464 * 465 * Return: QDF_STATUS 466 */ 467 QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc, 468 struct device *dev, void *bdev, 469 const struct hif_bus_id *bid, 470 enum hif_enable_type type) 471 { 472 int ret = 0; 473 int hif_type; 474 int target_type; 475 const struct platform_device_id *id = (struct platform_device_id *)bid; 476 struct platform_device *pdev = bdev; 477 struct hif_target_info *tgt_info = NULL; 478 struct resource *memres = NULL; 479 void __iomem *mem = NULL; 480 uint32_t revision_id = 0; 481 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(ol_sc); 482 483 sc->pdev = (struct pci_dev *)pdev; 484 sc->dev = &pdev->dev; 485 sc->devid = id->driver_data; 486 487 ret = hif_get_device_type(id->driver_data, revision_id, 488 &hif_type, &target_type); 489 if (ret < 0) { 490 HIF_ERROR("%s: invalid device ret %d id %d revision_id %d", 491 __func__, ret, (int)id->driver_data, revision_id); 492 return QDF_STATUS_E_FAILURE; 493 } 494 495 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 496 if (!memres) { 497 HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", __func__); 498 return -EIO; 499 } 500 501 ret = dma_set_mask(dev, DMA_BIT_MASK(32)); 502 if (ret) { 503 HIF_INFO("ath: 32-bit DMA not available\n"); 504 goto err_cleanup1; 505 } 506 507 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) 508 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 509 #else 510 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); 511 #endif 512 if (ret) { 513 HIF_ERROR("%s: failed to set dma mask error = %d", 514 __func__, ret); 515 return ret; 516 } 517 518 /* Arrange for access to Target SoC registers. */ 519 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) 520 mem = devm_ioremap_resource(&pdev->dev, memres); 521 #else 522 mem = devm_request_and_ioremap(&pdev->dev, memres); 523 #endif 524 if (IS_ERR(mem)) { 525 HIF_INFO("ath: ioremap error\n"); 526 ret = PTR_ERR(mem); 527 goto err_cleanup1; 528 } 529 530 sc->mem = mem; 531 ol_sc->mem = mem; 532 ol_sc->mem_pa = memres->start; 533 534 tgt_info = hif_get_target_info_handle((struct hif_opaque_softc *)ol_sc); 535 536 tgt_info->target_type = target_type; 537 hif_register_tbl_attach(ol_sc, hif_type); 538 hif_target_register_tbl_attach(ol_sc, target_type); 539 540 /* QCA_WIFI_QCA8074_VP:Should not be executed on 8074 VP platform */ 541 if (tgt_info->target_type != TARGET_TYPE_QCA8074) { 542 if (hif_ahb_enable_radio(sc, pdev, id) != 0) { 543 HIF_INFO("error in enabling soc\n"); 544 return -EIO; 545 } 546 547 if (hif_target_sync_ahb(ol_sc) < 0) { 548 ret = -EIO; 549 goto err_target_sync; 550 } 551 } 552 HIF_TRACE("%s: X - hif_type = 0x%x, target_type = 0x%x", 553 __func__, hif_type, target_type); 554 555 return QDF_STATUS_SUCCESS; 556 err_target_sync: 557 /* QCA_WIFI_QCA8074_VP:Should not be executed on 8074 VP platform */ 558 if (tgt_info->target_type != TARGET_TYPE_QCA8074) { 559 HIF_INFO("Error: Disabling target\n"); 560 hif_ahb_disable_bus(ol_sc); 561 } 562 err_cleanup1: 563 return ret; 564 } 565 566 567 /** 568 * hif_reset_soc() - reset soc 569 * 570 * @hif_ctx: HIF context 571 * 572 * This function resets soc and helds the 573 * target in reset state 574 * 575 * Return: void 576 */ 577 /* Function to reset SoC */ 578 void hif_ahb_reset_soc(struct hif_softc *hif_ctx) 579 { 580 hif_ahb_device_reset(hif_ctx); 581 } 582 583 584 /** 585 * hif_nointrs() - disable IRQ 586 * 587 * @scn: struct hif_softc 588 * 589 * This function stops interrupt(s) 590 * 591 * Return: none 592 */ 593 void hif_ahb_nointrs(struct hif_softc *scn) 594 { 595 int i; 596 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 597 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 598 struct CE_attr *host_ce_conf = hif_state->host_ce_config; 599 600 ce_unregister_irq(hif_state, CE_ALL_BITMAP); 601 602 if (scn->request_irq_done == false) 603 return; 604 605 if (sc->num_msi_intrs > 0) { 606 /* MSI interrupt(s) */ 607 for (i = 0; i < sc->num_msi_intrs; i++) { 608 free_irq(sc->irq + i, sc); 609 } 610 sc->num_msi_intrs = 0; 611 } else { 612 if (!scn->per_ce_irq) { 613 free_irq(sc->irq, sc); 614 } else { 615 for (i = 0; i < scn->ce_count; i++) { 616 if (host_ce_conf[i].flags 617 & CE_ATTR_DISABLE_INTR) 618 continue; 619 620 free_irq(ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i], 621 &hif_state->tasklets[i]); 622 } 623 hif_ahb_deconfigure_grp_irq(scn); 624 } 625 } 626 scn->request_irq_done = false; 627 628 } 629 630 /** 631 * ce_irq_enable() - enable copy engine IRQ 632 * @scn: struct hif_softc 633 * @ce_id: ce_id 634 * 635 * This function enables the interrupt for the radio. 636 * 637 * Return: N/A 638 */ 639 void hif_ahb_irq_enable(struct hif_softc *scn, int ce_id) 640 { 641 uint32_t regval; 642 uint32_t reg_offset = 0; 643 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 644 struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id]; 645 struct hif_target_info *tgt_info = &scn->target_info; 646 647 if (scn->per_ce_irq) { 648 if (target_ce_conf->pipedir & PIPEDIR_OUT) { 649 reg_offset = HOST_IE_ADDRESS; 650 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 651 regval = hif_read32_mb(scn, scn->mem + reg_offset); 652 regval |= HOST_IE_REG1_CE_BIT(ce_id); 653 hif_write32_mb(scn, scn->mem + reg_offset, regval); 654 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 655 } 656 if (target_ce_conf->pipedir & PIPEDIR_IN) { 657 reg_offset = HOST_IE_ADDRESS_2; 658 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 659 regval = hif_read32_mb(scn, scn->mem + reg_offset); 660 regval |= HOST_IE_REG2_CE_BIT(ce_id); 661 hif_write32_mb(scn, scn->mem + reg_offset, regval); 662 if (tgt_info->target_type == TARGET_TYPE_QCA8074) { 663 /* Enable destination ring interrupts for 8074 664 * TODO: To be removed in 2.0 HW */ 665 regval = hif_read32_mb(scn, scn->mem + 666 HOST_IE_ADDRESS_3); 667 regval |= HOST_IE_REG3_CE_BIT(ce_id); 668 } 669 hif_write32_mb(scn, scn->mem + HOST_IE_ADDRESS_3, 670 regval); 671 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 672 } 673 } else { 674 hif_pci_irq_enable(scn, ce_id); 675 } 676 } 677 678 /** 679 * ce_irq_disable() - disable copy engine IRQ 680 * @scn: struct hif_softc 681 * @ce_id: ce_id 682 * 683 * Return: N/A 684 */ 685 void hif_ahb_irq_disable(struct hif_softc *scn, int ce_id) 686 { 687 uint32_t regval; 688 uint32_t reg_offset = 0; 689 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 690 struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id]; 691 struct hif_target_info *tgt_info = &scn->target_info; 692 693 if (scn->per_ce_irq) { 694 if (target_ce_conf->pipedir & PIPEDIR_OUT) { 695 reg_offset = HOST_IE_ADDRESS; 696 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 697 regval = hif_read32_mb(scn, scn->mem + reg_offset); 698 regval &= ~HOST_IE_REG1_CE_BIT(ce_id); 699 hif_write32_mb(scn, scn->mem + reg_offset, regval); 700 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 701 } 702 if (target_ce_conf->pipedir & PIPEDIR_IN) { 703 reg_offset = HOST_IE_ADDRESS_2; 704 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 705 regval = hif_read32_mb(scn, scn->mem + reg_offset); 706 regval &= ~HOST_IE_REG2_CE_BIT(ce_id); 707 hif_write32_mb(scn, scn->mem + reg_offset, regval); 708 if (tgt_info->target_type == TARGET_TYPE_QCA8074) { 709 /* Disable destination ring interrupts for 8074 710 * TODO: To be removed in 2.0 HW */ 711 regval = hif_read32_mb(scn, scn->mem + 712 HOST_IE_ADDRESS_3); 713 regval &= ~HOST_IE_REG3_CE_BIT(ce_id); 714 } 715 hif_write32_mb(scn, scn->mem + HOST_IE_ADDRESS_3, 716 regval); 717 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 718 } 719 } 720 } 721 722 void hif_ahb_exec_grp_irq_disable(struct hif_exec_context *hif_ext_group) 723 { 724 int i; 725 726 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 727 if (hif_ext_group->irq_enabled) { 728 for (i = 0; i < hif_ext_group->numirq; i++) { 729 disable_irq_nosync(hif_ext_group->os_irq[i]); 730 } 731 hif_ext_group->irq_enabled = false; 732 } 733 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 734 } 735 736 void hif_ahb_exec_grp_irq_enable(struct hif_exec_context *hif_ext_group) 737 { 738 int i; 739 740 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 741 if (!hif_ext_group->irq_enabled) { 742 for (i = 0; i < hif_ext_group->numirq; i++) { 743 enable_irq(hif_ext_group->os_irq[i]); 744 } 745 hif_ext_group->irq_enabled = true; 746 } 747 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 748 } 749 750 /** 751 * hif_ahb_needs_bmi() - return true if the soc needs bmi through the driver 752 * @scn: hif context 753 * 754 * Return: true if soc needs driver bmi otherwise false 755 */ 756 bool hif_ahb_needs_bmi(struct hif_softc *scn) 757 { 758 return !ce_srng_based(scn); 759 } 760