1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * DOC: if_ahb.c 22 * 23 * c file for ahb specific implementations. 24 */ 25 26 #include "hif.h" 27 #include "target_type.h" 28 #include "hif_main.h" 29 #include "hif_debug.h" 30 #include "hif_io32.h" 31 #include "ce_main.h" 32 #include "ce_api.h" 33 #include "ce_tasklet.h" 34 #include "if_ahb.h" 35 #include "if_pci.h" 36 #include "ahb_api.h" 37 #include "pci_api.h" 38 #include "hif_napi.h" 39 #include "qal_vbus_dev.h" 40 #include "qdf_irq.h" 41 42 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) 43 #define IRQF_DISABLED 0x00000020 44 #endif 45 46 #define HIF_IC_CE0_IRQ_OFFSET 4 47 #define HIF_IC_MAX_IRQ 58 48 49 static uint16_t ic_irqnum[HIF_IC_MAX_IRQ]; 50 /* integrated chip irq names */ 51 const char *ic_irqname[HIF_IC_MAX_IRQ] = { 52 "misc-pulse1", 53 "misc-latch", 54 "sw-exception", 55 "watchdog", 56 "ce0", 57 "ce1", 58 "ce2", 59 "ce3", 60 "ce4", 61 "ce5", 62 "ce6", 63 "ce7", 64 "ce8", 65 "ce9", 66 "ce10", 67 "ce11", 68 "host2wbm-desc-feed", 69 "host2reo-re-injection", 70 "host2reo-command", 71 "host2rxdma-monitor-ring3", 72 "host2rxdma-monitor-ring2", 73 "host2rxdma-monitor-ring1", 74 "reo2ost-exception", 75 "wbm2host-rx-release", 76 "reo2host-status", 77 "reo2host-destination-ring4", 78 "reo2host-destination-ring3", 79 "reo2host-destination-ring2", 80 "reo2host-destination-ring1", 81 "rxdma2host-monitor-destination-mac3", 82 "rxdma2host-monitor-destination-mac2", 83 "rxdma2host-monitor-destination-mac1", 84 "ppdu-end-interrupts-mac3", 85 "ppdu-end-interrupts-mac2", 86 "ppdu-end-interrupts-mac1", 87 "rxdma2host-monitor-status-ring-mac3", 88 "rxdma2host-monitor-status-ring-mac2", 89 "rxdma2host-monitor-status-ring-mac1", 90 "host2rxdma-host-buf-ring-mac3", 91 "host2rxdma-host-buf-ring-mac2", 92 "host2rxdma-host-buf-ring-mac1", 93 "rxdma2host-destination-ring-mac3", 94 "rxdma2host-destination-ring-mac2", 95 "rxdma2host-destination-ring-mac1", 96 "host2tcl-input-ring4", 97 "host2tcl-input-ring3", 98 "host2tcl-input-ring2", 99 "host2tcl-input-ring1", 100 "wbm2host-tx-completions-ring4", 101 "wbm2host-tx-completions-ring3", 102 "wbm2host-tx-completions-ring2", 103 "wbm2host-tx-completions-ring1", 104 "tcl2host-status-ring", 105 "txmon2host-monitor-destination-mac3", 106 "txmon2host-monitor-destination-mac2", 107 "txmon2host-monitor-destination-mac1", 108 "host2tx-monitor-ring1", 109 "umac_reset" 110 }; 111 112 /** 113 * hif_ahb_get_irq_name() - get irqname 114 * @irq_no: irq number 115 * 116 * This function gives irqnumber to irqname 117 * mapping. 118 * 119 * Return: irq name 120 */ 121 const char *hif_ahb_get_irq_name(int irq_no) 122 { 123 return ic_irqname[irq_no]; 124 } 125 126 /** 127 * hif_ahb_disable_isr() - disable isr 128 * @scn: struct hif_softc 129 * 130 * This function disables isr and kills tasklets 131 * 132 * Return: void 133 */ 134 void hif_ahb_disable_isr(struct hif_softc *scn) 135 { 136 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 137 hif_exec_kill(&scn->osc); 138 hif_nointrs(scn); 139 ce_tasklet_kill(scn); 140 tasklet_kill(&sc->intr_tq); 141 qdf_atomic_set(&scn->active_tasklet_cnt, 0); 142 qdf_atomic_set(&scn->active_grp_tasklet_cnt, 0); 143 } 144 145 /** 146 * hif_ahb_dump_registers() - dump bus debug registers 147 * @hif_ctx: struct hif_opaque_softc 148 * 149 * This function dumps hif bus debug registers 150 * 151 * Return: 0 for success or error code 152 */ 153 int hif_ahb_dump_registers(struct hif_softc *hif_ctx) 154 { 155 int status; 156 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 157 158 status = hif_dump_ce_registers(scn); 159 if (status) 160 hif_err("Dump CE Registers Failed status %d", status); 161 162 return 0; 163 } 164 165 /** 166 * hif_ahb_close() - hif_bus_close 167 * @scn: pointer to the hif context. 168 * 169 * This is a callback function for hif_bus_close. 170 * 171 * 172 * Return: n/a 173 */ 174 void hif_ahb_close(struct hif_softc *scn) 175 { 176 hif_ce_close(scn); 177 } 178 179 /** 180 * hif_ahb_open() - hif_ahb open 181 * @hif_ctx: hif context 182 * @bus_type: bus type 183 * 184 * This is a callback function for hif_bus_open. 185 * 186 * Return: QDF_STATUS 187 */ 188 QDF_STATUS hif_ahb_open(struct hif_softc *hif_ctx, enum qdf_bus_type bus_type) 189 { 190 191 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_ctx); 192 193 qdf_spinlock_create(&sc->irq_lock); 194 return hif_ce_open(hif_ctx); 195 } 196 197 /** 198 * hif_ahb_bus_configure() - Configure the bus 199 * @scn: pointer to the hif context. 200 * 201 * This function configure the ahb bus 202 * 203 * Return: 0 for success. nonzero for failure. 204 */ 205 int hif_ahb_bus_configure(struct hif_softc *scn) 206 { 207 return hif_pci_bus_configure(scn); 208 } 209 210 static void hif_ahb_get_bar_addr_pld(struct hif_pci_softc *sc, 211 struct device *dev) 212 { 213 struct pld_soc_info info; 214 int ret = 0; 215 216 ret = pld_get_soc_info(dev, &info); 217 sc->mem = info.v_addr; 218 sc->ce_sc.ol_sc.mem = info.v_addr; 219 sc->ce_sc.ol_sc.mem_pa = info.p_addr; 220 } 221 222 static void hif_ahb_get_soc_cmem_info_pld(struct hif_pci_softc *sc, 223 struct device *dev) 224 { 225 struct pld_soc_info info; 226 int ret = 0; 227 struct hif_softc *scn = HIF_GET_SOFTC(sc); 228 229 ret = pld_get_soc_info(dev, &info); 230 /* dev_mem_info[0] is for CMEM */ 231 scn->cmem_start = info.dev_mem_info[0].start; 232 scn->cmem_size = info.dev_mem_info[0].size; 233 } 234 235 int hif_ahb_configure_irq_by_ceid(struct hif_softc *scn, int ce_id) 236 { 237 int ret = 0; 238 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 239 struct platform_device *pdev = (struct platform_device *)sc->pdev; 240 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 241 int irq = 0; 242 243 if (ce_id >= CE_COUNT_MAX) 244 return -EINVAL; 245 246 ret = pfrm_get_irq(&pdev->dev, (struct qdf_pfm_hndl *)pdev, 247 ic_irqname[HIF_IC_CE0_IRQ_OFFSET + ce_id], 248 HIF_IC_CE0_IRQ_OFFSET + ce_id, &irq); 249 if (ret) { 250 dev_err(&pdev->dev, "get irq failed\n"); 251 ret = -EFAULT; 252 goto end; 253 } 254 255 ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + ce_id] = irq; 256 ret = pfrm_request_irq(&pdev->dev, irq, 257 hif_ahb_interrupt_handler, 258 IRQF_TRIGGER_RISING, 259 ic_irqname[HIF_IC_CE0_IRQ_OFFSET + ce_id], 260 &hif_state->tasklets[ce_id]); 261 if (ret) { 262 dev_err(&pdev->dev, "ath_request_irq failed\n"); 263 ret = -EFAULT; 264 goto end; 265 } 266 hif_ahb_irq_enable(scn, ce_id); 267 268 end: 269 return ret; 270 } 271 272 int hif_ahb_configure_irq(struct hif_pci_softc *sc) 273 { 274 int ret = 0; 275 struct hif_softc *scn = HIF_GET_SOFTC(sc); 276 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 277 struct CE_attr *host_ce_conf = hif_state->host_ce_config; 278 int i; 279 280 /* configure per CE interrupts */ 281 for (i = 0; i < scn->ce_count; i++) { 282 if (host_ce_conf[i].flags & CE_ATTR_DISABLE_INTR) 283 continue; 284 285 if (host_ce_conf[i].flags & CE_ATTR_INIT_ON_DEMAND) 286 continue; 287 288 ret = hif_ahb_configure_irq_by_ceid(scn, i); 289 if (ret) 290 goto end; 291 } 292 293 end: 294 return ret; 295 } 296 297 int hif_ahb_configure_grp_irq(struct hif_softc *scn, 298 struct hif_exec_context *hif_ext_group) 299 { 300 int ret = 0; 301 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 302 struct platform_device *pdev = (struct platform_device *)sc->pdev; 303 int irq = 0; 304 int j; 305 306 /* configure external interrupts */ 307 hif_ext_group->irq_enable = &hif_ahb_exec_grp_irq_enable; 308 hif_ext_group->irq_disable = &hif_ahb_exec_grp_irq_disable; 309 hif_ext_group->irq_name = &hif_ahb_get_irq_name; 310 hif_ext_group->work_complete = &hif_dummy_grp_done; 311 312 for (j = 0; j < hif_ext_group->numirq; j++) { 313 ret = pfrm_get_irq(&pdev->dev, (struct qdf_pfm_hndl *)pdev, 314 ic_irqname[hif_ext_group->irq[j]], 315 hif_ext_group->irq[j], &irq); 316 if (ret) { 317 dev_err(&pdev->dev, "get irq failed\n"); 318 ret = -EFAULT; 319 goto end; 320 } 321 ic_irqnum[hif_ext_group->irq[j]] = irq; 322 hif_ext_group->os_irq[j] = irq; 323 } 324 325 for (j = 0; j < hif_ext_group->numirq; j++) { 326 irq = hif_ext_group->os_irq[j]; 327 328 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 329 qdf_dev_set_irq_status_flags(irq, QDF_IRQ_DISABLE_UNLAZY); 330 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 331 332 ret = pfrm_request_irq(scn->qdf_dev->dev, 333 irq, hif_ext_group_interrupt_handler, 334 IRQF_TRIGGER_RISING | IRQF_SHARED, 335 ic_irqname[hif_ext_group->irq[j]], 336 hif_ext_group); 337 if (ret) { 338 dev_err(&pdev->dev, "ath_request_irq failed\n"); 339 ret = -EFAULT; 340 goto end; 341 } 342 } 343 344 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 345 hif_ext_group->irq_requested = true; 346 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 347 end: 348 return ret; 349 } 350 351 void hif_ahb_deconfigure_grp_irq(struct hif_softc *scn) 352 { 353 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 354 struct hif_exec_context *hif_ext_group; 355 int i, j; 356 int irq = 0; 357 358 /* configure external interrupts */ 359 for (i = 0; i < hif_state->hif_num_extgroup; i++) { 360 hif_ext_group = hif_state->hif_ext_group[i]; 361 if (hif_ext_group->irq_requested == true) { 362 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 363 hif_ext_group->irq_requested = false; 364 for (j = 0; j < hif_ext_group->numirq; j++) { 365 irq = hif_ext_group->os_irq[j]; 366 hif_ext_group->irq_enabled = false; 367 qdf_dev_clear_irq_status_flags( 368 irq, 369 QDF_IRQ_DISABLE_UNLAZY); 370 } 371 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 372 373 /* Avoid holding the irq_lock while freeing the irq 374 * as the same lock is being held by the irq handler 375 * while disabling the irq. This causes a deadlock 376 * between free_irq and irq_handler. 377 */ 378 for (j = 0; j < hif_ext_group->numirq; j++) { 379 irq = hif_ext_group->os_irq[j]; 380 pfrm_free_irq(scn->qdf_dev->dev, 381 irq, hif_ext_group); 382 } 383 } 384 } 385 } 386 387 irqreturn_t hif_ahb_interrupt_handler(int irq, void *context) 388 { 389 struct ce_tasklet_entry *tasklet_entry = context; 390 return ce_dispatch_interrupt(tasklet_entry->ce_id, tasklet_entry); 391 } 392 393 /** 394 * hif_ahb_disable_bus() - Disable the bus 395 * @scn : pointer to the hif context 396 * 397 * This function disables the bus and helds the target in reset state 398 * 399 * Return: none 400 */ 401 void hif_ahb_disable_bus(struct hif_softc *scn) 402 { 403 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 404 void __iomem *mem; 405 struct platform_device *pdev = (struct platform_device *)sc->pdev; 406 struct resource *memres = NULL; 407 int mem_pa_size = 0; 408 struct hif_target_info *tgt_info = NULL; 409 struct qdf_vbus_resource *vmres = NULL; 410 QDF_STATUS status; 411 412 tgt_info = &scn->target_info; 413 /*Disable WIFI clock input*/ 414 if (sc->mem) { 415 status = pfrm_platform_get_resource( 416 scn->qdf_dev->dev, 417 (struct qdf_pfm_hndl *)pdev, &vmres, 418 IORESOURCE_MEM, 0); 419 if (QDF_IS_STATUS_ERROR(status)) { 420 hif_info("Failed to get IORESOURCE_MEM"); 421 return; 422 } 423 memres = (struct resource *)vmres; 424 if (memres) 425 mem_pa_size = memres->end - memres->start + 1; 426 427 if (tgt_info->target_type == TARGET_TYPE_QCA5018 || 428 tgt_info->target_type == TARGET_TYPE_QCA5332) { 429 iounmap(sc->mem_ce); 430 sc->mem_ce = NULL; 431 scn->mem_ce = NULL; 432 } 433 if (sc->mem_pmm_base) { 434 iounmap(sc->mem_pmm_base); 435 sc->mem_pmm_base = NULL; 436 scn->mem_pmm_base = NULL; 437 } 438 if (sc->mem_cmem) { 439 iounmap(sc->mem_cmem); 440 sc->mem_cmem = NULL; 441 scn->mem_cmem = NULL; 442 } 443 mem = (void __iomem *)sc->mem; 444 if (mem) { 445 pfrm_devm_iounmap(&pdev->dev, mem); 446 pfrm_devm_release_mem_region(&pdev->dev, scn->mem_pa, 447 mem_pa_size); 448 sc->mem = NULL; 449 pld_set_bar_addr(&pdev->dev, NULL); 450 } 451 } 452 scn->mem = NULL; 453 } 454 455 /** 456 * hif_ahb_enable_bus() - Enable the bus 457 * @ol_sc: HIF context 458 * @dev: dev 459 * @bdev: bus dev 460 * @bid: bus id 461 * @type: bus type 462 * 463 * This function enables the radio bus by enabling necessary 464 * clocks and waits for the target to get ready to proceed further 465 * 466 * Return: QDF_STATUS 467 */ 468 QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc, 469 struct device *dev, void *bdev, 470 const struct hif_bus_id *bid, 471 enum hif_enable_type type) 472 { 473 int ret = 0; 474 int hif_type; 475 int target_type; 476 const struct platform_device_id *id = (struct platform_device_id *)bid; 477 struct platform_device *pdev = bdev; 478 struct hif_target_info *tgt_info = NULL; 479 struct resource *memres = NULL; 480 void __iomem *mem = NULL; 481 uint32_t revision_id = 0; 482 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(ol_sc); 483 QDF_STATUS status; 484 struct qdf_vbus_resource *vmres = NULL; 485 486 sc->pdev = (struct pci_dev *)pdev; 487 sc->dev = &pdev->dev; 488 sc->devid = id->driver_data; 489 490 ret = hif_get_device_type(id->driver_data, revision_id, 491 &hif_type, &target_type); 492 if (ret < 0) { 493 hif_err("Invalid device ret %d id %d revision_id %d", 494 ret, (int)id->driver_data, revision_id); 495 return QDF_STATUS_E_FAILURE; 496 } 497 498 if (target_type == TARGET_TYPE_QCN6122 || 499 target_type == TARGET_TYPE_QCN9160) { 500 hif_ahb_get_bar_addr_pld(sc, dev); 501 } 502 503 /* 11BE SoC chipsets Need to call this function to get cmem addr */ 504 if (target_type == TARGET_TYPE_QCA5332) 505 hif_ahb_get_soc_cmem_info_pld(sc, dev); 506 507 if (target_type == TARGET_TYPE_QCN6122 || 508 target_type == TARGET_TYPE_QCN9160) { 509 hif_update_irq_ops_with_pci(ol_sc); 510 } else { 511 status = pfrm_platform_get_resource(&pdev->dev, 512 (struct qdf_pfm_hndl *)pdev, 513 &vmres, 514 IORESOURCE_MEM, 0); 515 if (QDF_IS_STATUS_ERROR(status)) { 516 hif_err("Failed to get IORESOURCE_MEM"); 517 return status; 518 } 519 memres = (struct resource *)vmres; 520 if (!memres) { 521 hif_err("Failed to get IORESOURCE_MEM"); 522 return QDF_STATUS_E_IO; 523 } 524 525 /* Arrange for access to Target SoC registers. */ 526 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) 527 status = pfrm_devm_ioremap_resource( 528 dev, 529 (struct qdf_vbus_resource *)memres, 530 &mem); 531 #else 532 status = pfrm_devm_request_and_ioremap( 533 dev, 534 (struct qdf_vbus_resource *)memres, 535 &mem); 536 #endif 537 if (QDF_IS_STATUS_ERROR(status)) { 538 hif_err("ath: ioremap error"); 539 ret = PTR_ERR(mem); 540 goto err_cleanup1; 541 } 542 543 sc->mem = mem; 544 pld_set_bar_addr(dev, mem); 545 ol_sc->mem = mem; 546 ol_sc->mem_pa = memres->start; 547 } 548 549 ret = pfrm_dma_set_mask(dev, 32); 550 if (ret) { 551 hif_err("ath: 32-bit DMA not available"); 552 status = QDF_STATUS_E_IO; 553 goto err_cleanup1; 554 } 555 556 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) 557 ret = pfrm_dma_set_mask_and_coherent(dev, 32); 558 #else 559 ret = pfrm_dma_set_coherent_mask(dev, 32); 560 #endif 561 if (ret) { 562 hif_err("Failed to set dma mask error = %d", ret); 563 return QDF_STATUS_E_IO; 564 } 565 566 tgt_info = hif_get_target_info_handle((struct hif_opaque_softc *)ol_sc); 567 568 tgt_info->target_type = target_type; 569 hif_register_tbl_attach(ol_sc, hif_type); 570 hif_target_register_tbl_attach(ol_sc, target_type); 571 /* 572 * In QCA5018 CE region moved to SOC outside WCSS block. 573 * Allocate separate I/O remap to access CE registers. 574 */ 575 if (tgt_info->target_type == TARGET_TYPE_QCA5018 || 576 tgt_info->target_type == TARGET_TYPE_QCA5332) { 577 struct hif_softc *scn = HIF_GET_SOFTC(sc); 578 579 sc->mem_ce = qdf_ioremap(HOST_CE_ADDRESS, HOST_CE_SIZE); 580 if (IS_ERR(sc->mem_ce)) { 581 hif_err("CE: ioremap failed"); 582 return QDF_STATUS_E_IO; 583 } 584 ol_sc->mem_ce = sc->mem_ce; 585 } 586 587 if (tgt_info->target_type == TARGET_TYPE_QCA5332) { 588 struct hif_softc *scn = HIF_GET_SOFTC(sc); 589 590 /* 591 * In QCA5332 CMEM region is outside WCSS block. 592 * Allocate separate I/O remap to access CMEM address. 593 */ 594 sc->mem_cmem = qdf_ioremap(HOST_CMEM_ADDRESS, HOST_CMEM_SIZE); 595 if (IS_ERR(sc->mem_cmem)) { 596 hif_err("CE: ioremap failed"); 597 return QDF_STATUS_E_IO; 598 } 599 ol_sc->mem_cmem = sc->mem_cmem; 600 601 /* 602 * PMM SCRATCH Register for QCA5332 603 */ 604 sc->mem_pmm_base = qdf_ioremap(PMM_SCRATCH_BASE, 605 PMM_SCRATCH_SIZE); 606 if (IS_ERR(sc->mem_pmm_base)) { 607 hif_err("CE: ioremap failed"); 608 return QDF_STATUS_E_IO; 609 } 610 ol_sc->mem_pmm_base = sc->mem_pmm_base; 611 } 612 613 hif_info("X - hif_type = 0x%x, target_type = 0x%x", 614 hif_type, target_type); 615 616 return QDF_STATUS_SUCCESS; 617 err_cleanup1: 618 return status; 619 } 620 621 /** 622 * hif_ahb_nointrs() - disable IRQ 623 * 624 * @scn: struct hif_softc 625 * 626 * This function stops interrupt(s) 627 * 628 * Return: none 629 */ 630 void hif_ahb_nointrs(struct hif_softc *scn) 631 { 632 int i; 633 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 634 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 635 struct CE_attr *host_ce_conf = hif_state->host_ce_config; 636 637 scn->free_irq_done = true; 638 ce_unregister_irq(hif_state, CE_ALL_BITMAP); 639 640 if (scn->request_irq_done == false) 641 return; 642 643 if (sc->num_msi_intrs > 0) { 644 /* MSI interrupt(s) */ 645 for (i = 0; i < sc->num_msi_intrs; i++) { 646 pfrm_free_irq(scn->qdf_dev->dev, sc->irq + i, sc); 647 } 648 sc->num_msi_intrs = 0; 649 } else { 650 if (!scn->per_ce_irq) { 651 pfrm_free_irq(scn->qdf_dev->dev, sc->irq, sc); 652 } else { 653 for (i = 0; i < scn->ce_count; i++) { 654 if (host_ce_conf[i].flags 655 & CE_ATTR_DISABLE_INTR) 656 continue; 657 if (!hif_state->tasklets[i].inited) 658 continue; 659 pfrm_free_irq( 660 scn->qdf_dev->dev, 661 ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i], 662 &hif_state->tasklets[i]); 663 } 664 hif_ahb_deconfigure_grp_irq(scn); 665 } 666 } 667 scn->request_irq_done = false; 668 669 } 670 671 /** 672 * hif_ahb_irq_enable() - enable copy engine IRQ 673 * @scn: struct hif_softc 674 * @ce_id: ce_id 675 * 676 * This function enables the interrupt for the radio. 677 * 678 * Return: N/A 679 */ 680 void hif_ahb_irq_enable(struct hif_softc *scn, int ce_id) 681 { 682 uint32_t regval; 683 uint32_t reg_offset = 0; 684 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 685 struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id]; 686 struct hif_target_info *tgt_info = &scn->target_info; 687 void *mem = scn->mem_ce ? scn->mem_ce : scn->mem; 688 689 if (scn->per_ce_irq) { 690 if (target_ce_conf->pipedir & PIPEDIR_OUT) { 691 reg_offset = HOST_IE_ADDRESS; 692 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 693 regval = hif_read32_mb(scn, mem + reg_offset); 694 regval |= HOST_IE_REG1_CE_BIT(ce_id); 695 hif_write32_mb(scn, mem + reg_offset, regval); 696 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 697 } 698 if (target_ce_conf->pipedir & PIPEDIR_IN) { 699 reg_offset = HOST_IE_ADDRESS_2; 700 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 701 regval = hif_read32_mb(scn, mem + reg_offset); 702 regval |= HOST_IE_REG2_CE_BIT(ce_id); 703 hif_write32_mb(scn, mem + reg_offset, regval); 704 if (tgt_info->target_type == TARGET_TYPE_QCA8074 || 705 tgt_info->target_type == TARGET_TYPE_QCA8074V2 || 706 tgt_info->target_type == TARGET_TYPE_QCA9574 || 707 tgt_info->target_type == TARGET_TYPE_QCA5332 || 708 tgt_info->target_type == TARGET_TYPE_QCA5018 || 709 tgt_info->target_type == TARGET_TYPE_QCA6018) { 710 /* Enable destination ring interrupts for 711 * 8074, 8074V2, 6018 and 50xx 712 */ 713 regval = hif_read32_mb(scn, mem + 714 HOST_IE_ADDRESS_3); 715 regval |= HOST_IE_REG3_CE_BIT(ce_id); 716 717 hif_write32_mb(scn, mem + 718 HOST_IE_ADDRESS_3, regval); 719 } 720 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 721 } 722 } else { 723 hif_pci_irq_enable(scn, ce_id); 724 } 725 } 726 727 /** 728 * hif_ahb_irq_disable() - disable copy engine IRQ 729 * @scn: struct hif_softc 730 * @ce_id: ce_id 731 * 732 * Return: N/A 733 */ 734 void hif_ahb_irq_disable(struct hif_softc *scn, int ce_id) 735 { 736 uint32_t regval; 737 uint32_t reg_offset = 0; 738 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 739 struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id]; 740 struct hif_target_info *tgt_info = &scn->target_info; 741 void *mem = scn->mem_ce ? scn->mem_ce : scn->mem; 742 743 if (scn->per_ce_irq) { 744 if (target_ce_conf->pipedir & PIPEDIR_OUT) { 745 reg_offset = HOST_IE_ADDRESS; 746 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 747 regval = hif_read32_mb(scn, mem + reg_offset); 748 regval &= ~HOST_IE_REG1_CE_BIT(ce_id); 749 hif_write32_mb(scn, mem + reg_offset, regval); 750 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 751 } 752 if (target_ce_conf->pipedir & PIPEDIR_IN) { 753 reg_offset = HOST_IE_ADDRESS_2; 754 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 755 regval = hif_read32_mb(scn, mem + reg_offset); 756 regval &= ~HOST_IE_REG2_CE_BIT(ce_id); 757 hif_write32_mb(scn, mem + reg_offset, regval); 758 if (tgt_info->target_type == TARGET_TYPE_QCA8074 || 759 tgt_info->target_type == TARGET_TYPE_QCA8074V2 || 760 tgt_info->target_type == TARGET_TYPE_QCA9574 || 761 tgt_info->target_type == TARGET_TYPE_QCA5332 || 762 tgt_info->target_type == TARGET_TYPE_QCA5018 || 763 tgt_info->target_type == TARGET_TYPE_QCA6018) { 764 /* Disable destination ring interrupts for 765 * 8074, 8074V2, 6018 and 50xx 766 */ 767 regval = hif_read32_mb(scn, mem + 768 HOST_IE_ADDRESS_3); 769 regval &= ~HOST_IE_REG3_CE_BIT(ce_id); 770 771 hif_write32_mb(scn, mem + 772 HOST_IE_ADDRESS_3, regval); 773 } 774 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 775 } 776 } 777 } 778 779 void hif_ahb_exec_grp_irq_disable(struct hif_exec_context *hif_ext_group) 780 { 781 int i; 782 783 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 784 if (hif_ext_group->irq_enabled) { 785 for (i = 0; i < hif_ext_group->numirq; i++) { 786 disable_irq_nosync(hif_ext_group->os_irq[i]); 787 } 788 hif_ext_group->irq_enabled = false; 789 } 790 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 791 } 792 793 void hif_ahb_exec_grp_irq_enable(struct hif_exec_context *hif_ext_group) 794 { 795 int i; 796 797 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 798 if (hif_ext_group->irq_requested && !hif_ext_group->irq_enabled) { 799 for (i = 0; i < hif_ext_group->numirq; i++) { 800 enable_irq(hif_ext_group->os_irq[i]); 801 } 802 hif_ext_group->irq_enabled = true; 803 } 804 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 805 } 806 807 /** 808 * hif_ahb_needs_bmi() - return true if the soc needs bmi through the driver 809 * @scn: hif context 810 * 811 * Return: true if soc needs driver bmi otherwise false 812 */ 813 bool hif_ahb_needs_bmi(struct hif_softc *scn) 814 { 815 return !ce_srng_based(scn); 816 } 817 818 /** 819 * hif_display_ahb_irq_regs() - prints the host interrupt enable (IE) regs 820 * @scn: hif context 821 * 822 * Return: None 823 */ 824 825 void hif_display_ahb_irq_regs(struct hif_softc *scn) 826 { 827 uint32_t regval; 828 void *mem = scn->mem_ce ? scn->mem_ce : scn->mem; 829 struct hif_target_info *tgt_info = &scn->target_info; 830 831 if (tgt_info->target_type == TARGET_TYPE_QCN6122 || 832 tgt_info->target_type == TARGET_TYPE_QCN9160) { 833 return; 834 } 835 if (scn->per_ce_irq) { 836 regval = hif_read32_mb(scn, mem + HOST_IE_ADDRESS); 837 hif_nofl_err("IRQ enable register value 0x%08x", regval); 838 839 regval = hif_read32_mb(scn, mem + HOST_IE_ADDRESS_2); 840 hif_nofl_err("IRQ enable register 2 value 0x%08x", regval); 841 842 if (tgt_info->target_type == TARGET_TYPE_QCA8074 || 843 tgt_info->target_type == TARGET_TYPE_QCA8074V2 || 844 tgt_info->target_type == TARGET_TYPE_QCA9574 || 845 tgt_info->target_type == TARGET_TYPE_QCA5332 || 846 tgt_info->target_type == TARGET_TYPE_QCA5018 || 847 tgt_info->target_type == TARGET_TYPE_QCA6018) { 848 regval = hif_read32_mb(scn, mem + 849 HOST_IE_ADDRESS_3); 850 hif_nofl_err("IRQ enable register 3 value 0x%08x", 851 regval); 852 } 853 } 854 } 855 856 void hif_ahb_display_stats(struct hif_softc *scn) 857 { 858 if (!scn) { 859 hif_err("hif_scn null"); 860 return; 861 } 862 hif_display_ahb_irq_regs(scn); 863 hif_display_ce_stats(scn); 864 } 865 866 void hif_ahb_clear_stats(struct hif_softc *scn) 867 { 868 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 869 870 if (!hif_state) { 871 hif_err("hif_state null"); 872 return; 873 } 874 hif_clear_ce_stats(hif_state); 875 } 876