1 /* 2 * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /** 20 * DOC: if_ahb.c 21 * 22 * c file for ahb specific implementations. 23 */ 24 25 #include "hif.h" 26 #include "target_type.h" 27 #include "hif_main.h" 28 #include "hif_debug.h" 29 #include "hif_io32.h" 30 #include "ce_main.h" 31 #include "ce_api.h" 32 #include "ce_tasklet.h" 33 #include "if_ahb.h" 34 #include "if_pci.h" 35 #include "ahb_api.h" 36 #include "pci_api.h" 37 #include "hif_napi.h" 38 39 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) 40 #define IRQF_DISABLED 0x00000020 41 #endif 42 43 #define HIF_IC_CE0_IRQ_OFFSET 4 44 #define HIF_IC_MAX_IRQ 54 45 46 static uint8_t ic_irqnum[HIF_IC_MAX_IRQ]; 47 /* integrated chip irq names */ 48 const char *ic_irqname[HIF_IC_MAX_IRQ] = { 49 "misc-pulse1", 50 "misc-latch", 51 "sw-exception", 52 "watchdog", 53 "ce0", 54 "ce1", 55 "ce2", 56 "ce3", 57 "ce4", 58 "ce5", 59 "ce6", 60 "ce7", 61 "ce8", 62 "ce9", 63 "ce10", 64 "ce11", 65 "ce12", 66 "ce13", 67 "host2wbm-desc-feed", 68 "host2reo-re-injection", 69 "host2reo-command", 70 "host2rxdma-monitor-ring3", 71 "host2rxdma-monitor-ring2", 72 "host2rxdma-monitor-ring1", 73 "reo2ost-exception", 74 "wbm2host-rx-release", 75 "reo2host-status", 76 "reo2host-destination-ring4", 77 "reo2host-destination-ring3", 78 "reo2host-destination-ring2", 79 "reo2host-destination-ring1", 80 "rxdma2host-monitor-destination-mac3", 81 "rxdma2host-monitor-destination-mac2", 82 "rxdma2host-monitor-destination-mac1", 83 "ppdu-end-interrupts-mac3", 84 "ppdu-end-interrupts-mac2", 85 "ppdu-end-interrupts-mac1", 86 "rxdma2host-monitor-status-ring-mac3", 87 "rxdma2host-monitor-status-ring-mac2", 88 "rxdma2host-monitor-status-ring-mac1", 89 "host2rxdma-host-buf-ring-mac3", 90 "host2rxdma-host-buf-ring-mac2", 91 "host2rxdma-host-buf-ring-mac1", 92 "rxdma2host-destination-ring-mac3", 93 "rxdma2host-destination-ring-mac2", 94 "rxdma2host-destination-ring-mac1", 95 "host2tcl-input-ring4", 96 "host2tcl-input-ring3", 97 "host2tcl-input-ring2", 98 "host2tcl-input-ring1", 99 "wbm2host-tx-completions-ring3", 100 "wbm2host-tx-completions-ring2", 101 "wbm2host-tx-completions-ring1", 102 "tcl2host-status-ring", 103 }; 104 105 /** 106 * hif_disable_isr() - disable isr 107 * 108 * This function disables isr and kills tasklets 109 * 110 * @hif_ctx: struct hif_softc 111 * 112 * Return: void 113 */ 114 void hif_ahb_disable_isr(struct hif_softc *scn) 115 { 116 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 117 118 hif_exec_kill(&scn->osc); 119 hif_nointrs(scn); 120 ce_tasklet_kill(scn); 121 tasklet_kill(&sc->intr_tq); 122 qdf_atomic_set(&scn->active_tasklet_cnt, 0); 123 qdf_atomic_set(&scn->active_grp_tasklet_cnt, 0); 124 } 125 126 /** 127 * hif_dump_registers() - dump bus debug registers 128 * @scn: struct hif_opaque_softc 129 * 130 * This function dumps hif bus debug registers 131 * 132 * Return: 0 for success or error code 133 */ 134 int hif_ahb_dump_registers(struct hif_softc *hif_ctx) 135 { 136 int status; 137 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 138 139 status = hif_dump_ce_registers(scn); 140 if (status) 141 HIF_ERROR("%s: Dump CE Registers Failed status %d", __func__, 142 status); 143 144 return 0; 145 } 146 147 /** 148 * hif_ahb_close() - hif_bus_close 149 * @scn: pointer to the hif context. 150 * 151 * This is a callback function for hif_bus_close. 152 * 153 * 154 * Return: n/a 155 */ 156 void hif_ahb_close(struct hif_softc *scn) 157 { 158 hif_ce_close(scn); 159 } 160 161 /** 162 * hif_bus_open() - hif_ahb open 163 * @hif_ctx: hif context 164 * @bus_type: bus type 165 * 166 * This is a callback function for hif_bus_open. 167 * 168 * Return: n/a 169 */ 170 QDF_STATUS hif_ahb_open(struct hif_softc *hif_ctx, enum qdf_bus_type bus_type) 171 { 172 173 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_ctx); 174 175 qdf_spinlock_create(&sc->irq_lock); 176 return hif_ce_open(hif_ctx); 177 } 178 179 /** 180 * hif_bus_configure() - Configure the bus 181 * @scn: pointer to the hif context. 182 * 183 * This function configure the ahb bus 184 * 185 * return: 0 for success. nonzero for failure. 186 */ 187 int hif_ahb_bus_configure(struct hif_softc *scn) 188 { 189 return hif_pci_bus_configure(scn); 190 } 191 192 /** 193 * hif_configure_msi_ahb - Configure MSI interrupts 194 * @sc : pointer to the hif context 195 * 196 * return: 0 for success. nonzero for failure. 197 */ 198 199 int hif_configure_msi_ahb(struct hif_pci_softc *sc) 200 { 201 return 0; 202 } 203 204 /** 205 * hif_ahb_configure_legacy_irq() - Configure Legacy IRQ 206 * @sc: pointer to the hif context. 207 * 208 * This function registers the irq handler and enables legacy interrupts 209 * 210 * return: 0 for success. nonzero for failure. 211 */ 212 int hif_ahb_configure_legacy_irq(struct hif_pci_softc *sc) 213 { 214 int ret = 0; 215 struct hif_softc *scn = HIF_GET_SOFTC(sc); 216 struct platform_device *pdev = (struct platform_device *)sc->pdev; 217 int irq = 0; 218 219 /* do not support MSI or MSI IRQ failed */ 220 tasklet_init(&sc->intr_tq, wlan_tasklet, (unsigned long)sc); 221 irq = platform_get_irq_byname(pdev, "legacy"); 222 if (irq < 0) { 223 dev_err(&pdev->dev, "Unable to get irq\n"); 224 ret = -1; 225 goto end; 226 } 227 ret = request_irq(irq, hif_pci_legacy_ce_interrupt_handler, 228 IRQF_DISABLED, "wlan_ahb", sc); 229 if (ret) { 230 dev_err(&pdev->dev, "ath_request_irq failed\n"); 231 ret = -1; 232 goto end; 233 } 234 sc->irq = irq; 235 236 /* Use Legacy PCI Interrupts */ 237 hif_write32_mb(sc->mem+(SOC_CORE_BASE_ADDRESS | 238 PCIE_INTR_ENABLE_ADDRESS), 239 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 240 /* read once to flush */ 241 hif_read32_mb(sc->mem+(SOC_CORE_BASE_ADDRESS | 242 PCIE_INTR_ENABLE_ADDRESS) 243 ); 244 245 end: 246 return ret; 247 } 248 249 int hif_ahb_configure_irq(struct hif_pci_softc *sc) 250 { 251 int ret = 0; 252 struct hif_softc *scn = HIF_GET_SOFTC(sc); 253 struct platform_device *pdev = (struct platform_device *)sc->pdev; 254 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 255 struct CE_attr *host_ce_conf = hif_state->host_ce_config; 256 int irq = 0; 257 int i; 258 259 /* configure per CE interrupts */ 260 for (i = 0; i < scn->ce_count; i++) { 261 if (host_ce_conf[i].flags & CE_ATTR_DISABLE_INTR) 262 continue; 263 irq = platform_get_irq_byname(pdev, ic_irqname[HIF_IC_CE0_IRQ_OFFSET + i]); 264 ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i] = irq; 265 ret = request_irq(irq , 266 hif_ahb_interrupt_handler, 267 IRQF_TRIGGER_RISING, ic_irqname[HIF_IC_CE0_IRQ_OFFSET + i], 268 &hif_state->tasklets[i]); 269 if (ret) { 270 dev_err(&pdev->dev, "ath_request_irq failed\n"); 271 ret = -1; 272 goto end; 273 } 274 hif_ahb_irq_enable(scn, i); 275 } 276 277 end: 278 return ret; 279 } 280 281 int hif_ahb_configure_grp_irq(struct hif_softc *scn, 282 struct hif_exec_context *hif_ext_group) 283 { 284 int ret = 0; 285 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 286 struct platform_device *pdev = (struct platform_device *)sc->pdev; 287 int irq = 0; 288 const char *irq_name; 289 int j; 290 291 /* configure external interrupts */ 292 hif_ext_group->irq_enable = &hif_ahb_exec_grp_irq_enable; 293 hif_ext_group->irq_disable = &hif_ahb_exec_grp_irq_disable; 294 hif_ext_group->work_complete = &hif_dummy_grp_done; 295 296 hif_ext_group->irq_requested = true; 297 298 for (j = 0; j < hif_ext_group->numirq; j++) { 299 irq_name = ic_irqname[hif_ext_group->irq[j]]; 300 irq = platform_get_irq_byname(pdev, irq_name); 301 302 ic_irqnum[hif_ext_group->irq[j]] = irq; 303 ret = request_irq(irq, hif_ext_group_interrupt_handler, 304 IRQF_TRIGGER_RISING, 305 ic_irqname[hif_ext_group->irq[j]], 306 hif_ext_group); 307 if (ret) { 308 dev_err(&pdev->dev, 309 "ath_request_irq failed\n"); 310 ret = -1; 311 goto end; 312 } 313 hif_ext_group->os_irq[j] = irq; 314 } 315 316 end: 317 return ret; 318 } 319 320 void hif_ahb_deconfigure_grp_irq(struct hif_softc *scn) 321 { 322 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 323 struct hif_exec_context *hif_ext_group; 324 int i, j; 325 326 /* configure external interrupts */ 327 for (i = 0; i < hif_state->hif_num_extgroup; i++) { 328 hif_ext_group = hif_state->hif_ext_group[i]; 329 if (hif_ext_group->irq_requested == true) { 330 hif_ext_group->irq_requested = false; 331 for (j = 0; j < hif_ext_group->numirq; j++) { 332 free_irq(hif_ext_group->os_irq[j], 333 hif_ext_group); 334 } 335 } 336 } 337 } 338 339 irqreturn_t hif_ahb_interrupt_handler(int irq, void *context) 340 { 341 struct ce_tasklet_entry *tasklet_entry = context; 342 return ce_dispatch_interrupt(tasklet_entry->ce_id, tasklet_entry); 343 } 344 345 /** 346 * hif_target_sync() : ensure the target is ready 347 * @scn: hif control structure 348 * 349 * Informs fw that we plan to use legacy interupts so that 350 * it can begin booting. Ensures that the fw finishes booting 351 * before continuing. Should be called before trying to write 352 * to the targets other registers for the first time. 353 * 354 * Return: none 355 */ 356 int hif_target_sync_ahb(struct hif_softc *scn) 357 { 358 hif_write32_mb(scn->mem + FW_INDICATOR_ADDRESS, FW_IND_HOST_READY); 359 if (HAS_FW_INDICATOR) { 360 int wait_limit = 500; 361 int fw_ind = 0; 362 363 while (1) { 364 fw_ind = hif_read32_mb(scn->mem + 365 FW_INDICATOR_ADDRESS); 366 if (fw_ind & FW_IND_INITIALIZED) 367 break; 368 if (wait_limit-- < 0) 369 break; 370 hif_write32_mb(scn->mem+(SOC_CORE_BASE_ADDRESS | 371 PCIE_INTR_ENABLE_ADDRESS), 372 PCIE_INTR_FIRMWARE_MASK); 373 qdf_mdelay(10); 374 } 375 if (wait_limit < 0) { 376 HIF_TRACE("%s: FW signal timed out", __func__); 377 return -EIO; 378 } 379 HIF_TRACE("%s: Got FW signal, retries = %x", __func__, 380 500-wait_limit); 381 } 382 383 return 0; 384 } 385 386 /** 387 * hif_disable_bus() - Disable the bus 388 * @scn : pointer to the hif context 389 * 390 * This function disables the bus and helds the target in reset state 391 * 392 * Return: none 393 */ 394 void hif_ahb_disable_bus(struct hif_softc *scn) 395 { 396 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 397 void __iomem *mem; 398 struct platform_device *pdev = (struct platform_device *)sc->pdev; 399 struct resource *memres = NULL; 400 int mem_pa_size = 0; 401 struct hif_target_info *tgt_info = NULL; 402 403 tgt_info = &scn->target_info; 404 /*Disable WIFI clock input*/ 405 if (sc->mem) { 406 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 407 if (!memres) { 408 HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", 409 __func__); 410 return; 411 } 412 mem_pa_size = memres->end - memres->start + 1; 413 414 /* Should not be executed on 8074 platform */ 415 if (tgt_info->target_type != TARGET_TYPE_QCA8074) { 416 hif_ahb_clk_enable_disable(&pdev->dev, 0); 417 418 hif_ahb_device_reset(scn); 419 } 420 mem = (void __iomem *)sc->mem; 421 if (mem) { 422 devm_iounmap(&pdev->dev, mem); 423 devm_release_mem_region(&pdev->dev, scn->mem_pa, 424 mem_pa_size); 425 sc->mem = NULL; 426 } 427 } 428 scn->mem = NULL; 429 } 430 431 /** 432 * hif_enable_bus() - Enable the bus 433 * @dev: dev 434 * @bdev: bus dev 435 * @bid: bus id 436 * @type: bus type 437 * 438 * This function enables the radio bus by enabling necessary 439 * clocks and waits for the target to get ready to proceed futher 440 * 441 * Return: QDF_STATUS 442 */ 443 QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc, 444 struct device *dev, void *bdev, 445 const struct hif_bus_id *bid, 446 enum hif_enable_type type) 447 { 448 int ret = 0; 449 int hif_type; 450 int target_type; 451 const struct platform_device_id *id = (struct platform_device_id *)bid; 452 struct platform_device *pdev = bdev; 453 struct hif_target_info *tgt_info = NULL; 454 struct resource *memres = NULL; 455 void __iomem *mem = NULL; 456 uint32_t revision_id = 0; 457 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(ol_sc); 458 459 sc->pdev = (struct pci_dev *)pdev; 460 sc->dev = &pdev->dev; 461 sc->devid = id->driver_data; 462 463 ret = hif_get_device_type(id->driver_data, revision_id, 464 &hif_type, &target_type); 465 if (ret < 0) { 466 HIF_ERROR("%s: invalid device ret %d id %d revision_id %d", 467 __func__, ret, (int)id->driver_data, revision_id); 468 return QDF_STATUS_E_FAILURE; 469 } 470 471 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 472 if (!memres) { 473 HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", __func__); 474 return -EIO; 475 } 476 477 ret = dma_set_mask(dev, DMA_BIT_MASK(32)); 478 if (ret) { 479 HIF_INFO("ath: 32-bit DMA not available\n"); 480 goto err_cleanup1; 481 } 482 483 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) 484 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 485 #else 486 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); 487 #endif 488 if (ret) { 489 HIF_ERROR("%s: failed to set dma mask error = %d", 490 __func__, ret); 491 return ret; 492 } 493 494 /* Arrange for access to Target SoC registers. */ 495 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) 496 mem = devm_ioremap_resource(&pdev->dev, memres); 497 #else 498 mem = devm_request_and_ioremap(&pdev->dev, memres); 499 #endif 500 if (IS_ERR(mem)) { 501 HIF_INFO("ath: ioremap error\n"); 502 ret = PTR_ERR(mem); 503 goto err_cleanup1; 504 } 505 506 sc->mem = mem; 507 ol_sc->mem = mem; 508 ol_sc->mem_pa = memres->start; 509 510 tgt_info = hif_get_target_info_handle((struct hif_opaque_softc *)ol_sc); 511 512 tgt_info->target_type = target_type; 513 hif_register_tbl_attach(ol_sc, hif_type); 514 hif_target_register_tbl_attach(ol_sc, target_type); 515 516 /* QCA_WIFI_QCA8074_VP:Should not be executed on 8074 VP platform */ 517 if (tgt_info->target_type != TARGET_TYPE_QCA8074) { 518 if (hif_ahb_enable_radio(sc, pdev, id) != 0) { 519 HIF_INFO("error in enabling soc\n"); 520 return -EIO; 521 } 522 523 if (hif_target_sync_ahb(ol_sc) < 0) { 524 ret = -EIO; 525 goto err_target_sync; 526 } 527 } 528 HIF_TRACE("%s: X - hif_type = 0x%x, target_type = 0x%x", 529 __func__, hif_type, target_type); 530 531 return QDF_STATUS_SUCCESS; 532 err_target_sync: 533 /* QCA_WIFI_QCA8074_VP:Should not be executed on 8074 VP platform */ 534 if (tgt_info->target_type != TARGET_TYPE_QCA8074) { 535 HIF_INFO("Error: Disabling target\n"); 536 hif_ahb_disable_bus(ol_sc); 537 } 538 err_cleanup1: 539 return ret; 540 } 541 542 543 /** 544 * hif_reset_soc() - reset soc 545 * 546 * @hif_ctx: HIF context 547 * 548 * This function resets soc and helds the 549 * target in reset state 550 * 551 * Return: void 552 */ 553 /* Function to reset SoC */ 554 void hif_ahb_reset_soc(struct hif_softc *hif_ctx) 555 { 556 hif_ahb_device_reset(hif_ctx); 557 } 558 559 560 /** 561 * hif_nointrs() - disable IRQ 562 * 563 * @scn: struct hif_softc 564 * 565 * This function stops interrupt(s) 566 * 567 * Return: none 568 */ 569 void hif_ahb_nointrs(struct hif_softc *scn) 570 { 571 int i; 572 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 573 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 574 struct CE_attr *host_ce_conf = hif_state->host_ce_config; 575 576 ce_unregister_irq(hif_state, CE_ALL_BITMAP); 577 578 if (scn->request_irq_done == false) 579 return; 580 581 if (sc->num_msi_intrs > 0) { 582 /* MSI interrupt(s) */ 583 for (i = 0; i < sc->num_msi_intrs; i++) { 584 free_irq(sc->irq + i, sc); 585 } 586 sc->num_msi_intrs = 0; 587 } else { 588 if (!scn->per_ce_irq) { 589 free_irq(sc->irq, sc); 590 } else { 591 for (i = 0; i < scn->ce_count; i++) { 592 if (host_ce_conf[i].flags 593 & CE_ATTR_DISABLE_INTR) 594 continue; 595 596 free_irq(ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i], 597 &hif_state->tasklets[i]); 598 } 599 hif_ahb_deconfigure_grp_irq(scn); 600 } 601 } 602 scn->request_irq_done = false; 603 604 } 605 606 /** 607 * ce_irq_enable() - enable copy engine IRQ 608 * @scn: struct hif_softc 609 * @ce_id: ce_id 610 * 611 * This function enables the interrupt for the radio. 612 * 613 * Return: N/A 614 */ 615 void hif_ahb_irq_enable(struct hif_softc *scn, int ce_id) 616 { 617 uint32_t regval; 618 uint32_t reg_offset = 0; 619 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 620 struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id]; 621 struct hif_target_info *tgt_info = &scn->target_info; 622 623 if (scn->per_ce_irq) { 624 if (target_ce_conf->pipedir & PIPEDIR_OUT) { 625 reg_offset = HOST_IE_ADDRESS; 626 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 627 regval = hif_read32_mb(scn->mem + reg_offset); 628 regval |= HOST_IE_REG1_CE_BIT(ce_id); 629 hif_write32_mb(scn->mem + reg_offset, regval); 630 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 631 } 632 if (target_ce_conf->pipedir & PIPEDIR_IN) { 633 reg_offset = HOST_IE_ADDRESS_2; 634 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 635 regval = hif_read32_mb(scn->mem + reg_offset); 636 regval |= HOST_IE_REG2_CE_BIT(ce_id); 637 hif_write32_mb(scn->mem + reg_offset, regval); 638 if (tgt_info->target_type == TARGET_TYPE_QCA8074) { 639 /* Enable destination ring interrupts for 8074 640 * TODO: To be removed in 2.0 HW */ 641 regval = hif_read32_mb(scn->mem + 642 HOST_IE_ADDRESS_3); 643 regval |= HOST_IE_REG3_CE_BIT(ce_id); 644 } 645 hif_write32_mb(scn->mem + HOST_IE_ADDRESS_3, regval); 646 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 647 } 648 } else { 649 hif_pci_irq_enable(scn, ce_id); 650 } 651 } 652 653 /** 654 * ce_irq_disable() - disable copy engine IRQ 655 * @scn: struct hif_softc 656 * @ce_id: ce_id 657 * 658 * Return: N/A 659 */ 660 void hif_ahb_irq_disable(struct hif_softc *scn, int ce_id) 661 { 662 uint32_t regval; 663 uint32_t reg_offset = 0; 664 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 665 struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id]; 666 struct hif_target_info *tgt_info = &scn->target_info; 667 668 if (scn->per_ce_irq) { 669 if (target_ce_conf->pipedir & PIPEDIR_OUT) { 670 reg_offset = HOST_IE_ADDRESS; 671 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 672 regval = hif_read32_mb(scn->mem + reg_offset); 673 regval &= ~HOST_IE_REG1_CE_BIT(ce_id); 674 hif_write32_mb(scn->mem + reg_offset, regval); 675 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 676 } 677 if (target_ce_conf->pipedir & PIPEDIR_IN) { 678 reg_offset = HOST_IE_ADDRESS_2; 679 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 680 regval = hif_read32_mb(scn->mem + reg_offset); 681 regval &= ~HOST_IE_REG2_CE_BIT(ce_id); 682 hif_write32_mb(scn->mem + reg_offset, regval); 683 if (tgt_info->target_type == TARGET_TYPE_QCA8074) { 684 /* Disable destination ring interrupts for 8074 685 * TODO: To be removed in 2.0 HW */ 686 regval = hif_read32_mb(scn->mem + 687 HOST_IE_ADDRESS_3); 688 regval &= ~HOST_IE_REG3_CE_BIT(ce_id); 689 } 690 hif_write32_mb(scn->mem + HOST_IE_ADDRESS_3, regval); 691 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 692 } 693 } 694 } 695 696 void hif_ahb_exec_grp_irq_disable(struct hif_exec_context *hif_ext_group) 697 { 698 int i; 699 700 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 701 if (hif_ext_group->irq_enabled) { 702 for (i = 0; i < hif_ext_group->numirq; i++) { 703 disable_irq_nosync(hif_ext_group->os_irq[i]); 704 } 705 hif_ext_group->irq_enabled = false; 706 } 707 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 708 } 709 710 void hif_ahb_exec_grp_irq_enable(struct hif_exec_context *hif_ext_group) 711 { 712 int i; 713 714 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 715 if (!hif_ext_group->irq_enabled) { 716 for (i = 0; i < hif_ext_group->numirq; i++) { 717 enable_irq(hif_ext_group->os_irq[i]); 718 } 719 hif_ext_group->irq_enabled = true; 720 } 721 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 722 } 723 724 /** 725 * hif_ahb_needs_bmi() - return true if the soc needs bmi through the driver 726 * @scn: hif context 727 * 728 * Return: true if soc needs driver bmi otherwise false 729 */ 730 bool hif_ahb_needs_bmi(struct hif_softc *scn) 731 { 732 return !ce_srng_based(scn); 733 } 734