1 /* 2 * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /** 20 * DOC: if_ahb.c 21 * 22 * c file for ahb specific implementations. 23 */ 24 25 #include "hif.h" 26 #include "target_type.h" 27 #include "hif_main.h" 28 #include "hif_debug.h" 29 #include "hif_io32.h" 30 #include "ce_main.h" 31 #include "ce_api.h" 32 #include "ce_tasklet.h" 33 #include "if_ahb.h" 34 #include "if_pci.h" 35 #include "ahb_api.h" 36 #include "pci_api.h" 37 #include "hif_napi.h" 38 #include "qal_vbus_dev.h" 39 40 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) 41 #define IRQF_DISABLED 0x00000020 42 #endif 43 44 #define HIF_IC_CE0_IRQ_OFFSET 4 45 #define HIF_IC_MAX_IRQ 52 46 47 static uint8_t ic_irqnum[HIF_IC_MAX_IRQ]; 48 /* integrated chip irq names */ 49 const char *ic_irqname[HIF_IC_MAX_IRQ] = { 50 "misc-pulse1", 51 "misc-latch", 52 "sw-exception", 53 "watchdog", 54 "ce0", 55 "ce1", 56 "ce2", 57 "ce3", 58 "ce4", 59 "ce5", 60 "ce6", 61 "ce7", 62 "ce8", 63 "ce9", 64 "ce10", 65 "ce11", 66 "host2wbm-desc-feed", 67 "host2reo-re-injection", 68 "host2reo-command", 69 "host2rxdma-monitor-ring3", 70 "host2rxdma-monitor-ring2", 71 "host2rxdma-monitor-ring1", 72 "reo2ost-exception", 73 "wbm2host-rx-release", 74 "reo2host-status", 75 "reo2host-destination-ring4", 76 "reo2host-destination-ring3", 77 "reo2host-destination-ring2", 78 "reo2host-destination-ring1", 79 "rxdma2host-monitor-destination-mac3", 80 "rxdma2host-monitor-destination-mac2", 81 "rxdma2host-monitor-destination-mac1", 82 "ppdu-end-interrupts-mac3", 83 "ppdu-end-interrupts-mac2", 84 "ppdu-end-interrupts-mac1", 85 "rxdma2host-monitor-status-ring-mac3", 86 "rxdma2host-monitor-status-ring-mac2", 87 "rxdma2host-monitor-status-ring-mac1", 88 "host2rxdma-host-buf-ring-mac3", 89 "host2rxdma-host-buf-ring-mac2", 90 "host2rxdma-host-buf-ring-mac1", 91 "rxdma2host-destination-ring-mac3", 92 "rxdma2host-destination-ring-mac2", 93 "rxdma2host-destination-ring-mac1", 94 "host2tcl-input-ring4", 95 "host2tcl-input-ring3", 96 "host2tcl-input-ring2", 97 "host2tcl-input-ring1", 98 "wbm2host-tx-completions-ring3", 99 "wbm2host-tx-completions-ring2", 100 "wbm2host-tx-completions-ring1", 101 "tcl2host-status-ring", 102 }; 103 104 /** hif_ahb_get_irq_name() - get irqname 105 * This function gives irqnumber to irqname 106 * mapping. 107 * 108 * @irq_no: irq number 109 * 110 * Return: irq name 111 */ 112 const char *hif_ahb_get_irq_name(int irq_no) 113 { 114 return ic_irqname[irq_no]; 115 } 116 117 /** 118 * hif_disable_isr() - disable isr 119 * 120 * This function disables isr and kills tasklets 121 * 122 * @hif_ctx: struct hif_softc 123 * 124 * Return: void 125 */ 126 void hif_ahb_disable_isr(struct hif_softc *scn) 127 { 128 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 129 130 hif_exec_kill(&scn->osc); 131 hif_nointrs(scn); 132 ce_tasklet_kill(scn); 133 tasklet_kill(&sc->intr_tq); 134 qdf_atomic_set(&scn->active_tasklet_cnt, 0); 135 qdf_atomic_set(&scn->active_grp_tasklet_cnt, 0); 136 } 137 138 /** 139 * hif_dump_registers() - dump bus debug registers 140 * @scn: struct hif_opaque_softc 141 * 142 * This function dumps hif bus debug registers 143 * 144 * Return: 0 for success or error code 145 */ 146 int hif_ahb_dump_registers(struct hif_softc *hif_ctx) 147 { 148 int status; 149 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 150 151 status = hif_dump_ce_registers(scn); 152 if (status) 153 HIF_ERROR("%s: Dump CE Registers Failed status %d", __func__, 154 status); 155 156 return 0; 157 } 158 159 /** 160 * hif_ahb_close() - hif_bus_close 161 * @scn: pointer to the hif context. 162 * 163 * This is a callback function for hif_bus_close. 164 * 165 * 166 * Return: n/a 167 */ 168 void hif_ahb_close(struct hif_softc *scn) 169 { 170 hif_ce_close(scn); 171 } 172 173 /** 174 * hif_bus_open() - hif_ahb open 175 * @hif_ctx: hif context 176 * @bus_type: bus type 177 * 178 * This is a callback function for hif_bus_open. 179 * 180 * Return: n/a 181 */ 182 QDF_STATUS hif_ahb_open(struct hif_softc *hif_ctx, enum qdf_bus_type bus_type) 183 { 184 185 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_ctx); 186 187 qdf_spinlock_create(&sc->irq_lock); 188 return hif_ce_open(hif_ctx); 189 } 190 191 /** 192 * hif_bus_configure() - Configure the bus 193 * @scn: pointer to the hif context. 194 * 195 * This function configure the ahb bus 196 * 197 * return: 0 for success. nonzero for failure. 198 */ 199 int hif_ahb_bus_configure(struct hif_softc *scn) 200 { 201 return hif_pci_bus_configure(scn); 202 } 203 204 /** 205 * hif_configure_msi_ahb - Configure MSI interrupts 206 * @sc : pointer to the hif context 207 * 208 * return: 0 for success. nonzero for failure. 209 */ 210 211 int hif_configure_msi_ahb(struct hif_pci_softc *sc) 212 { 213 return 0; 214 } 215 216 /** 217 * hif_ahb_configure_legacy_irq() - Configure Legacy IRQ 218 * @sc: pointer to the hif context. 219 * 220 * This function registers the irq handler and enables legacy interrupts 221 * 222 * return: 0 for success. nonzero for failure. 223 */ 224 int hif_ahb_configure_legacy_irq(struct hif_pci_softc *sc) 225 { 226 int ret = 0; 227 struct hif_softc *scn = HIF_GET_SOFTC(sc); 228 struct platform_device *pdev = (struct platform_device *)sc->pdev; 229 int irq = 0; 230 231 /* do not support MSI or MSI IRQ failed */ 232 tasklet_init(&sc->intr_tq, wlan_tasklet, (unsigned long)sc); 233 qal_vbus_get_irq((struct qdf_pfm_hndl *)pdev, "legacy", &irq); 234 if (irq < 0) { 235 dev_err(&pdev->dev, "Unable to get irq\n"); 236 ret = -1; 237 goto end; 238 } 239 ret = request_irq(irq, hif_pci_legacy_ce_interrupt_handler, 240 IRQF_DISABLED, "wlan_ahb", sc); 241 if (ret) { 242 dev_err(&pdev->dev, "ath_request_irq failed\n"); 243 ret = -1; 244 goto end; 245 } 246 sc->irq = irq; 247 248 /* Use Legacy PCI Interrupts */ 249 hif_write32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS | 250 PCIE_INTR_ENABLE_ADDRESS), 251 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 252 /* read once to flush */ 253 hif_read32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS | 254 PCIE_INTR_ENABLE_ADDRESS)); 255 256 end: 257 return ret; 258 } 259 260 int hif_ahb_configure_irq(struct hif_pci_softc *sc) 261 { 262 int ret = 0; 263 struct hif_softc *scn = HIF_GET_SOFTC(sc); 264 struct platform_device *pdev = (struct platform_device *)sc->pdev; 265 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 266 struct CE_attr *host_ce_conf = hif_state->host_ce_config; 267 int irq = 0; 268 int i; 269 270 /* configure per CE interrupts */ 271 for (i = 0; i < scn->ce_count; i++) { 272 if (host_ce_conf[i].flags & CE_ATTR_DISABLE_INTR) 273 continue; 274 ret = pfrm_get_irq(&pdev->dev, (struct qdf_pfm_hndl *)pdev, 275 ic_irqname[HIF_IC_CE0_IRQ_OFFSET + i], 276 HIF_IC_CE0_IRQ_OFFSET + i, &irq); 277 if (ret) { 278 dev_err(&pdev->dev, "get irq failed\n"); 279 ret = -1; 280 goto end; 281 } 282 283 ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i] = irq; 284 ret = pfrm_request_irq(&pdev->dev, irq, 285 hif_ahb_interrupt_handler, 286 IRQF_TRIGGER_RISING, 287 ic_irqname[HIF_IC_CE0_IRQ_OFFSET + i], 288 &hif_state->tasklets[i]); 289 if (ret) { 290 dev_err(&pdev->dev, "ath_request_irq failed\n"); 291 ret = -1; 292 goto end; 293 } 294 hif_ahb_irq_enable(scn, i); 295 } 296 297 end: 298 return ret; 299 } 300 301 int hif_ahb_configure_grp_irq(struct hif_softc *scn, 302 struct hif_exec_context *hif_ext_group) 303 { 304 int ret = 0; 305 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 306 struct platform_device *pdev = (struct platform_device *)sc->pdev; 307 int irq = 0; 308 int j; 309 310 /* configure external interrupts */ 311 hif_ext_group->irq_enable = &hif_ahb_exec_grp_irq_enable; 312 hif_ext_group->irq_disable = &hif_ahb_exec_grp_irq_disable; 313 hif_ext_group->irq_name = &hif_ahb_get_irq_name; 314 hif_ext_group->work_complete = &hif_dummy_grp_done; 315 316 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 317 318 for (j = 0; j < hif_ext_group->numirq; j++) { 319 ret = pfrm_get_irq(&pdev->dev, (struct qdf_pfm_hndl *)pdev, 320 ic_irqname[hif_ext_group->irq[j]], 321 hif_ext_group->irq[j], &irq); 322 if (ret) { 323 dev_err(&pdev->dev, "get irq failed\n"); 324 ret = -1; 325 goto end; 326 } 327 ic_irqnum[hif_ext_group->irq[j]] = irq; 328 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); 329 ret = pfrm_request_irq(scn->qdf_dev->dev, 330 irq, hif_ext_group_interrupt_handler, 331 IRQF_TRIGGER_RISING, 332 ic_irqname[hif_ext_group->irq[j]], 333 hif_ext_group); 334 if (ret) { 335 dev_err(&pdev->dev, "ath_request_irq failed\n"); 336 ret = -1; 337 goto end; 338 } 339 hif_ext_group->os_irq[j] = irq; 340 } 341 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 342 343 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 344 hif_ext_group->irq_requested = true; 345 346 end: 347 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 348 return ret; 349 } 350 351 void hif_ahb_deconfigure_grp_irq(struct hif_softc *scn) 352 { 353 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 354 struct hif_exec_context *hif_ext_group; 355 int i, j; 356 int irq = 0; 357 358 /* configure external interrupts */ 359 for (i = 0; i < hif_state->hif_num_extgroup; i++) { 360 hif_ext_group = hif_state->hif_ext_group[i]; 361 if (hif_ext_group->irq_requested == true) { 362 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 363 hif_ext_group->irq_requested = false; 364 for (j = 0; j < hif_ext_group->numirq; j++) { 365 irq = hif_ext_group->os_irq[j]; 366 hif_ext_group->irq_enabled = false; 367 irq_clear_status_flags(irq, 368 IRQ_DISABLE_UNLAZY); 369 } 370 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 371 372 /* Avoid holding the irq_lock while freeing the irq 373 * as the same lock is being held by the irq handler 374 * while disabling the irq. This causes a deadlock 375 * between free_irq and irq_handler. 376 */ 377 for (j = 0; j < hif_ext_group->numirq; j++) { 378 irq = hif_ext_group->os_irq[j]; 379 pfrm_free_irq(scn->qdf_dev->dev, 380 irq, hif_ext_group); 381 } 382 } 383 } 384 } 385 386 irqreturn_t hif_ahb_interrupt_handler(int irq, void *context) 387 { 388 struct ce_tasklet_entry *tasklet_entry = context; 389 return ce_dispatch_interrupt(tasklet_entry->ce_id, tasklet_entry); 390 } 391 392 /** 393 * hif_target_sync() : ensure the target is ready 394 * @scn: hif control structure 395 * 396 * Informs fw that we plan to use legacy interupts so that 397 * it can begin booting. Ensures that the fw finishes booting 398 * before continuing. Should be called before trying to write 399 * to the targets other registers for the first time. 400 * 401 * Return: none 402 */ 403 int hif_target_sync_ahb(struct hif_softc *scn) 404 { 405 int val = 0; 406 int limit = 0; 407 408 while (limit < 50) { 409 hif_write32_mb(scn, scn->mem + 410 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS), 411 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 412 qdf_mdelay(10); 413 val = hif_read32_mb(scn, scn->mem + 414 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS)); 415 if (val == 0) 416 break; 417 limit++; 418 } 419 hif_write32_mb(scn, scn->mem + 420 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS), 421 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 422 hif_write32_mb(scn, scn->mem + FW_INDICATOR_ADDRESS, FW_IND_HOST_READY); 423 if (HAS_FW_INDICATOR) { 424 int wait_limit = 500; 425 int fw_ind = 0; 426 427 while (1) { 428 fw_ind = hif_read32_mb(scn, scn->mem + 429 FW_INDICATOR_ADDRESS); 430 if (fw_ind & FW_IND_INITIALIZED) 431 break; 432 if (wait_limit-- < 0) 433 break; 434 hif_write32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS | 435 PCIE_INTR_ENABLE_ADDRESS), 436 PCIE_INTR_FIRMWARE_MASK); 437 qdf_mdelay(10); 438 } 439 if (wait_limit < 0) { 440 HIF_TRACE("%s: FW signal timed out", __func__); 441 return -EIO; 442 } 443 HIF_TRACE("%s: Got FW signal, retries = %x", __func__, 444 500-wait_limit); 445 } 446 447 return 0; 448 } 449 450 /** 451 * hif_disable_bus() - Disable the bus 452 * @scn : pointer to the hif context 453 * 454 * This function disables the bus and helds the target in reset state 455 * 456 * Return: none 457 */ 458 void hif_ahb_disable_bus(struct hif_softc *scn) 459 { 460 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 461 void __iomem *mem; 462 struct platform_device *pdev = (struct platform_device *)sc->pdev; 463 struct resource *memres = NULL; 464 int mem_pa_size = 0; 465 struct hif_target_info *tgt_info = NULL; 466 struct qdf_vbus_resource *vmres = NULL; 467 QDF_STATUS status; 468 469 tgt_info = &scn->target_info; 470 /*Disable WIFI clock input*/ 471 if (sc->mem) { 472 status = pfrm_platform_get_resource( 473 scn->qdf_dev->dev, 474 (struct qdf_pfm_hndl *)pdev, &vmres, 475 IORESOURCE_MEM, 0); 476 if (QDF_IS_STATUS_ERROR(status)) { 477 HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", 478 __func__); 479 return; 480 } 481 memres = (struct resource *)vmres; 482 if (memres) 483 mem_pa_size = memres->end - memres->start + 1; 484 485 /* Should not be executed on 8074 platform */ 486 if ((tgt_info->target_type != TARGET_TYPE_QCA8074) && 487 (tgt_info->target_type != TARGET_TYPE_QCA8074V2) && 488 (tgt_info->target_type != TARGET_TYPE_QCA6018)) { 489 hif_ahb_clk_enable_disable(&pdev->dev, 0); 490 491 hif_ahb_device_reset(scn); 492 } 493 mem = (void __iomem *)sc->mem; 494 if (mem) { 495 pfrm_devm_iounmap(&pdev->dev, mem); 496 pfrm_devm_release_mem_region(&pdev->dev, scn->mem_pa, 497 mem_pa_size); 498 sc->mem = NULL; 499 } 500 } 501 scn->mem = NULL; 502 } 503 504 /** 505 * hif_enable_bus() - Enable the bus 506 * @dev: dev 507 * @bdev: bus dev 508 * @bid: bus id 509 * @type: bus type 510 * 511 * This function enables the radio bus by enabling necessary 512 * clocks and waits for the target to get ready to proceed futher 513 * 514 * Return: QDF_STATUS 515 */ 516 QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc, 517 struct device *dev, void *bdev, 518 const struct hif_bus_id *bid, 519 enum hif_enable_type type) 520 { 521 int ret = 0; 522 int hif_type; 523 int target_type; 524 const struct platform_device_id *id = (struct platform_device_id *)bid; 525 struct platform_device *pdev = bdev; 526 struct hif_target_info *tgt_info = NULL; 527 struct resource *memres = NULL; 528 void __iomem *mem = NULL; 529 uint32_t revision_id = 0; 530 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(ol_sc); 531 QDF_STATUS status; 532 struct qdf_vbus_resource *vmres = NULL; 533 534 sc->pdev = (struct pci_dev *)pdev; 535 sc->dev = &pdev->dev; 536 sc->devid = id->driver_data; 537 538 ret = hif_get_device_type(id->driver_data, revision_id, 539 &hif_type, &target_type); 540 if (ret < 0) { 541 HIF_ERROR("%s: invalid device ret %d id %d revision_id %d", 542 __func__, ret, (int)id->driver_data, revision_id); 543 return QDF_STATUS_E_FAILURE; 544 } 545 546 status = pfrm_platform_get_resource(&pdev->dev, 547 (struct qdf_pfm_hndl *)pdev, 548 &vmres, 549 IORESOURCE_MEM, 0); 550 if (QDF_IS_STATUS_ERROR(status)) { 551 HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", __func__); 552 return -EIO; 553 } 554 memres = (struct resource *)vmres; 555 if (!memres) { 556 HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", __func__); 557 return -EIO; 558 } 559 560 ret = pfrm_dma_set_mask(dev, 32); 561 if (ret) { 562 HIF_INFO("ath: 32-bit DMA not available\n"); 563 goto err_cleanup1; 564 } 565 566 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) 567 ret = pfrm_dma_set_mask_and_coherent(dev, 32); 568 #else 569 ret = pfrm_dma_set_coherent_mask(dev, 32); 570 #endif 571 if (ret) { 572 HIF_ERROR("%s: failed to set dma mask error = %d", 573 __func__, ret); 574 return ret; 575 } 576 577 /* Arrange for access to Target SoC registers. */ 578 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) 579 status = pfrm_devm_ioremap_resource(dev, 580 (struct qdf_vbus_resource *)memres, 581 &mem); 582 #else 583 status = pfrm_devm_request_and_ioremap( 584 dev, 585 (struct qdf_vbus_resource *)memres, 586 &mem); 587 #endif 588 if (QDF_IS_STATUS_ERROR(status)) { 589 HIF_INFO("ath: ioremap error\n"); 590 ret = PTR_ERR(mem); 591 goto err_cleanup1; 592 } 593 594 sc->mem = mem; 595 ol_sc->mem = mem; 596 ol_sc->mem_pa = memres->start; 597 598 tgt_info = hif_get_target_info_handle((struct hif_opaque_softc *)ol_sc); 599 600 tgt_info->target_type = target_type; 601 hif_register_tbl_attach(ol_sc, hif_type); 602 hif_target_register_tbl_attach(ol_sc, target_type); 603 604 /* QCA_WIFI_QCA8074_VP:Should not be executed on 8074 VP platform */ 605 if ((tgt_info->target_type != TARGET_TYPE_QCA8074) && 606 (tgt_info->target_type != TARGET_TYPE_QCA8074V2) && 607 (tgt_info->target_type != TARGET_TYPE_QCA6018)) { 608 if (hif_ahb_enable_radio(sc, pdev, id) != 0) { 609 HIF_INFO("error in enabling soc\n"); 610 return -EIO; 611 } 612 613 if (hif_target_sync_ahb(ol_sc) < 0) { 614 ret = -EIO; 615 goto err_target_sync; 616 } 617 } 618 HIF_TRACE("%s: X - hif_type = 0x%x, target_type = 0x%x", 619 __func__, hif_type, target_type); 620 621 return QDF_STATUS_SUCCESS; 622 err_target_sync: 623 /* QCA_WIFI_QCA8074_VP:Should not be executed on 8074 VP platform */ 624 if ((tgt_info->target_type != TARGET_TYPE_QCA8074) && 625 (tgt_info->target_type != TARGET_TYPE_QCA8074V2) && 626 (tgt_info->target_type != TARGET_TYPE_QCA6018)) { 627 HIF_INFO("Error: Disabling target\n"); 628 hif_ahb_disable_bus(ol_sc); 629 } 630 err_cleanup1: 631 return ret; 632 } 633 634 635 /** 636 * hif_reset_soc() - reset soc 637 * 638 * @hif_ctx: HIF context 639 * 640 * This function resets soc and helds the 641 * target in reset state 642 * 643 * Return: void 644 */ 645 /* Function to reset SoC */ 646 void hif_ahb_reset_soc(struct hif_softc *hif_ctx) 647 { 648 hif_ahb_device_reset(hif_ctx); 649 } 650 651 652 /** 653 * hif_nointrs() - disable IRQ 654 * 655 * @scn: struct hif_softc 656 * 657 * This function stops interrupt(s) 658 * 659 * Return: none 660 */ 661 void hif_ahb_nointrs(struct hif_softc *scn) 662 { 663 int i; 664 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 665 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 666 struct CE_attr *host_ce_conf = hif_state->host_ce_config; 667 668 ce_unregister_irq(hif_state, CE_ALL_BITMAP); 669 670 if (scn->request_irq_done == false) 671 return; 672 673 if (sc->num_msi_intrs > 0) { 674 /* MSI interrupt(s) */ 675 for (i = 0; i < sc->num_msi_intrs; i++) { 676 pfrm_free_irq(scn->qdf_dev->dev, sc->irq + i, sc); 677 } 678 sc->num_msi_intrs = 0; 679 } else { 680 if (!scn->per_ce_irq) { 681 pfrm_free_irq(scn->qdf_dev->dev, sc->irq, sc); 682 } else { 683 for (i = 0; i < scn->ce_count; i++) { 684 if (host_ce_conf[i].flags 685 & CE_ATTR_DISABLE_INTR) 686 continue; 687 688 pfrm_free_irq( 689 scn->qdf_dev->dev, 690 ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i], 691 &hif_state->tasklets[i]); 692 } 693 hif_ahb_deconfigure_grp_irq(scn); 694 } 695 } 696 scn->request_irq_done = false; 697 698 } 699 700 /** 701 * ce_irq_enable() - enable copy engine IRQ 702 * @scn: struct hif_softc 703 * @ce_id: ce_id 704 * 705 * This function enables the interrupt for the radio. 706 * 707 * Return: N/A 708 */ 709 void hif_ahb_irq_enable(struct hif_softc *scn, int ce_id) 710 { 711 uint32_t regval; 712 uint32_t reg_offset = 0; 713 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 714 struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id]; 715 struct hif_target_info *tgt_info = &scn->target_info; 716 717 if (scn->per_ce_irq) { 718 if (target_ce_conf->pipedir & PIPEDIR_OUT) { 719 reg_offset = HOST_IE_ADDRESS; 720 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 721 regval = hif_read32_mb(scn, scn->mem + reg_offset); 722 regval |= HOST_IE_REG1_CE_BIT(ce_id); 723 hif_write32_mb(scn, scn->mem + reg_offset, regval); 724 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 725 } 726 if (target_ce_conf->pipedir & PIPEDIR_IN) { 727 reg_offset = HOST_IE_ADDRESS_2; 728 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 729 regval = hif_read32_mb(scn, scn->mem + reg_offset); 730 regval |= HOST_IE_REG2_CE_BIT(ce_id); 731 hif_write32_mb(scn, scn->mem + reg_offset, regval); 732 if (tgt_info->target_type == TARGET_TYPE_QCA8074 || 733 tgt_info->target_type == TARGET_TYPE_QCA8074V2 || 734 tgt_info->target_type == TARGET_TYPE_QCA6018) { 735 /* Enable destination ring interrupts for 736 * 8074, 8074V2 and 6018 737 */ 738 regval = hif_read32_mb(scn, scn->mem + 739 HOST_IE_ADDRESS_3); 740 regval |= HOST_IE_REG3_CE_BIT(ce_id); 741 742 hif_write32_mb(scn, scn->mem + 743 HOST_IE_ADDRESS_3, regval); 744 } 745 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 746 } 747 } else { 748 hif_pci_irq_enable(scn, ce_id); 749 } 750 } 751 752 /** 753 * ce_irq_disable() - disable copy engine IRQ 754 * @scn: struct hif_softc 755 * @ce_id: ce_id 756 * 757 * Return: N/A 758 */ 759 void hif_ahb_irq_disable(struct hif_softc *scn, int ce_id) 760 { 761 uint32_t regval; 762 uint32_t reg_offset = 0; 763 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 764 struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id]; 765 struct hif_target_info *tgt_info = &scn->target_info; 766 767 if (scn->per_ce_irq) { 768 if (target_ce_conf->pipedir & PIPEDIR_OUT) { 769 reg_offset = HOST_IE_ADDRESS; 770 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 771 regval = hif_read32_mb(scn, scn->mem + reg_offset); 772 regval &= ~HOST_IE_REG1_CE_BIT(ce_id); 773 hif_write32_mb(scn, scn->mem + reg_offset, regval); 774 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 775 } 776 if (target_ce_conf->pipedir & PIPEDIR_IN) { 777 reg_offset = HOST_IE_ADDRESS_2; 778 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 779 regval = hif_read32_mb(scn, scn->mem + reg_offset); 780 regval &= ~HOST_IE_REG2_CE_BIT(ce_id); 781 hif_write32_mb(scn, scn->mem + reg_offset, regval); 782 if (tgt_info->target_type == TARGET_TYPE_QCA8074 || 783 tgt_info->target_type == TARGET_TYPE_QCA8074V2 || 784 tgt_info->target_type == TARGET_TYPE_QCA6018) { 785 /* Disable destination ring interrupts for 786 * 8074, 8074V2 and 6018 787 */ 788 regval = hif_read32_mb(scn, scn->mem + 789 HOST_IE_ADDRESS_3); 790 regval &= ~HOST_IE_REG3_CE_BIT(ce_id); 791 792 hif_write32_mb(scn, scn->mem + 793 HOST_IE_ADDRESS_3, regval); 794 } 795 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 796 } 797 } 798 } 799 800 void hif_ahb_exec_grp_irq_disable(struct hif_exec_context *hif_ext_group) 801 { 802 int i; 803 804 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 805 if (hif_ext_group->irq_enabled) { 806 for (i = 0; i < hif_ext_group->numirq; i++) { 807 disable_irq_nosync(hif_ext_group->os_irq[i]); 808 } 809 hif_ext_group->irq_enabled = false; 810 } 811 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 812 } 813 814 void hif_ahb_exec_grp_irq_enable(struct hif_exec_context *hif_ext_group) 815 { 816 int i; 817 818 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 819 if (hif_ext_group->irq_requested && !hif_ext_group->irq_enabled) { 820 for (i = 0; i < hif_ext_group->numirq; i++) { 821 enable_irq(hif_ext_group->os_irq[i]); 822 } 823 hif_ext_group->irq_enabled = true; 824 } 825 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 826 } 827 828 /** 829 * hif_ahb_needs_bmi() - return true if the soc needs bmi through the driver 830 * @scn: hif context 831 * 832 * Return: true if soc needs driver bmi otherwise false 833 */ 834 bool hif_ahb_needs_bmi(struct hif_softc *scn) 835 { 836 return !ce_srng_based(scn); 837 } 838 839 void hif_ahb_display_stats(struct hif_softc *scn) 840 { 841 if (!scn) { 842 HIF_ERROR("%s, hif_scn null", __func__); 843 return; 844 } 845 hif_display_ce_stats(scn); 846 } 847 848 void hif_ahb_clear_stats(struct hif_softc *scn) 849 { 850 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 851 852 if (!hif_state) { 853 HIF_ERROR("%s, hif_state null", __func__); 854 return; 855 } 856 hif_clear_ce_stats(hif_state); 857 } 858