xref: /wlan-dirver/qca-wifi-host-cmn/hif/src/snoc/if_ahb.c (revision 2888b71da71bce103343119fa1b31f4a0cee07c8)
1 /*
2  * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved.
3  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 /**
21  * DOC: if_ahb.c
22  *
23  * c file for ahb specific implementations.
24  */
25 
26 #include "hif.h"
27 #include "target_type.h"
28 #include "hif_main.h"
29 #include "hif_debug.h"
30 #include "hif_io32.h"
31 #include "ce_main.h"
32 #include "ce_api.h"
33 #include "ce_tasklet.h"
34 #include "if_ahb.h"
35 #include "if_pci.h"
36 #include "ahb_api.h"
37 #include "pci_api.h"
38 #include "hif_napi.h"
39 #include "qal_vbus_dev.h"
40 #include "qdf_irq.h"
41 
42 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
43 #define IRQF_DISABLED 0x00000020
44 #endif
45 
46 #define HIF_IC_CE0_IRQ_OFFSET 4
47 #define HIF_IC_MAX_IRQ 53
48 
49 static uint16_t ic_irqnum[HIF_IC_MAX_IRQ];
50 /* integrated chip irq names */
51 const char *ic_irqname[HIF_IC_MAX_IRQ] = {
52 "misc-pulse1",
53 "misc-latch",
54 "sw-exception",
55 "watchdog",
56 "ce0",
57 "ce1",
58 "ce2",
59 "ce3",
60 "ce4",
61 "ce5",
62 "ce6",
63 "ce7",
64 "ce8",
65 "ce9",
66 "ce10",
67 "ce11",
68 "host2wbm-desc-feed",
69 "host2reo-re-injection",
70 "host2reo-command",
71 "host2rxdma-monitor-ring3",
72 "host2rxdma-monitor-ring2",
73 "host2rxdma-monitor-ring1",
74 "reo2ost-exception",
75 "wbm2host-rx-release",
76 "reo2host-status",
77 "reo2host-destination-ring4",
78 "reo2host-destination-ring3",
79 "reo2host-destination-ring2",
80 "reo2host-destination-ring1",
81 "rxdma2host-monitor-destination-mac3",
82 "rxdma2host-monitor-destination-mac2",
83 "rxdma2host-monitor-destination-mac1",
84 "ppdu-end-interrupts-mac3",
85 "ppdu-end-interrupts-mac2",
86 "ppdu-end-interrupts-mac1",
87 "rxdma2host-monitor-status-ring-mac3",
88 "rxdma2host-monitor-status-ring-mac2",
89 "rxdma2host-monitor-status-ring-mac1",
90 "host2rxdma-host-buf-ring-mac3",
91 "host2rxdma-host-buf-ring-mac2",
92 "host2rxdma-host-buf-ring-mac1",
93 "rxdma2host-destination-ring-mac3",
94 "rxdma2host-destination-ring-mac2",
95 "rxdma2host-destination-ring-mac1",
96 "host2tcl-input-ring4",
97 "host2tcl-input-ring3",
98 "host2tcl-input-ring2",
99 "host2tcl-input-ring1",
100 "wbm2host-tx-completions-ring4",
101 "wbm2host-tx-completions-ring3",
102 "wbm2host-tx-completions-ring2",
103 "wbm2host-tx-completions-ring1",
104 "tcl2host-status-ring",
105 };
106 
107 /** hif_ahb_get_irq_name() - get irqname
108  * This function gives irqnumber to irqname
109  * mapping.
110  *
111  * @irq_no: irq number
112  *
113  * Return: irq name
114  */
115 const char *hif_ahb_get_irq_name(int irq_no)
116 {
117 	return ic_irqname[irq_no];
118 }
119 
120 /**
121  * hif_disable_isr() - disable isr
122  *
123  * This function disables isr and kills tasklets
124  *
125  * @hif_ctx: struct hif_softc
126  *
127  * Return: void
128  */
129 void hif_ahb_disable_isr(struct hif_softc *scn)
130 {
131 	struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn);
132 	hif_exec_kill(&scn->osc);
133 	hif_nointrs(scn);
134 	ce_tasklet_kill(scn);
135 	tasklet_kill(&sc->intr_tq);
136 	qdf_atomic_set(&scn->active_tasklet_cnt, 0);
137 	qdf_atomic_set(&scn->active_grp_tasklet_cnt, 0);
138 }
139 
140 /**
141  * hif_dump_registers() - dump bus debug registers
142  * @scn: struct hif_opaque_softc
143  *
144  * This function dumps hif bus debug registers
145  *
146  * Return: 0 for success or error code
147  */
148 int hif_ahb_dump_registers(struct hif_softc *hif_ctx)
149 {
150 	int status;
151 	struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx);
152 
153 	status = hif_dump_ce_registers(scn);
154 	if (status)
155 		hif_err("Dump CE Registers Failed status %d", status);
156 
157 	return 0;
158 }
159 
160 /**
161  * hif_ahb_close() - hif_bus_close
162  * @scn: pointer to the hif context.
163  *
164  * This is a callback function for hif_bus_close.
165  *
166  *
167  * Return: n/a
168  */
169 void hif_ahb_close(struct hif_softc *scn)
170 {
171 	hif_ce_close(scn);
172 }
173 
174 /**
175  * hif_bus_open() - hif_ahb open
176  * @hif_ctx: hif context
177  * @bus_type: bus type
178  *
179  * This is a callback function for hif_bus_open.
180  *
181  * Return: n/a
182  */
183 QDF_STATUS hif_ahb_open(struct hif_softc *hif_ctx, enum qdf_bus_type bus_type)
184 {
185 
186 	struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_ctx);
187 
188 	qdf_spinlock_create(&sc->irq_lock);
189 	return hif_ce_open(hif_ctx);
190 }
191 
192 /**
193  * hif_bus_configure() - Configure the bus
194  * @scn: pointer to the hif context.
195  *
196  * This function configure the ahb bus
197  *
198  * return: 0 for success. nonzero for failure.
199  */
200 int hif_ahb_bus_configure(struct hif_softc *scn)
201 {
202 	return hif_pci_bus_configure(scn);
203 }
204 
205 static void hif_ahb_get_soc_info_pld(struct hif_pci_softc *sc,
206 				     struct device *dev)
207 {
208 	struct pld_soc_info info;
209 	int ret = 0;
210 
211 	ret = pld_get_soc_info(dev, &info);
212 	sc->mem = info.v_addr;
213 	sc->ce_sc.ol_sc.mem    = info.v_addr;
214 	sc->ce_sc.ol_sc.mem_pa = info.p_addr;
215 }
216 
217 int hif_ahb_configure_irq_by_ceid(struct hif_softc *scn, int ce_id)
218 {
219 	int ret = 0;
220 	struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn);
221 	struct platform_device *pdev = (struct platform_device *)sc->pdev;
222 	struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
223 	int irq = 0;
224 
225 	if (ce_id >= CE_COUNT_MAX)
226 		return -EINVAL;
227 
228 	ret = pfrm_get_irq(&pdev->dev, (struct qdf_pfm_hndl *)pdev,
229 			   ic_irqname[HIF_IC_CE0_IRQ_OFFSET + ce_id],
230 			   HIF_IC_CE0_IRQ_OFFSET + ce_id, &irq);
231 	if (ret) {
232 		dev_err(&pdev->dev, "get irq failed\n");
233 		ret = -EFAULT;
234 		goto end;
235 	}
236 
237 	ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + ce_id] = irq;
238 	ret = pfrm_request_irq(&pdev->dev, irq,
239 			       hif_ahb_interrupt_handler,
240 			       IRQF_TRIGGER_RISING,
241 			       ic_irqname[HIF_IC_CE0_IRQ_OFFSET + ce_id],
242 			       &hif_state->tasklets[ce_id]);
243 	if (ret) {
244 		dev_err(&pdev->dev, "ath_request_irq failed\n");
245 		ret = -EFAULT;
246 		goto end;
247 	}
248 	hif_ahb_irq_enable(scn, ce_id);
249 
250 end:
251 	return ret;
252 }
253 
254 int hif_ahb_configure_irq(struct hif_pci_softc *sc)
255 {
256 	int ret = 0;
257 	struct hif_softc *scn = HIF_GET_SOFTC(sc);
258 	struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
259 	struct CE_attr *host_ce_conf = hif_state->host_ce_config;
260 	int i;
261 
262 	/* configure per CE interrupts */
263 	for (i = 0; i < scn->ce_count; i++) {
264 		if (host_ce_conf[i].flags & CE_ATTR_DISABLE_INTR)
265 			continue;
266 
267 		if (host_ce_conf[i].flags & CE_ATTR_INIT_ON_DEMAND)
268 			continue;
269 
270 		ret = hif_ahb_configure_irq_by_ceid(scn, i);
271 		if (ret)
272 			goto end;
273 	}
274 
275 end:
276 	return ret;
277 }
278 
279 int hif_ahb_configure_grp_irq(struct hif_softc *scn,
280 			      struct hif_exec_context *hif_ext_group)
281 {
282 	int ret = 0;
283 	struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn);
284 	struct platform_device *pdev = (struct platform_device *)sc->pdev;
285 	int irq = 0;
286 	int j;
287 
288 	/* configure external interrupts */
289 	hif_ext_group->irq_enable = &hif_ahb_exec_grp_irq_enable;
290 	hif_ext_group->irq_disable = &hif_ahb_exec_grp_irq_disable;
291 	hif_ext_group->irq_name = &hif_ahb_get_irq_name;
292 	hif_ext_group->work_complete = &hif_dummy_grp_done;
293 
294 	for (j = 0; j < hif_ext_group->numirq; j++) {
295 		ret = pfrm_get_irq(&pdev->dev, (struct qdf_pfm_hndl *)pdev,
296 				   ic_irqname[hif_ext_group->irq[j]],
297 				   hif_ext_group->irq[j], &irq);
298 		if (ret) {
299 			dev_err(&pdev->dev, "get irq failed\n");
300 			ret = -EFAULT;
301 			goto end;
302 		}
303 		ic_irqnum[hif_ext_group->irq[j]] = irq;
304 		hif_ext_group->os_irq[j] = irq;
305 	}
306 
307 	for (j = 0; j < hif_ext_group->numirq; j++) {
308 		irq = hif_ext_group->os_irq[j];
309 
310 		qdf_spin_lock_irqsave(&hif_ext_group->irq_lock);
311 		qdf_dev_set_irq_status_flags(irq, QDF_IRQ_DISABLE_UNLAZY);
312 		qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock);
313 
314 		ret = pfrm_request_irq(scn->qdf_dev->dev,
315 				       irq, hif_ext_group_interrupt_handler,
316 				       IRQF_TRIGGER_RISING,
317 				       ic_irqname[hif_ext_group->irq[j]],
318 				       hif_ext_group);
319 		if (ret) {
320 			dev_err(&pdev->dev, "ath_request_irq failed\n");
321 			ret = -EFAULT;
322 			goto end;
323 		}
324 	}
325 
326 	qdf_spin_lock_irqsave(&hif_ext_group->irq_lock);
327 	hif_ext_group->irq_requested = true;
328 	qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock);
329 end:
330 	return ret;
331 }
332 
333 void hif_ahb_deconfigure_grp_irq(struct hif_softc *scn)
334 {
335 	struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
336 	struct hif_exec_context *hif_ext_group;
337 	int i, j;
338 	int irq = 0;
339 
340 	/* configure external interrupts */
341 	for (i = 0; i < hif_state->hif_num_extgroup; i++) {
342 		hif_ext_group = hif_state->hif_ext_group[i];
343 		if (hif_ext_group->irq_requested == true) {
344 			qdf_spin_lock_irqsave(&hif_ext_group->irq_lock);
345 			hif_ext_group->irq_requested = false;
346 			for (j = 0; j < hif_ext_group->numirq; j++) {
347 				irq = hif_ext_group->os_irq[j];
348 				hif_ext_group->irq_enabled = false;
349 				qdf_dev_clear_irq_status_flags(
350 							irq,
351 							QDF_IRQ_DISABLE_UNLAZY);
352 			}
353 			qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock);
354 
355 			/* Avoid holding the irq_lock while freeing the irq
356 			 * as the same lock is being held by the irq handler
357 			 * while disabling the irq. This causes a deadlock
358 			 * between free_irq and irq_handler.
359 			 */
360 			for (j = 0; j < hif_ext_group->numirq; j++) {
361 				irq = hif_ext_group->os_irq[j];
362 				pfrm_free_irq(scn->qdf_dev->dev,
363 					      irq, hif_ext_group);
364 			}
365 		}
366 	}
367 }
368 
369 irqreturn_t hif_ahb_interrupt_handler(int irq, void *context)
370 {
371 	struct ce_tasklet_entry *tasklet_entry = context;
372 	return ce_dispatch_interrupt(tasklet_entry->ce_id, tasklet_entry);
373 }
374 
375 /**
376  * hif_disable_bus() - Disable the bus
377  * @scn : pointer to the hif context
378  *
379  * This function disables the bus and helds the target in reset state
380  *
381  * Return: none
382  */
383 void hif_ahb_disable_bus(struct hif_softc *scn)
384 {
385 	struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn);
386 	void __iomem *mem;
387 	struct platform_device *pdev = (struct platform_device *)sc->pdev;
388 	struct resource *memres = NULL;
389 	int mem_pa_size = 0;
390 	struct hif_target_info *tgt_info = NULL;
391 	struct qdf_vbus_resource *vmres = NULL;
392 	QDF_STATUS status;
393 
394 	tgt_info = &scn->target_info;
395 	/*Disable WIFI clock input*/
396 	if (sc->mem) {
397 		status = pfrm_platform_get_resource(
398 				scn->qdf_dev->dev,
399 				(struct qdf_pfm_hndl *)pdev, &vmres,
400 				IORESOURCE_MEM, 0);
401 		if (QDF_IS_STATUS_ERROR(status)) {
402 			hif_info("Failed to get IORESOURCE_MEM");
403 			return;
404 		}
405 		memres = (struct resource *)vmres;
406 		if (memres)
407 			mem_pa_size = memres->end - memres->start + 1;
408 
409 		if (tgt_info->target_type == TARGET_TYPE_QCA5018 ||
410 		    tgt_info->target_type == TARGET_TYPE_QCA5332) {
411 			iounmap(sc->mem_ce);
412 			sc->mem_ce = NULL;
413 			scn->mem_ce = NULL;
414 		}
415 		mem = (void __iomem *)sc->mem;
416 		if (mem) {
417 			pfrm_devm_iounmap(&pdev->dev, mem);
418 			pfrm_devm_release_mem_region(&pdev->dev, scn->mem_pa,
419 						     mem_pa_size);
420 			sc->mem = NULL;
421 			pld_set_bar_addr(&pdev->dev, NULL);
422 		}
423 	}
424 	scn->mem = NULL;
425 }
426 
427 /**
428  * hif_enable_bus() - Enable the bus
429  * @dev: dev
430  * @bdev: bus dev
431  * @bid: bus id
432  * @type: bus type
433  *
434  * This function enables the radio bus by enabling necessary
435  * clocks and waits for the target to get ready to proceed futher
436  *
437  * Return: QDF_STATUS
438  */
439 QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc,
440 		struct device *dev, void *bdev,
441 		const struct hif_bus_id *bid,
442 		enum hif_enable_type type)
443 {
444 	int ret = 0;
445 	int hif_type;
446 	int target_type;
447 	const struct platform_device_id *id = (struct platform_device_id *)bid;
448 	struct platform_device *pdev = bdev;
449 	struct hif_target_info *tgt_info = NULL;
450 	struct resource *memres = NULL;
451 	void __iomem *mem = NULL;
452 	uint32_t revision_id = 0;
453 	struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(ol_sc);
454 	QDF_STATUS status;
455 	struct qdf_vbus_resource *vmres = NULL;
456 
457 	sc->pdev = (struct pci_dev *)pdev;
458 	sc->dev = &pdev->dev;
459 	sc->devid = id->driver_data;
460 
461 	ret = hif_get_device_type(id->driver_data, revision_id,
462 			&hif_type, &target_type);
463 	if (ret < 0) {
464 		hif_err("Invalid device ret %d id %d revision_id %d",
465 			ret, (int)id->driver_data, revision_id);
466 		return QDF_STATUS_E_FAILURE;
467 	}
468 
469 	if (target_type == TARGET_TYPE_QCN6122) {
470 		hif_ahb_get_soc_info_pld(sc, dev);
471 		hif_update_irq_ops_with_pci(ol_sc);
472 	} else {
473 		status = pfrm_platform_get_resource(&pdev->dev,
474 						    (struct qdf_pfm_hndl *)pdev,
475 						    &vmres,
476 						    IORESOURCE_MEM, 0);
477 		if (QDF_IS_STATUS_ERROR(status)) {
478 			hif_err("Failed to get IORESOURCE_MEM");
479 			return status;
480 		}
481 		memres = (struct resource *)vmres;
482 		if (!memres) {
483 			hif_err("Failed to get IORESOURCE_MEM");
484 			return QDF_STATUS_E_IO;
485 		}
486 
487 		/* Arrange for access to Target SoC registers. */
488 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
489 		status = pfrm_devm_ioremap_resource(
490 					dev,
491 					(struct qdf_vbus_resource *)memres,
492 					&mem);
493 #else
494 		status = pfrm_devm_request_and_ioremap(
495 					dev,
496 					(struct qdf_vbus_resource *)memres,
497 					&mem);
498 #endif
499 		if (QDF_IS_STATUS_ERROR(status)) {
500 			hif_err("ath: ioremap error");
501 			ret = PTR_ERR(mem);
502 			goto err_cleanup1;
503 		}
504 
505 		sc->mem = mem;
506 		pld_set_bar_addr(dev, mem);
507 		ol_sc->mem = mem;
508 		ol_sc->mem_pa = memres->start;
509 	}
510 
511 	ret = pfrm_dma_set_mask(dev, 32);
512 	if (ret) {
513 		hif_err("ath: 32-bit DMA not available");
514 		status = QDF_STATUS_E_IO;
515 		goto err_cleanup1;
516 	}
517 
518 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
519 	ret = pfrm_dma_set_mask_and_coherent(dev, 32);
520 #else
521 	ret = pfrm_dma_set_coherent_mask(dev, 32);
522 #endif
523 	if (ret) {
524 		hif_err("Failed to set dma mask error = %d", ret);
525 		return QDF_STATUS_E_IO;
526 	}
527 
528 	tgt_info = hif_get_target_info_handle((struct hif_opaque_softc *)ol_sc);
529 
530 	tgt_info->target_type = target_type;
531 	hif_register_tbl_attach(ol_sc, hif_type);
532 	hif_target_register_tbl_attach(ol_sc, target_type);
533 	/*
534 	 * In QCA5018 CE region moved to SOC outside WCSS block.
535 	 * Allocate separate I/O remap to access CE registers.
536 	 */
537 	if (tgt_info->target_type == TARGET_TYPE_QCA5018 ||
538 	    tgt_info->target_type == TARGET_TYPE_QCA5332) {
539 		struct hif_softc *scn = HIF_GET_SOFTC(sc);
540 
541 		sc->mem_ce = ioremap_nocache(HOST_CE_ADDRESS, HOST_CE_SIZE);
542 		if (IS_ERR(sc->mem_ce)) {
543 			hif_err("CE: ioremap failed");
544 			return QDF_STATUS_E_IO;
545 		}
546 		ol_sc->mem_ce = sc->mem_ce;
547 	}
548 
549 	hif_info("X - hif_type = 0x%x, target_type = 0x%x",
550 		hif_type, target_type);
551 
552 	return QDF_STATUS_SUCCESS;
553 err_cleanup1:
554 	return status;
555 }
556 
557 /**
558  * hif_nointrs() - disable IRQ
559  *
560  * @scn: struct hif_softc
561  *
562  * This function stops interrupt(s)
563  *
564  * Return: none
565  */
566 void hif_ahb_nointrs(struct hif_softc *scn)
567 {
568 	int i;
569 	struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn);
570 	struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
571 	struct CE_attr *host_ce_conf = hif_state->host_ce_config;
572 
573 	scn->free_irq_done = true;
574 	ce_unregister_irq(hif_state, CE_ALL_BITMAP);
575 
576 	if (scn->request_irq_done == false)
577 		return;
578 
579 	if (sc->num_msi_intrs > 0) {
580 		/* MSI interrupt(s) */
581 		for (i = 0; i < sc->num_msi_intrs; i++) {
582 			pfrm_free_irq(scn->qdf_dev->dev, sc->irq + i, sc);
583 		}
584 		sc->num_msi_intrs = 0;
585 	} else {
586 		if (!scn->per_ce_irq) {
587 			pfrm_free_irq(scn->qdf_dev->dev, sc->irq, sc);
588 		} else {
589 			for (i = 0; i < scn->ce_count; i++) {
590 				if (host_ce_conf[i].flags
591 						& CE_ATTR_DISABLE_INTR)
592 					continue;
593 				if (!hif_state->tasklets[i].inited)
594 					continue;
595 				pfrm_free_irq(
596 					scn->qdf_dev->dev,
597 					ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i],
598 					&hif_state->tasklets[i]);
599 			}
600 			hif_ahb_deconfigure_grp_irq(scn);
601 		}
602 	}
603 	scn->request_irq_done = false;
604 
605 }
606 
607 /**
608  * ce_irq_enable() - enable copy engine IRQ
609  * @scn: struct hif_softc
610  * @ce_id: ce_id
611  *
612  * This function enables the interrupt for the radio.
613  *
614  * Return: N/A
615  */
616 void hif_ahb_irq_enable(struct hif_softc *scn, int ce_id)
617 {
618 	uint32_t regval;
619 	uint32_t reg_offset = 0;
620 	struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
621 	struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id];
622 	struct hif_target_info *tgt_info = &scn->target_info;
623 	void *mem = scn->mem_ce ? scn->mem_ce : scn->mem;
624 
625 	if (scn->per_ce_irq) {
626 		if (target_ce_conf->pipedir & PIPEDIR_OUT) {
627 			reg_offset = HOST_IE_ADDRESS;
628 			qdf_spin_lock_irqsave(&hif_state->irq_reg_lock);
629 			regval = hif_read32_mb(scn, mem + reg_offset);
630 			regval |= HOST_IE_REG1_CE_BIT(ce_id);
631 			hif_write32_mb(scn, mem + reg_offset, regval);
632 			qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock);
633 		}
634 		if (target_ce_conf->pipedir & PIPEDIR_IN) {
635 			reg_offset = HOST_IE_ADDRESS_2;
636 			qdf_spin_lock_irqsave(&hif_state->irq_reg_lock);
637 			regval = hif_read32_mb(scn, mem + reg_offset);
638 			regval |= HOST_IE_REG2_CE_BIT(ce_id);
639 			hif_write32_mb(scn, mem + reg_offset, regval);
640 			if (tgt_info->target_type == TARGET_TYPE_QCA8074 ||
641 			    tgt_info->target_type == TARGET_TYPE_QCA8074V2 ||
642 			    tgt_info->target_type == TARGET_TYPE_QCA9574 ||
643 			    tgt_info->target_type == TARGET_TYPE_QCA5332 ||
644 			    tgt_info->target_type == TARGET_TYPE_QCA5018 ||
645 			    tgt_info->target_type == TARGET_TYPE_QCA6018) {
646 				/* Enable destination ring interrupts for
647 				 * 8074, 8074V2, 6018 and 50xx
648 				 */
649 				regval = hif_read32_mb(scn, mem +
650 					HOST_IE_ADDRESS_3);
651 				regval |= HOST_IE_REG3_CE_BIT(ce_id);
652 
653 				hif_write32_mb(scn, mem +
654 					       HOST_IE_ADDRESS_3, regval);
655 			}
656 			qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock);
657 		}
658 	} else {
659 		hif_pci_irq_enable(scn, ce_id);
660 	}
661 }
662 
663 /**
664  * ce_irq_disable() - disable copy engine IRQ
665  * @scn: struct hif_softc
666  * @ce_id: ce_id
667  *
668  * Return: N/A
669  */
670 void hif_ahb_irq_disable(struct hif_softc *scn, int ce_id)
671 {
672 	uint32_t regval;
673 	uint32_t reg_offset = 0;
674 	struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
675 	struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id];
676 	struct hif_target_info *tgt_info = &scn->target_info;
677 	void *mem = scn->mem_ce ? scn->mem_ce : scn->mem;
678 
679 	if (scn->per_ce_irq) {
680 		if (target_ce_conf->pipedir & PIPEDIR_OUT) {
681 			reg_offset = HOST_IE_ADDRESS;
682 			qdf_spin_lock_irqsave(&hif_state->irq_reg_lock);
683 			regval = hif_read32_mb(scn, mem + reg_offset);
684 			regval &= ~HOST_IE_REG1_CE_BIT(ce_id);
685 			hif_write32_mb(scn, mem + reg_offset, regval);
686 			qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock);
687 		}
688 		if (target_ce_conf->pipedir & PIPEDIR_IN) {
689 			reg_offset = HOST_IE_ADDRESS_2;
690 			qdf_spin_lock_irqsave(&hif_state->irq_reg_lock);
691 			regval = hif_read32_mb(scn, mem + reg_offset);
692 			regval &= ~HOST_IE_REG2_CE_BIT(ce_id);
693 			hif_write32_mb(scn, mem + reg_offset, regval);
694 			if (tgt_info->target_type == TARGET_TYPE_QCA8074 ||
695 			    tgt_info->target_type == TARGET_TYPE_QCA8074V2 ||
696 			    tgt_info->target_type == TARGET_TYPE_QCA9574 ||
697 			    tgt_info->target_type == TARGET_TYPE_QCA5332 ||
698 			    tgt_info->target_type == TARGET_TYPE_QCA5018 ||
699 			    tgt_info->target_type == TARGET_TYPE_QCA6018) {
700 				/* Disable destination ring interrupts for
701 				 * 8074, 8074V2, 6018 and 50xx
702 				 */
703 				regval = hif_read32_mb(scn, mem +
704 					HOST_IE_ADDRESS_3);
705 				regval &= ~HOST_IE_REG3_CE_BIT(ce_id);
706 
707 				hif_write32_mb(scn, mem +
708 					       HOST_IE_ADDRESS_3, regval);
709 			}
710 			qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock);
711 		}
712 	}
713 }
714 
715 void hif_ahb_exec_grp_irq_disable(struct hif_exec_context *hif_ext_group)
716 {
717 	int i;
718 
719 	qdf_spin_lock_irqsave(&hif_ext_group->irq_lock);
720 	if (hif_ext_group->irq_enabled) {
721 		for (i = 0; i < hif_ext_group->numirq; i++) {
722 			disable_irq_nosync(hif_ext_group->os_irq[i]);
723 		}
724 		hif_ext_group->irq_enabled = false;
725 	}
726 	qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock);
727 }
728 
729 void hif_ahb_exec_grp_irq_enable(struct hif_exec_context *hif_ext_group)
730 {
731 	int i;
732 
733 	qdf_spin_lock_irqsave(&hif_ext_group->irq_lock);
734 	if (hif_ext_group->irq_requested && !hif_ext_group->irq_enabled) {
735 		for (i = 0; i < hif_ext_group->numirq; i++) {
736 			enable_irq(hif_ext_group->os_irq[i]);
737 		}
738 		hif_ext_group->irq_enabled = true;
739 	}
740 	qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock);
741 }
742 
743 /**
744  * hif_ahb_needs_bmi() - return true if the soc needs bmi through the driver
745  * @scn: hif context
746  *
747  * Return: true if soc needs driver bmi otherwise false
748  */
749 bool hif_ahb_needs_bmi(struct hif_softc *scn)
750 {
751 	return !ce_srng_based(scn);
752 }
753 
754 /**
755  * hif_display_ahb_irq_regs() - prints the host interrupt enable (IE) regs
756  * @scn: hif context
757  *
758  * Return: None
759  */
760 
761 void hif_display_ahb_irq_regs(struct hif_softc *scn)
762 {
763 	uint32_t regval;
764 	void *mem = scn->mem_ce ? scn->mem_ce : scn->mem;
765 	struct hif_target_info *tgt_info = &scn->target_info;
766 
767 	if (tgt_info->target_type == TARGET_TYPE_QCN6122) {
768 		return;
769 	}
770 	if (scn->per_ce_irq) {
771 		regval = hif_read32_mb(scn, mem + HOST_IE_ADDRESS);
772 		hif_nofl_err("IRQ enable register value 0x%08x", regval);
773 
774 		regval = hif_read32_mb(scn, mem + HOST_IE_ADDRESS_2);
775 		hif_nofl_err("IRQ enable register 2 value 0x%08x", regval);
776 
777 		if (tgt_info->target_type == TARGET_TYPE_QCA8074 ||
778 		    tgt_info->target_type == TARGET_TYPE_QCA8074V2 ||
779 		    tgt_info->target_type == TARGET_TYPE_QCA9574 ||
780 		    tgt_info->target_type == TARGET_TYPE_QCA5332 ||
781 		    tgt_info->target_type == TARGET_TYPE_QCA5018 ||
782 		    tgt_info->target_type == TARGET_TYPE_QCA6018) {
783 			regval = hif_read32_mb(scn, mem +
784 					       HOST_IE_ADDRESS_3);
785 			hif_nofl_err("IRQ enable register 3 value 0x%08x",
786 				     regval);
787 		}
788 	}
789 }
790 
791 void hif_ahb_display_stats(struct hif_softc *scn)
792 {
793 	if (!scn) {
794 		hif_err("hif_scn null");
795 		return;
796 	}
797 	hif_display_ahb_irq_regs(scn);
798 	hif_display_ce_stats(scn);
799 }
800 
801 void hif_ahb_clear_stats(struct hif_softc *scn)
802 {
803 	struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
804 
805 	if (!hif_state) {
806 		hif_err("hif_state null");
807 		return;
808 	}
809 	hif_clear_ce_stats(hif_state);
810 }
811