1 /* 2 * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /** 20 * DOC: if_ahb.c 21 * 22 * c file for ahb specific implementations. 23 */ 24 25 #include "hif.h" 26 #include "target_type.h" 27 #include "hif_main.h" 28 #include "hif_debug.h" 29 #include "hif_io32.h" 30 #include "ce_main.h" 31 #include "ce_api.h" 32 #include "ce_tasklet.h" 33 #include "if_ahb.h" 34 #include "if_pci.h" 35 #include "ahb_api.h" 36 #include "pci_api.h" 37 #include "hif_napi.h" 38 #include "qal_vbus_dev.h" 39 40 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) 41 #define IRQF_DISABLED 0x00000020 42 #endif 43 44 #define HIF_IC_CE0_IRQ_OFFSET 4 45 #define HIF_IC_MAX_IRQ 52 46 47 static uint8_t ic_irqnum[HIF_IC_MAX_IRQ]; 48 /* integrated chip irq names */ 49 const char *ic_irqname[HIF_IC_MAX_IRQ] = { 50 "misc-pulse1", 51 "misc-latch", 52 "sw-exception", 53 "watchdog", 54 "ce0", 55 "ce1", 56 "ce2", 57 "ce3", 58 "ce4", 59 "ce5", 60 "ce6", 61 "ce7", 62 "ce8", 63 "ce9", 64 "ce10", 65 "ce11", 66 "host2wbm-desc-feed", 67 "host2reo-re-injection", 68 "host2reo-command", 69 "host2rxdma-monitor-ring3", 70 "host2rxdma-monitor-ring2", 71 "host2rxdma-monitor-ring1", 72 "reo2ost-exception", 73 "wbm2host-rx-release", 74 "reo2host-status", 75 "reo2host-destination-ring4", 76 "reo2host-destination-ring3", 77 "reo2host-destination-ring2", 78 "reo2host-destination-ring1", 79 "rxdma2host-monitor-destination-mac3", 80 "rxdma2host-monitor-destination-mac2", 81 "rxdma2host-monitor-destination-mac1", 82 "ppdu-end-interrupts-mac3", 83 "ppdu-end-interrupts-mac2", 84 "ppdu-end-interrupts-mac1", 85 "rxdma2host-monitor-status-ring-mac3", 86 "rxdma2host-monitor-status-ring-mac2", 87 "rxdma2host-monitor-status-ring-mac1", 88 "host2rxdma-host-buf-ring-mac3", 89 "host2rxdma-host-buf-ring-mac2", 90 "host2rxdma-host-buf-ring-mac1", 91 "rxdma2host-destination-ring-mac3", 92 "rxdma2host-destination-ring-mac2", 93 "rxdma2host-destination-ring-mac1", 94 "host2tcl-input-ring4", 95 "host2tcl-input-ring3", 96 "host2tcl-input-ring2", 97 "host2tcl-input-ring1", 98 "wbm2host-tx-completions-ring3", 99 "wbm2host-tx-completions-ring2", 100 "wbm2host-tx-completions-ring1", 101 "tcl2host-status-ring", 102 }; 103 104 /** 105 * hif_disable_isr() - disable isr 106 * 107 * This function disables isr and kills tasklets 108 * 109 * @hif_ctx: struct hif_softc 110 * 111 * Return: void 112 */ 113 void hif_ahb_disable_isr(struct hif_softc *scn) 114 { 115 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 116 117 hif_exec_kill(&scn->osc); 118 hif_nointrs(scn); 119 ce_tasklet_kill(scn); 120 tasklet_kill(&sc->intr_tq); 121 qdf_atomic_set(&scn->active_tasklet_cnt, 0); 122 qdf_atomic_set(&scn->active_grp_tasklet_cnt, 0); 123 } 124 125 /** 126 * hif_dump_registers() - dump bus debug registers 127 * @scn: struct hif_opaque_softc 128 * 129 * This function dumps hif bus debug registers 130 * 131 * Return: 0 for success or error code 132 */ 133 int hif_ahb_dump_registers(struct hif_softc *hif_ctx) 134 { 135 int status; 136 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 137 138 status = hif_dump_ce_registers(scn); 139 if (status) 140 HIF_ERROR("%s: Dump CE Registers Failed status %d", __func__, 141 status); 142 143 return 0; 144 } 145 146 /** 147 * hif_ahb_close() - hif_bus_close 148 * @scn: pointer to the hif context. 149 * 150 * This is a callback function for hif_bus_close. 151 * 152 * 153 * Return: n/a 154 */ 155 void hif_ahb_close(struct hif_softc *scn) 156 { 157 hif_ce_close(scn); 158 } 159 160 /** 161 * hif_bus_open() - hif_ahb open 162 * @hif_ctx: hif context 163 * @bus_type: bus type 164 * 165 * This is a callback function for hif_bus_open. 166 * 167 * Return: n/a 168 */ 169 QDF_STATUS hif_ahb_open(struct hif_softc *hif_ctx, enum qdf_bus_type bus_type) 170 { 171 172 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_ctx); 173 174 qdf_spinlock_create(&sc->irq_lock); 175 return hif_ce_open(hif_ctx); 176 } 177 178 /** 179 * hif_bus_configure() - Configure the bus 180 * @scn: pointer to the hif context. 181 * 182 * This function configure the ahb bus 183 * 184 * return: 0 for success. nonzero for failure. 185 */ 186 int hif_ahb_bus_configure(struct hif_softc *scn) 187 { 188 return hif_pci_bus_configure(scn); 189 } 190 191 /** 192 * hif_configure_msi_ahb - Configure MSI interrupts 193 * @sc : pointer to the hif context 194 * 195 * return: 0 for success. nonzero for failure. 196 */ 197 198 int hif_configure_msi_ahb(struct hif_pci_softc *sc) 199 { 200 return 0; 201 } 202 203 /** 204 * hif_ahb_configure_legacy_irq() - Configure Legacy IRQ 205 * @sc: pointer to the hif context. 206 * 207 * This function registers the irq handler and enables legacy interrupts 208 * 209 * return: 0 for success. nonzero for failure. 210 */ 211 int hif_ahb_configure_legacy_irq(struct hif_pci_softc *sc) 212 { 213 int ret = 0; 214 struct hif_softc *scn = HIF_GET_SOFTC(sc); 215 struct platform_device *pdev = (struct platform_device *)sc->pdev; 216 int irq = 0; 217 218 /* do not support MSI or MSI IRQ failed */ 219 tasklet_init(&sc->intr_tq, wlan_tasklet, (unsigned long)sc); 220 qal_vbus_get_irq((struct qdf_pfm_hndl *)pdev, "legacy", &irq); 221 if (irq < 0) { 222 dev_err(&pdev->dev, "Unable to get irq\n"); 223 ret = -1; 224 goto end; 225 } 226 ret = request_irq(irq, hif_pci_legacy_ce_interrupt_handler, 227 IRQF_DISABLED, "wlan_ahb", sc); 228 if (ret) { 229 dev_err(&pdev->dev, "ath_request_irq failed\n"); 230 ret = -1; 231 goto end; 232 } 233 sc->irq = irq; 234 235 /* Use Legacy PCI Interrupts */ 236 hif_write32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS | 237 PCIE_INTR_ENABLE_ADDRESS), 238 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 239 /* read once to flush */ 240 hif_read32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS | 241 PCIE_INTR_ENABLE_ADDRESS)); 242 243 end: 244 return ret; 245 } 246 247 int hif_ahb_configure_irq(struct hif_pci_softc *sc) 248 { 249 int ret = 0; 250 struct hif_softc *scn = HIF_GET_SOFTC(sc); 251 struct platform_device *pdev = (struct platform_device *)sc->pdev; 252 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 253 struct CE_attr *host_ce_conf = hif_state->host_ce_config; 254 int irq = 0; 255 int i; 256 257 /* configure per CE interrupts */ 258 for (i = 0; i < scn->ce_count; i++) { 259 if (host_ce_conf[i].flags & CE_ATTR_DISABLE_INTR) 260 continue; 261 qal_vbus_get_irq((struct qdf_pfm_hndl *)pdev, 262 ic_irqname[HIF_IC_CE0_IRQ_OFFSET + i], &irq); 263 ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i] = irq; 264 ret = request_irq(irq , 265 hif_ahb_interrupt_handler, 266 IRQF_TRIGGER_RISING, ic_irqname[HIF_IC_CE0_IRQ_OFFSET + i], 267 &hif_state->tasklets[i]); 268 if (ret) { 269 dev_err(&pdev->dev, "ath_request_irq failed\n"); 270 ret = -1; 271 goto end; 272 } 273 hif_ahb_irq_enable(scn, i); 274 } 275 276 end: 277 return ret; 278 } 279 280 int hif_ahb_configure_grp_irq(struct hif_softc *scn, 281 struct hif_exec_context *hif_ext_group) 282 { 283 int ret = 0; 284 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 285 struct platform_device *pdev = (struct platform_device *)sc->pdev; 286 int irq = 0; 287 int j; 288 289 /* configure external interrupts */ 290 hif_ext_group->irq_enable = &hif_ahb_exec_grp_irq_enable; 291 hif_ext_group->irq_disable = &hif_ahb_exec_grp_irq_disable; 292 hif_ext_group->work_complete = &hif_dummy_grp_done; 293 294 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 295 296 for (j = 0; j < hif_ext_group->numirq; j++) { 297 qal_vbus_get_irq((struct qdf_pfm_hndl *)pdev, 298 ic_irqname[hif_ext_group->irq[j]], &irq); 299 300 ic_irqnum[hif_ext_group->irq[j]] = irq; 301 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); 302 ret = request_irq(irq, hif_ext_group_interrupt_handler, 303 IRQF_TRIGGER_RISING, 304 ic_irqname[hif_ext_group->irq[j]], 305 hif_ext_group); 306 if (ret) { 307 dev_err(&pdev->dev, 308 "ath_request_irq failed\n"); 309 ret = -1; 310 goto end; 311 } 312 hif_ext_group->os_irq[j] = irq; 313 } 314 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 315 316 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 317 hif_ext_group->irq_requested = true; 318 319 end: 320 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 321 return ret; 322 } 323 324 void hif_ahb_deconfigure_grp_irq(struct hif_softc *scn) 325 { 326 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 327 struct hif_exec_context *hif_ext_group; 328 int i, j; 329 int irq = 0; 330 331 /* configure external interrupts */ 332 for (i = 0; i < hif_state->hif_num_extgroup; i++) { 333 hif_ext_group = hif_state->hif_ext_group[i]; 334 if (hif_ext_group->irq_requested == true) { 335 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 336 hif_ext_group->irq_requested = false; 337 for (j = 0; j < hif_ext_group->numirq; j++) { 338 irq = hif_ext_group->os_irq[j]; 339 irq_clear_status_flags(irq, 340 IRQ_DISABLE_UNLAZY); 341 free_irq(irq, hif_ext_group); 342 } 343 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 344 } 345 } 346 } 347 348 irqreturn_t hif_ahb_interrupt_handler(int irq, void *context) 349 { 350 struct ce_tasklet_entry *tasklet_entry = context; 351 return ce_dispatch_interrupt(tasklet_entry->ce_id, tasklet_entry); 352 } 353 354 /** 355 * hif_target_sync() : ensure the target is ready 356 * @scn: hif control structure 357 * 358 * Informs fw that we plan to use legacy interupts so that 359 * it can begin booting. Ensures that the fw finishes booting 360 * before continuing. Should be called before trying to write 361 * to the targets other registers for the first time. 362 * 363 * Return: none 364 */ 365 int hif_target_sync_ahb(struct hif_softc *scn) 366 { 367 int val = 0; 368 int limit = 0; 369 370 while (limit < 50) { 371 hif_write32_mb(scn, scn->mem + 372 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS), 373 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 374 qdf_mdelay(10); 375 val = hif_read32_mb(scn, scn->mem + 376 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS)); 377 if (val == 0) 378 break; 379 limit++; 380 } 381 hif_write32_mb(scn, scn->mem + 382 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS), 383 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 384 hif_write32_mb(scn, scn->mem + FW_INDICATOR_ADDRESS, FW_IND_HOST_READY); 385 if (HAS_FW_INDICATOR) { 386 int wait_limit = 500; 387 int fw_ind = 0; 388 389 while (1) { 390 fw_ind = hif_read32_mb(scn, scn->mem + 391 FW_INDICATOR_ADDRESS); 392 if (fw_ind & FW_IND_INITIALIZED) 393 break; 394 if (wait_limit-- < 0) 395 break; 396 hif_write32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS | 397 PCIE_INTR_ENABLE_ADDRESS), 398 PCIE_INTR_FIRMWARE_MASK); 399 qdf_mdelay(10); 400 } 401 if (wait_limit < 0) { 402 HIF_TRACE("%s: FW signal timed out", __func__); 403 return -EIO; 404 } 405 HIF_TRACE("%s: Got FW signal, retries = %x", __func__, 406 500-wait_limit); 407 } 408 409 return 0; 410 } 411 412 /** 413 * hif_disable_bus() - Disable the bus 414 * @scn : pointer to the hif context 415 * 416 * This function disables the bus and helds the target in reset state 417 * 418 * Return: none 419 */ 420 void hif_ahb_disable_bus(struct hif_softc *scn) 421 { 422 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 423 void __iomem *mem; 424 struct platform_device *pdev = (struct platform_device *)sc->pdev; 425 struct resource *memres = NULL; 426 int mem_pa_size = 0; 427 struct hif_target_info *tgt_info = NULL; 428 struct qdf_vbus_resource *vmres = NULL; 429 430 tgt_info = &scn->target_info; 431 /*Disable WIFI clock input*/ 432 if (sc->mem) { 433 qal_vbus_get_resource((struct qdf_pfm_hndl *)pdev, &vmres, 434 IORESOURCE_MEM, 0); 435 memres = (struct resource *)vmres; 436 if (!memres) { 437 HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", 438 __func__); 439 return; 440 } 441 mem_pa_size = memres->end - memres->start + 1; 442 443 /* Should not be executed on 8074 platform */ 444 if ((tgt_info->target_type != TARGET_TYPE_QCA8074) && 445 (tgt_info->target_type != TARGET_TYPE_QCA8074V2)) { 446 hif_ahb_clk_enable_disable(&pdev->dev, 0); 447 448 hif_ahb_device_reset(scn); 449 } 450 mem = (void __iomem *)sc->mem; 451 if (mem) { 452 devm_iounmap(&pdev->dev, mem); 453 devm_release_mem_region(&pdev->dev, scn->mem_pa, 454 mem_pa_size); 455 sc->mem = NULL; 456 } 457 } 458 scn->mem = NULL; 459 } 460 461 /** 462 * hif_enable_bus() - Enable the bus 463 * @dev: dev 464 * @bdev: bus dev 465 * @bid: bus id 466 * @type: bus type 467 * 468 * This function enables the radio bus by enabling necessary 469 * clocks and waits for the target to get ready to proceed futher 470 * 471 * Return: QDF_STATUS 472 */ 473 QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc, 474 struct device *dev, void *bdev, 475 const struct hif_bus_id *bid, 476 enum hif_enable_type type) 477 { 478 int ret = 0; 479 int hif_type; 480 int target_type; 481 const struct platform_device_id *id = (struct platform_device_id *)bid; 482 struct platform_device *pdev = bdev; 483 struct hif_target_info *tgt_info = NULL; 484 struct resource *memres = NULL; 485 void __iomem *mem = NULL; 486 uint32_t revision_id = 0; 487 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(ol_sc); 488 489 sc->pdev = (struct pci_dev *)pdev; 490 sc->dev = &pdev->dev; 491 sc->devid = id->driver_data; 492 493 ret = hif_get_device_type(id->driver_data, revision_id, 494 &hif_type, &target_type); 495 if (ret < 0) { 496 HIF_ERROR("%s: invalid device ret %d id %d revision_id %d", 497 __func__, ret, (int)id->driver_data, revision_id); 498 return QDF_STATUS_E_FAILURE; 499 } 500 501 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 502 if (!memres) { 503 HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", __func__); 504 return -EIO; 505 } 506 507 ret = dma_set_mask(dev, DMA_BIT_MASK(32)); 508 if (ret) { 509 HIF_INFO("ath: 32-bit DMA not available\n"); 510 goto err_cleanup1; 511 } 512 513 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) 514 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 515 #else 516 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); 517 #endif 518 if (ret) { 519 HIF_ERROR("%s: failed to set dma mask error = %d", 520 __func__, ret); 521 return ret; 522 } 523 524 /* Arrange for access to Target SoC registers. */ 525 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) 526 mem = devm_ioremap_resource(&pdev->dev, memres); 527 #else 528 mem = devm_request_and_ioremap(&pdev->dev, memres); 529 #endif 530 if (IS_ERR(mem)) { 531 HIF_INFO("ath: ioremap error\n"); 532 ret = PTR_ERR(mem); 533 goto err_cleanup1; 534 } 535 536 sc->mem = mem; 537 ol_sc->mem = mem; 538 ol_sc->mem_pa = memres->start; 539 540 tgt_info = hif_get_target_info_handle((struct hif_opaque_softc *)ol_sc); 541 542 tgt_info->target_type = target_type; 543 hif_register_tbl_attach(ol_sc, hif_type); 544 hif_target_register_tbl_attach(ol_sc, target_type); 545 546 /* QCA_WIFI_QCA8074_VP:Should not be executed on 8074 VP platform */ 547 if ((tgt_info->target_type != TARGET_TYPE_QCA8074) && 548 (tgt_info->target_type != TARGET_TYPE_QCA8074V2)) { 549 if (hif_ahb_enable_radio(sc, pdev, id) != 0) { 550 HIF_INFO("error in enabling soc\n"); 551 return -EIO; 552 } 553 554 if (hif_target_sync_ahb(ol_sc) < 0) { 555 ret = -EIO; 556 goto err_target_sync; 557 } 558 } 559 HIF_TRACE("%s: X - hif_type = 0x%x, target_type = 0x%x", 560 __func__, hif_type, target_type); 561 562 return QDF_STATUS_SUCCESS; 563 err_target_sync: 564 /* QCA_WIFI_QCA8074_VP:Should not be executed on 8074 VP platform */ 565 if ((tgt_info->target_type != TARGET_TYPE_QCA8074) && 566 (tgt_info->target_type != TARGET_TYPE_QCA8074V2)) { 567 HIF_INFO("Error: Disabling target\n"); 568 hif_ahb_disable_bus(ol_sc); 569 } 570 err_cleanup1: 571 return ret; 572 } 573 574 575 /** 576 * hif_reset_soc() - reset soc 577 * 578 * @hif_ctx: HIF context 579 * 580 * This function resets soc and helds the 581 * target in reset state 582 * 583 * Return: void 584 */ 585 /* Function to reset SoC */ 586 void hif_ahb_reset_soc(struct hif_softc *hif_ctx) 587 { 588 hif_ahb_device_reset(hif_ctx); 589 } 590 591 592 /** 593 * hif_nointrs() - disable IRQ 594 * 595 * @scn: struct hif_softc 596 * 597 * This function stops interrupt(s) 598 * 599 * Return: none 600 */ 601 void hif_ahb_nointrs(struct hif_softc *scn) 602 { 603 int i; 604 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 605 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 606 struct CE_attr *host_ce_conf = hif_state->host_ce_config; 607 608 ce_unregister_irq(hif_state, CE_ALL_BITMAP); 609 610 if (scn->request_irq_done == false) 611 return; 612 613 if (sc->num_msi_intrs > 0) { 614 /* MSI interrupt(s) */ 615 for (i = 0; i < sc->num_msi_intrs; i++) { 616 free_irq(sc->irq + i, sc); 617 } 618 sc->num_msi_intrs = 0; 619 } else { 620 if (!scn->per_ce_irq) { 621 free_irq(sc->irq, sc); 622 } else { 623 for (i = 0; i < scn->ce_count; i++) { 624 if (host_ce_conf[i].flags 625 & CE_ATTR_DISABLE_INTR) 626 continue; 627 628 free_irq(ic_irqnum[HIF_IC_CE0_IRQ_OFFSET + i], 629 &hif_state->tasklets[i]); 630 } 631 hif_ahb_deconfigure_grp_irq(scn); 632 } 633 } 634 scn->request_irq_done = false; 635 636 } 637 638 /** 639 * ce_irq_enable() - enable copy engine IRQ 640 * @scn: struct hif_softc 641 * @ce_id: ce_id 642 * 643 * This function enables the interrupt for the radio. 644 * 645 * Return: N/A 646 */ 647 void hif_ahb_irq_enable(struct hif_softc *scn, int ce_id) 648 { 649 uint32_t regval; 650 uint32_t reg_offset = 0; 651 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 652 struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id]; 653 struct hif_target_info *tgt_info = &scn->target_info; 654 655 if (scn->per_ce_irq) { 656 if (target_ce_conf->pipedir & PIPEDIR_OUT) { 657 reg_offset = HOST_IE_ADDRESS; 658 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 659 regval = hif_read32_mb(scn, scn->mem + reg_offset); 660 regval |= HOST_IE_REG1_CE_BIT(ce_id); 661 hif_write32_mb(scn, scn->mem + reg_offset, regval); 662 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 663 } 664 if (target_ce_conf->pipedir & PIPEDIR_IN) { 665 reg_offset = HOST_IE_ADDRESS_2; 666 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 667 regval = hif_read32_mb(scn, scn->mem + reg_offset); 668 regval |= HOST_IE_REG2_CE_BIT(ce_id); 669 hif_write32_mb(scn, scn->mem + reg_offset, regval); 670 if (tgt_info->target_type == TARGET_TYPE_QCA8074 || 671 tgt_info->target_type == TARGET_TYPE_QCA8074V2) { 672 /* Enable destination ring interrupts for 673 * 8074 and 8074V2 674 */ 675 regval = hif_read32_mb(scn, scn->mem + 676 HOST_IE_ADDRESS_3); 677 regval |= HOST_IE_REG3_CE_BIT(ce_id); 678 679 hif_write32_mb(scn, scn->mem + 680 HOST_IE_ADDRESS_3, regval); 681 } 682 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 683 } 684 } else { 685 hif_pci_irq_enable(scn, ce_id); 686 } 687 } 688 689 /** 690 * ce_irq_disable() - disable copy engine IRQ 691 * @scn: struct hif_softc 692 * @ce_id: ce_id 693 * 694 * Return: N/A 695 */ 696 void hif_ahb_irq_disable(struct hif_softc *scn, int ce_id) 697 { 698 uint32_t regval; 699 uint32_t reg_offset = 0; 700 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 701 struct CE_pipe_config *target_ce_conf = &hif_state->target_ce_config[ce_id]; 702 struct hif_target_info *tgt_info = &scn->target_info; 703 704 if (scn->per_ce_irq) { 705 if (target_ce_conf->pipedir & PIPEDIR_OUT) { 706 reg_offset = HOST_IE_ADDRESS; 707 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 708 regval = hif_read32_mb(scn, scn->mem + reg_offset); 709 regval &= ~HOST_IE_REG1_CE_BIT(ce_id); 710 hif_write32_mb(scn, scn->mem + reg_offset, regval); 711 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 712 } 713 if (target_ce_conf->pipedir & PIPEDIR_IN) { 714 reg_offset = HOST_IE_ADDRESS_2; 715 qdf_spin_lock_irqsave(&hif_state->irq_reg_lock); 716 regval = hif_read32_mb(scn, scn->mem + reg_offset); 717 regval &= ~HOST_IE_REG2_CE_BIT(ce_id); 718 hif_write32_mb(scn, scn->mem + reg_offset, regval); 719 if (tgt_info->target_type == TARGET_TYPE_QCA8074 || 720 tgt_info->target_type == TARGET_TYPE_QCA8074V2) { 721 /* Disable destination ring interrupts for 722 * 8074 and 8074V2 723 */ 724 regval = hif_read32_mb(scn, scn->mem + 725 HOST_IE_ADDRESS_3); 726 regval &= ~HOST_IE_REG3_CE_BIT(ce_id); 727 728 hif_write32_mb(scn, scn->mem + 729 HOST_IE_ADDRESS_3, regval); 730 } 731 qdf_spin_unlock_irqrestore(&hif_state->irq_reg_lock); 732 } 733 } 734 } 735 736 void hif_ahb_exec_grp_irq_disable(struct hif_exec_context *hif_ext_group) 737 { 738 int i; 739 740 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 741 if (hif_ext_group->irq_enabled) { 742 for (i = 0; i < hif_ext_group->numirq; i++) { 743 disable_irq_nosync(hif_ext_group->os_irq[i]); 744 } 745 hif_ext_group->irq_enabled = false; 746 } 747 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 748 } 749 750 void hif_ahb_exec_grp_irq_enable(struct hif_exec_context *hif_ext_group) 751 { 752 int i; 753 754 qdf_spin_lock_irqsave(&hif_ext_group->irq_lock); 755 if (!hif_ext_group->irq_enabled) { 756 for (i = 0; i < hif_ext_group->numirq; i++) { 757 enable_irq(hif_ext_group->os_irq[i]); 758 } 759 hif_ext_group->irq_enabled = true; 760 } 761 qdf_spin_unlock_irqrestore(&hif_ext_group->irq_lock); 762 } 763 764 /** 765 * hif_ahb_needs_bmi() - return true if the soc needs bmi through the driver 766 * @scn: hif context 767 * 768 * Return: true if soc needs driver bmi otherwise false 769 */ 770 bool hif_ahb_needs_bmi(struct hif_softc *scn) 771 { 772 return !ce_srng_based(scn); 773 } 774