1 /* 2 * Copyright (c) 2013-2017 The Linux Foundation. All rights reserved. 3 * 4 * Previously licensed under the ISC license by Qualcomm Atheros, Inc. 5 * 6 * 7 * Permission to use, copy, modify, and/or distribute this software for 8 * any purpose with or without fee is hereby granted, provided that the 9 * above copyright notice and this permission notice appear in all 10 * copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 13 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 14 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 15 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 16 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 17 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 18 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 19 * PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * This file was originally distributed by Qualcomm Atheros, Inc. 24 * under proprietary terms before Copyright ownership was assigned 25 * to the Linux Foundation. 26 */ 27 #ifndef _REGTABLE_SDIO_H_ 28 #define _REGTABLE_SDIO_H_ 29 30 #define MISSING 0 31 extern struct hif_sdio_softc *scn; 32 33 struct targetdef_s { 34 uint32_t d_RTC_SOC_BASE_ADDRESS; 35 uint32_t d_RTC_WMAC_BASE_ADDRESS; 36 uint32_t d_SYSTEM_SLEEP_OFFSET; 37 uint32_t d_WLAN_SYSTEM_SLEEP_OFFSET; 38 uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB; 39 uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK; 40 uint32_t d_CLOCK_CONTROL_OFFSET; 41 uint32_t d_CLOCK_CONTROL_SI0_CLK_MASK; 42 uint32_t d_RESET_CONTROL_OFFSET; 43 uint32_t d_RESET_CONTROL_MBOX_RST_MASK; 44 uint32_t d_RESET_CONTROL_SI0_RST_MASK; 45 uint32_t d_WLAN_RESET_CONTROL_OFFSET; 46 uint32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK; 47 uint32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK; 48 uint32_t d_GPIO_BASE_ADDRESS; 49 uint32_t d_GPIO_PIN0_OFFSET; 50 uint32_t d_GPIO_PIN1_OFFSET; 51 uint32_t d_GPIO_PIN0_CONFIG_MASK; 52 uint32_t d_GPIO_PIN1_CONFIG_MASK; 53 uint32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB; 54 uint32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK; 55 uint32_t d_SI_CONFIG_I2C_LSB; 56 uint32_t d_SI_CONFIG_I2C_MASK; 57 uint32_t d_SI_CONFIG_POS_SAMPLE_LSB; 58 uint32_t d_SI_CONFIG_POS_SAMPLE_MASK; 59 uint32_t d_SI_CONFIG_INACTIVE_CLK_LSB; 60 uint32_t d_SI_CONFIG_INACTIVE_CLK_MASK; 61 uint32_t d_SI_CONFIG_INACTIVE_DATA_LSB; 62 uint32_t d_SI_CONFIG_INACTIVE_DATA_MASK; 63 uint32_t d_SI_CONFIG_DIVIDER_LSB; 64 uint32_t d_SI_CONFIG_DIVIDER_MASK; 65 uint32_t d_SI_BASE_ADDRESS; 66 uint32_t d_SI_CONFIG_OFFSET; 67 uint32_t d_SI_TX_DATA0_OFFSET; 68 uint32_t d_SI_TX_DATA1_OFFSET; 69 uint32_t d_SI_RX_DATA0_OFFSET; 70 uint32_t d_SI_RX_DATA1_OFFSET; 71 uint32_t d_SI_CS_OFFSET; 72 uint32_t d_SI_CS_DONE_ERR_MASK; 73 uint32_t d_SI_CS_DONE_INT_MASK; 74 uint32_t d_SI_CS_START_LSB; 75 uint32_t d_SI_CS_START_MASK; 76 uint32_t d_SI_CS_RX_CNT_LSB; 77 uint32_t d_SI_CS_RX_CNT_MASK; 78 uint32_t d_SI_CS_TX_CNT_LSB; 79 uint32_t d_SI_CS_TX_CNT_MASK; 80 uint32_t d_BOARD_DATA_SZ; 81 uint32_t d_BOARD_EXT_DATA_SZ; 82 uint32_t d_MBOX_BASE_ADDRESS; 83 uint32_t d_LOCAL_SCRATCH_OFFSET; 84 uint32_t d_CPU_CLOCK_OFFSET; 85 uint32_t d_LPO_CAL_OFFSET; 86 uint32_t d_GPIO_PIN10_OFFSET; 87 uint32_t d_GPIO_PIN11_OFFSET; 88 uint32_t d_GPIO_PIN12_OFFSET; 89 uint32_t d_GPIO_PIN13_OFFSET; 90 uint32_t d_CLOCK_GPIO_OFFSET; 91 uint32_t d_CPU_CLOCK_STANDARD_LSB; 92 uint32_t d_CPU_CLOCK_STANDARD_MASK; 93 uint32_t d_LPO_CAL_ENABLE_LSB; 94 uint32_t d_LPO_CAL_ENABLE_MASK; 95 uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB; 96 uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK; 97 uint32_t d_ANALOG_INTF_BASE_ADDRESS; 98 uint32_t d_WLAN_MAC_BASE_ADDRESS; 99 uint32_t d_FW_INDICATOR_ADDRESS; 100 uint32_t d_DRAM_BASE_ADDRESS; 101 uint32_t d_SOC_CORE_BASE_ADDRESS; 102 uint32_t d_CORE_CTRL_ADDRESS; 103 uint32_t d_MSI_NUM_REQUEST; 104 uint32_t d_MSI_ASSIGN_FW; 105 uint32_t d_CORE_CTRL_CPU_INTR_MASK; 106 uint32_t d_SR_WR_INDEX_ADDRESS; 107 uint32_t d_DST_WATERMARK_ADDRESS; 108 109 /* htt_rx.c */ 110 uint32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK; 111 uint32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB; 112 uint32_t d_RX_MPDU_START_0_RETRY_LSB; 113 uint32_t d_RX_MPDU_START_0_RETRY_MASK; 114 uint32_t d_RX_MPDU_START_0_SEQ_NUM_MASK; 115 uint32_t d_RX_MPDU_START_0_SEQ_NUM_LSB; 116 uint32_t d_RX_MPDU_START_2_PN_47_32_LSB; 117 uint32_t d_RX_MPDU_START_2_PN_47_32_MASK; 118 uint32_t d_RX_MPDU_START_2_TID_LSB; 119 uint32_t d_RX_MPDU_START_2_TID_MASK; 120 uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK; 121 uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB; 122 uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK; 123 uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB; 124 uint32_t d_RX_MSDU_END_4_LAST_MSDU_MASK; 125 uint32_t d_RX_MSDU_END_4_LAST_MSDU_LSB; 126 uint32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK; 127 uint32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB; 128 uint32_t d_RX_ATTENTION_0_FRAGMENT_MASK; 129 uint32_t d_RX_ATTENTION_0_FRAGMENT_LSB; 130 uint32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK; 131 uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK; 132 uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB; 133 uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK; 134 uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB; 135 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET; 136 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK; 137 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB; 138 uint32_t d_RX_MPDU_START_0_ENCRYPTED_MASK; 139 uint32_t d_RX_MPDU_START_0_ENCRYPTED_LSB; 140 uint32_t d_RX_ATTENTION_0_MORE_DATA_MASK; 141 uint32_t d_RX_ATTENTION_0_MSDU_DONE_MASK; 142 uint32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK; 143 /* end */ 144 145 /* PLL start */ 146 uint32_t d_EFUSE_OFFSET; 147 uint32_t d_EFUSE_XTAL_SEL_MSB; 148 uint32_t d_EFUSE_XTAL_SEL_LSB; 149 uint32_t d_EFUSE_XTAL_SEL_MASK; 150 uint32_t d_BB_PLL_CONFIG_OFFSET; 151 uint32_t d_BB_PLL_CONFIG_OUTDIV_MSB; 152 uint32_t d_BB_PLL_CONFIG_OUTDIV_LSB; 153 uint32_t d_BB_PLL_CONFIG_OUTDIV_MASK; 154 uint32_t d_BB_PLL_CONFIG_FRAC_MSB; 155 uint32_t d_BB_PLL_CONFIG_FRAC_LSB; 156 uint32_t d_BB_PLL_CONFIG_FRAC_MASK; 157 uint32_t d_WLAN_PLL_SETTLE_TIME_MSB; 158 uint32_t d_WLAN_PLL_SETTLE_TIME_LSB; 159 uint32_t d_WLAN_PLL_SETTLE_TIME_MASK; 160 uint32_t d_WLAN_PLL_SETTLE_OFFSET; 161 uint32_t d_WLAN_PLL_SETTLE_SW_MASK; 162 uint32_t d_WLAN_PLL_SETTLE_RSTMASK; 163 uint32_t d_WLAN_PLL_SETTLE_RESET; 164 uint32_t d_WLAN_PLL_CONTROL_NOPWD_MSB; 165 uint32_t d_WLAN_PLL_CONTROL_NOPWD_LSB; 166 uint32_t d_WLAN_PLL_CONTROL_NOPWD_MASK; 167 uint32_t d_WLAN_PLL_CONTROL_BYPASS_MSB; 168 uint32_t d_WLAN_PLL_CONTROL_BYPASS_LSB; 169 uint32_t d_WLAN_PLL_CONTROL_BYPASS_MASK; 170 uint32_t d_WLAN_PLL_CONTROL_BYPASS_RESET; 171 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB; 172 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB; 173 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK; 174 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET; 175 uint32_t d_WLAN_PLL_CONTROL_REFDIV_MSB; 176 uint32_t d_WLAN_PLL_CONTROL_REFDIV_LSB; 177 uint32_t d_WLAN_PLL_CONTROL_REFDIV_MASK; 178 uint32_t d_WLAN_PLL_CONTROL_REFDIV_RESET; 179 uint32_t d_WLAN_PLL_CONTROL_DIV_MSB; 180 uint32_t d_WLAN_PLL_CONTROL_DIV_LSB; 181 uint32_t d_WLAN_PLL_CONTROL_DIV_MASK; 182 uint32_t d_WLAN_PLL_CONTROL_DIV_RESET; 183 uint32_t d_WLAN_PLL_CONTROL_OFFSET; 184 uint32_t d_WLAN_PLL_CONTROL_SW_MASK; 185 uint32_t d_WLAN_PLL_CONTROL_RSTMASK; 186 uint32_t d_WLAN_PLL_CONTROL_RESET; 187 uint32_t d_SOC_CORE_CLK_CTRL_OFFSET; 188 uint32_t d_SOC_CORE_CLK_CTRL_DIV_MSB; 189 uint32_t d_SOC_CORE_CLK_CTRL_DIV_LSB; 190 uint32_t d_SOC_CORE_CLK_CTRL_DIV_MASK; 191 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB; 192 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB; 193 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK; 194 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET; 195 uint32_t d_RTC_SYNC_STATUS_OFFSET; 196 uint32_t d_SOC_CPU_CLOCK_OFFSET; 197 uint32_t d_SOC_CPU_CLOCK_STANDARD_MSB; 198 uint32_t d_SOC_CPU_CLOCK_STANDARD_LSB; 199 uint32_t d_SOC_CPU_CLOCK_STANDARD_MASK; 200 /* PLL end */ 201 202 uint32_t d_SOC_POWER_REG_OFFSET; 203 uint32_t d_SOC_RESET_CONTROL_ADDRESS; 204 uint32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK; 205 uint32_t d_CPU_INTR_ADDRESS; 206 uint32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS; 207 uint32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK; 208 209 /* chip id start */ 210 uint32_t d_SOC_CHIP_ID_ADDRESS; 211 uint32_t d_SOC_CHIP_ID_VERSION_MASK; 212 uint32_t d_SOC_CHIP_ID_VERSION_LSB; 213 uint32_t d_SOC_CHIP_ID_REVISION_MASK; 214 uint32_t d_SOC_CHIP_ID_REVISION_LSB; 215 /* chip id end */ 216 217 uint32_t d_A_SOC_CORE_SCRATCH_0_ADDRESS; 218 uint32_t d_A_SOC_CORE_SCRATCH_1_ADDRESS; 219 uint32_t d_A_SOC_CORE_SCRATCH_2_ADDRESS; 220 uint32_t d_A_SOC_CORE_SCRATCH_3_ADDRESS; 221 uint32_t d_A_SOC_CORE_SCRATCH_4_ADDRESS; 222 uint32_t d_A_SOC_CORE_SCRATCH_5_ADDRESS; 223 uint32_t d_A_SOC_CORE_SCRATCH_6_ADDRESS; 224 uint32_t d_A_SOC_CORE_SCRATCH_7_ADDRESS; 225 uint32_t d_A_SOC_CORE_SPARE_0_REGISTER; 226 uint32_t d_A_SOC_CORE_SPARE_1_REGISTER; 227 228 uint32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET; 229 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB; 230 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB; 231 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK; 232 uint32_t d_WLAN_DEBUG_CONTROL_OFFSET; 233 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB; 234 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB; 235 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK; 236 uint32_t d_WLAN_DEBUG_OUT_OFFSET; 237 uint32_t d_WLAN_DEBUG_OUT_DATA_MSB; 238 uint32_t d_WLAN_DEBUG_OUT_DATA_LSB; 239 uint32_t d_WLAN_DEBUG_OUT_DATA_MASK; 240 uint32_t d_AMBA_DEBUG_BUS_OFFSET; 241 uint32_t d_AMBA_DEBUG_BUS_SEL_MSB; 242 uint32_t d_AMBA_DEBUG_BUS_SEL_LSB; 243 uint32_t d_AMBA_DEBUG_BUS_SEL_MASK; 244 245 #ifdef QCA_WIFI_3_0_ADRASTEA 246 uint32_t d_Q6_ENABLE_REGISTER_0; 247 uint32_t d_Q6_ENABLE_REGISTER_1; 248 uint32_t d_Q6_CAUSE_REGISTER_0; 249 uint32_t d_Q6_CAUSE_REGISTER_1; 250 uint32_t d_Q6_CLEAR_REGISTER_0; 251 uint32_t d_Q6_CLEAR_REGISTER_1; 252 #endif 253 }; 254 255 #define A_SOC_CORE_SPARE_0_REGISTER \ 256 (scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER) 257 #define A_SOC_CORE_SCRATCH_0_ADDRESS \ 258 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS) 259 #define A_SOC_CORE_SCRATCH_1_ADDRESS \ 260 (scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS) 261 #define A_SOC_CORE_SCRATCH_2_ADDRESS \ 262 (scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS) 263 #define A_SOC_CORE_SCRATCH_3_ADDRESS \ 264 (scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS) 265 #define A_SOC_CORE_SCRATCH_4_ADDRESS \ 266 (scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS) 267 #define A_SOC_CORE_SCRATCH_5_ADDRESS \ 268 (scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS) 269 #define A_SOC_CORE_SCRATCH_6_ADDRESS \ 270 (scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS) 271 #define A_SOC_CORE_SCRATCH_7_ADDRESS \ 272 (scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS) 273 #define RTC_SOC_BASE_ADDRESS (scn->targetdef->d_RTC_SOC_BASE_ADDRESS) 274 #define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS) 275 #define SYSTEM_SLEEP_OFFSET (scn->targetdef->d_SYSTEM_SLEEP_OFFSET) 276 #define WLAN_SYSTEM_SLEEP_OFFSET \ 277 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET) 278 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB \ 279 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB) 280 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK \ 281 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK) 282 #define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET) 283 #define CLOCK_CONTROL_SI0_CLK_MASK \ 284 (scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK) 285 #define RESET_CONTROL_OFFSET (scn->targetdef->d_RESET_CONTROL_OFFSET) 286 #define RESET_CONTROL_MBOX_RST_MASK \ 287 (scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK) 288 #define RESET_CONTROL_SI0_RST_MASK \ 289 (scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK) 290 #define WLAN_RESET_CONTROL_OFFSET \ 291 (scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET) 292 #define WLAN_RESET_CONTROL_COLD_RST_MASK \ 293 (scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK) 294 #define WLAN_RESET_CONTROL_WARM_RST_MASK \ 295 (scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK) 296 #define GPIO_BASE_ADDRESS (scn->targetdef->d_GPIO_BASE_ADDRESS) 297 #define GPIO_PIN0_OFFSET (scn->targetdef->d_GPIO_PIN0_OFFSET) 298 #define GPIO_PIN1_OFFSET (scn->targetdef->d_GPIO_PIN1_OFFSET) 299 #define GPIO_PIN0_CONFIG_MASK (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK) 300 #define GPIO_PIN1_CONFIG_MASK (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK) 301 #define A_SOC_CORE_SCRATCH_0 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0) 302 #define SI_CONFIG_BIDIR_OD_DATA_LSB \ 303 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB) 304 #define SI_CONFIG_BIDIR_OD_DATA_MASK \ 305 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK) 306 #define SI_CONFIG_I2C_LSB (scn->targetdef->d_SI_CONFIG_I2C_LSB) 307 #define SI_CONFIG_I2C_MASK \ 308 (scn->targetdef->d_SI_CONFIG_I2C_MASK) 309 #define SI_CONFIG_POS_SAMPLE_LSB \ 310 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB) 311 #define SI_CONFIG_POS_SAMPLE_MASK \ 312 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK) 313 #define SI_CONFIG_INACTIVE_CLK_LSB \ 314 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB) 315 #define SI_CONFIG_INACTIVE_CLK_MASK \ 316 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK) 317 #define SI_CONFIG_INACTIVE_DATA_LSB \ 318 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB) 319 #define SI_CONFIG_INACTIVE_DATA_MASK \ 320 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK) 321 #define SI_CONFIG_DIVIDER_LSB (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB) 322 #define SI_CONFIG_DIVIDER_MASK (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK) 323 #define SI_BASE_ADDRESS (scn->targetdef->d_SI_BASE_ADDRESS) 324 #define SI_CONFIG_OFFSET (scn->targetdef->d_SI_CONFIG_OFFSET) 325 #define SI_TX_DATA0_OFFSET (scn->targetdef->d_SI_TX_DATA0_OFFSET) 326 #define SI_TX_DATA1_OFFSET (scn->targetdef->d_SI_TX_DATA1_OFFSET) 327 #define SI_RX_DATA0_OFFSET (scn->targetdef->d_SI_RX_DATA0_OFFSET) 328 #define SI_RX_DATA1_OFFSET (scn->targetdef->d_SI_RX_DATA1_OFFSET) 329 #define SI_CS_OFFSET (scn->targetdef->d_SI_CS_OFFSET) 330 #define SI_CS_DONE_ERR_MASK (scn->targetdef->d_SI_CS_DONE_ERR_MASK) 331 #define SI_CS_DONE_INT_MASK (scn->targetdef->d_SI_CS_DONE_INT_MASK) 332 #define SI_CS_START_LSB (scn->targetdef->d_SI_CS_START_LSB) 333 #define SI_CS_START_MASK (scn->targetdef->d_SI_CS_START_MASK) 334 #define SI_CS_RX_CNT_LSB (scn->targetdef->d_SI_CS_RX_CNT_LSB) 335 #define SI_CS_RX_CNT_MASK (scn->targetdef->d_SI_CS_RX_CNT_MASK) 336 #define SI_CS_TX_CNT_LSB (scn->targetdef->d_SI_CS_TX_CNT_LSB) 337 #define SI_CS_TX_CNT_MASK (scn->targetdef->d_SI_CS_TX_CNT_MASK) 338 #define EEPROM_SZ (scn->targetdef->d_BOARD_DATA_SZ) 339 #define EEPROM_EXT_SZ (scn->targetdef->d_BOARD_EXT_DATA_SZ) 340 #define MBOX_BASE_ADDRESS (scn->targetdef->d_MBOX_BASE_ADDRESS) 341 #define LOCAL_SCRATCH_OFFSET (scn->targetdef->d_LOCAL_SCRATCH_OFFSET) 342 #define CPU_CLOCK_OFFSET (scn->targetdef->d_CPU_CLOCK_OFFSET) 343 #define LPO_CAL_OFFSET (scn->targetdef->d_LPO_CAL_OFFSET) 344 #define GPIO_PIN10_OFFSET (scn->targetdef->d_GPIO_PIN10_OFFSET) 345 #define GPIO_PIN11_OFFSET (scn->targetdef->d_GPIO_PIN11_OFFSET) 346 #define GPIO_PIN12_OFFSET (scn->targetdef->d_GPIO_PIN12_OFFSET) 347 #define GPIO_PIN13_OFFSET (scn->targetdef->d_GPIO_PIN13_OFFSET) 348 #define CLOCK_GPIO_OFFSET (scn->targetdef->d_CLOCK_GPIO_OFFSET) 349 #define CPU_CLOCK_STANDARD_LSB (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB) 350 #define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK) 351 #define LPO_CAL_ENABLE_LSB (scn->targetdef->d_LPO_CAL_ENABLE_LSB) 352 #define LPO_CAL_ENABLE_MASK (scn->targetdef->d_LPO_CAL_ENABLE_MASK) 353 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \ 354 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB) 355 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \ 356 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 357 #define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS) 358 #define WLAN_MAC_BASE_ADDRESS (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS) 359 #define FW_INDICATOR_ADDRESS (scn->targetdef->d_FW_INDICATOR_ADDRESS) 360 #define DRAM_BASE_ADDRESS (scn->targetdef->d_DRAM_BASE_ADDRESS) 361 #define SOC_CORE_BASE_ADDRESS (scn->targetdef->d_SOC_CORE_BASE_ADDRESS) 362 #define CORE_CTRL_ADDRESS (scn->targetdef->d_CORE_CTRL_ADDRESS) 363 #define CORE_CTRL_CPU_INTR_MASK (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK) 364 #define SOC_RESET_CONTROL_ADDRESS (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS) 365 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \ 366 (scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK) 367 #define CPU_INTR_ADDRESS (scn->targetdef->d_CPU_INTR_ADDRESS) 368 #define SOC_LF_TIMER_CONTROL0_ADDRESS \ 369 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS) 370 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \ 371 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK) 372 373 374 #define CHIP_ID_ADDRESS (scn->targetdef->d_SOC_CHIP_ID_ADDRESS) 375 #define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK) 376 #define SOC_CHIP_ID_REVISION_LSB (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB) 377 #define SOC_CHIP_ID_VERSION_MASK (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK) 378 #define SOC_CHIP_ID_VERSION_LSB (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB) 379 #define CHIP_ID_REVISION_GET(x) \ 380 (((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB) 381 #define CHIP_ID_VERSION_GET(x) \ 382 (((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB) 383 384 /* misc */ 385 #define SR_WR_INDEX_ADDRESS (scn->targetdef->d_SR_WR_INDEX_ADDRESS) 386 #define DST_WATERMARK_ADDRESS (scn->targetdef->d_DST_WATERMARK_ADDRESS) 387 #define SOC_POWER_REG_OFFSET (scn->targetdef->d_SOC_POWER_REG_OFFSET) 388 /* end */ 389 390 /* htt_rx.c */ 391 #define RX_MSDU_END_4_FIRST_MSDU_MASK \ 392 (pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_MASK) 393 #define RX_MSDU_END_4_FIRST_MSDU_LSB \ 394 (pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_LSB) 395 #define RX_MPDU_START_0_RETRY_LSB \ 396 (pdev->targetdef->d_RX_MPDU_START_0_RETRY_LSB) 397 #define RX_MPDU_START_0_RETRY_MASK \ 398 (pdev->targetdef->d_RX_MPDU_START_0_RETRY_MASK) 399 #define RX_MPDU_START_0_SEQ_NUM_MASK \ 400 (pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_MASK) 401 #define RX_MPDU_START_0_SEQ_NUM_LSB \ 402 (pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_LSB) 403 #define RX_MPDU_START_2_PN_47_32_LSB \ 404 (pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_LSB) 405 #define RX_MPDU_START_2_PN_47_32_MASK \ 406 (pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_MASK) 407 #define RX_MPDU_START_2_TID_LSB \ 408 (pdev->targetdef->d_RX_MPDU_START_2_TID_LSB) 409 #define RX_MPDU_START_2_TID_MASK \ 410 (pdev->targetdef->d_RX_MPDU_START_2_TID_MASK) 411 #define RX_MSDU_END_1_KEY_ID_OCT_MASK \ 412 (pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_MASK) 413 #define RX_MSDU_END_1_KEY_ID_OCT_LSB \ 414 (pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_LSB) 415 #define RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK \ 416 (pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK) 417 #define RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB \ 418 (pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB) 419 #define RX_MSDU_END_4_LAST_MSDU_MASK \ 420 (pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_MASK) 421 #define RX_MSDU_END_4_LAST_MSDU_LSB \ 422 (pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_LSB) 423 #define RX_ATTENTION_0_MCAST_BCAST_MASK \ 424 (pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_MASK) 425 #define RX_ATTENTION_0_MCAST_BCAST_LSB \ 426 (pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_LSB) 427 #define RX_ATTENTION_0_FRAGMENT_MASK \ 428 (pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_MASK) 429 #define RX_ATTENTION_0_FRAGMENT_LSB \ 430 (pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_LSB) 431 #define RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK \ 432 (pdev->targetdef->d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK) 433 #define RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK \ 434 (pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK) 435 #define RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB \ 436 (pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB) 437 #define RX_MSDU_START_0_MSDU_LENGTH_MASK \ 438 (pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_MASK) 439 #define RX_MSDU_START_0_MSDU_LENGTH_LSB \ 440 (pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_LSB) 441 #define RX_MSDU_START_2_DECAP_FORMAT_OFFSET \ 442 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET) 443 #define RX_MSDU_START_2_DECAP_FORMAT_MASK \ 444 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_MASK) 445 #define RX_MSDU_START_2_DECAP_FORMAT_LSB \ 446 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_LSB) 447 #define RX_MPDU_START_0_ENCRYPTED_MASK \ 448 (pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_MASK) 449 #define RX_MPDU_START_0_ENCRYPTED_LSB \ 450 (pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_LSB) 451 #define RX_ATTENTION_0_MORE_DATA_MASK \ 452 (pdev->targetdef->d_RX_ATTENTION_0_MORE_DATA_MASK) 453 #define RX_ATTENTION_0_MSDU_DONE_MASK \ 454 (pdev->targetdef->d_RX_ATTENTION_0_MSDU_DONE_MASK) 455 #define RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK \ 456 (pdev->targetdef->d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK) 457 /* end */ 458 459 /* copy_engine.c */ 460 /* end */ 461 /* PLL start */ 462 #define EFUSE_OFFSET (scn->targetdef->d_EFUSE_OFFSET) 463 #define EFUSE_XTAL_SEL_MSB (scn->targetdef->d_EFUSE_XTAL_SEL_MSB) 464 #define EFUSE_XTAL_SEL_LSB (scn->targetdef->d_EFUSE_XTAL_SEL_LSB) 465 #define EFUSE_XTAL_SEL_MASK (scn->targetdef->d_EFUSE_XTAL_SEL_MASK) 466 #define BB_PLL_CONFIG_OFFSET (scn->targetdef->d_BB_PLL_CONFIG_OFFSET) 467 #define BB_PLL_CONFIG_OUTDIV_MSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB) 468 #define BB_PLL_CONFIG_OUTDIV_LSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB) 469 #define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK) 470 #define BB_PLL_CONFIG_FRAC_MSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB) 471 #define BB_PLL_CONFIG_FRAC_LSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB) 472 #define BB_PLL_CONFIG_FRAC_MASK (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK) 473 #define WLAN_PLL_SETTLE_TIME_MSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB) 474 #define WLAN_PLL_SETTLE_TIME_LSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB) 475 #define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK) 476 #define WLAN_PLL_SETTLE_OFFSET (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET) 477 #define WLAN_PLL_SETTLE_SW_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK) 478 #define WLAN_PLL_SETTLE_RSTMASK (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK) 479 #define WLAN_PLL_SETTLE_RESET (scn->targetdef->d_WLAN_PLL_SETTLE_RESET) 480 #define WLAN_PLL_CONTROL_NOPWD_MSB \ 481 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB) 482 #define WLAN_PLL_CONTROL_NOPWD_LSB \ 483 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB) 484 #define WLAN_PLL_CONTROL_NOPWD_MASK \ 485 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK) 486 #define WLAN_PLL_CONTROL_BYPASS_MSB \ 487 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB) 488 #define WLAN_PLL_CONTROL_BYPASS_LSB \ 489 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB) 490 #define WLAN_PLL_CONTROL_BYPASS_MASK \ 491 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK) 492 #define WLAN_PLL_CONTROL_BYPASS_RESET \ 493 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET) 494 #define WLAN_PLL_CONTROL_CLK_SEL_MSB \ 495 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB) 496 #define WLAN_PLL_CONTROL_CLK_SEL_LSB \ 497 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB) 498 #define WLAN_PLL_CONTROL_CLK_SEL_MASK \ 499 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK) 500 #define WLAN_PLL_CONTROL_CLK_SEL_RESET \ 501 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET) 502 #define WLAN_PLL_CONTROL_REFDIV_MSB \ 503 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB) 504 #define WLAN_PLL_CONTROL_REFDIV_LSB \ 505 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB) 506 #define WLAN_PLL_CONTROL_REFDIV_MASK \ 507 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK) 508 #define WLAN_PLL_CONTROL_REFDIV_RESET \ 509 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET) 510 #define WLAN_PLL_CONTROL_DIV_MSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB) 511 #define WLAN_PLL_CONTROL_DIV_LSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB) 512 #define WLAN_PLL_CONTROL_DIV_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK) 513 #define WLAN_PLL_CONTROL_DIV_RESET \ 514 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET) 515 #define WLAN_PLL_CONTROL_OFFSET (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET) 516 #define WLAN_PLL_CONTROL_SW_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK) 517 #define WLAN_PLL_CONTROL_RSTMASK (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK) 518 #define WLAN_PLL_CONTROL_RESET (scn->targetdef->d_WLAN_PLL_CONTROL_RESET) 519 #define SOC_CORE_CLK_CTRL_OFFSET (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET) 520 #define SOC_CORE_CLK_CTRL_DIV_MSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB) 521 #define SOC_CORE_CLK_CTRL_DIV_LSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB) 522 #define SOC_CORE_CLK_CTRL_DIV_MASK \ 523 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK) 524 #define RTC_SYNC_STATUS_PLL_CHANGING_MSB \ 525 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB) 526 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB \ 527 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB) 528 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK \ 529 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK) 530 #define RTC_SYNC_STATUS_PLL_CHANGING_RESET \ 531 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET) 532 #define RTC_SYNC_STATUS_OFFSET (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET) 533 #define SOC_CPU_CLOCK_OFFSET (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET) 534 #define SOC_CPU_CLOCK_STANDARD_MSB \ 535 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB) 536 #define SOC_CPU_CLOCK_STANDARD_LSB \ 537 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB) 538 #define SOC_CPU_CLOCK_STANDARD_MASK \ 539 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK) 540 /* PLL end */ 541 542 /* SET macros */ 543 #define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \ 544 (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \ 545 WLAN_SYSTEM_SLEEP_DISABLE_MASK) 546 #define SI_CONFIG_BIDIR_OD_DATA_SET(x) \ 547 (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) 548 #define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) 549 #define SI_CONFIG_POS_SAMPLE_SET(x) \ 550 (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) 551 #define SI_CONFIG_INACTIVE_CLK_SET(x) \ 552 (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) 553 #define SI_CONFIG_INACTIVE_DATA_SET(x) \ 554 (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) 555 #define SI_CONFIG_DIVIDER_SET(x) \ 556 (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) 557 #define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) 558 #define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) 559 #define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) 560 #define LPO_CAL_ENABLE_SET(x) \ 561 (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) 562 #define CPU_CLOCK_STANDARD_SET(x) \ 563 (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) 564 #define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \ 565 (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 566 /* copy_engine.c */ 567 /* end */ 568 /* PLL start */ 569 #define EFUSE_XTAL_SEL_GET(x) \ 570 (((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB) 571 #define EFUSE_XTAL_SEL_SET(x) \ 572 (((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK) 573 #define BB_PLL_CONFIG_OUTDIV_GET(x) \ 574 (((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB) 575 #define BB_PLL_CONFIG_OUTDIV_SET(x) \ 576 (((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK) 577 #define BB_PLL_CONFIG_FRAC_GET(x) \ 578 (((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB) 579 #define BB_PLL_CONFIG_FRAC_SET(x) \ 580 (((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK) 581 #define WLAN_PLL_SETTLE_TIME_GET(x) \ 582 (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB) 583 #define WLAN_PLL_SETTLE_TIME_SET(x) \ 584 (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK) 585 #define WLAN_PLL_CONTROL_NOPWD_GET(x) \ 586 (((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB) 587 #define WLAN_PLL_CONTROL_NOPWD_SET(x) \ 588 (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK) 589 #define WLAN_PLL_CONTROL_BYPASS_GET(x) \ 590 (((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB) 591 #define WLAN_PLL_CONTROL_BYPASS_SET(x) \ 592 (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK) 593 #define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \ 594 (((x) & WLAN_PLL_CONTROL_CLK_SEL_MASK) >> WLAN_PLL_CONTROL_CLK_SEL_LSB) 595 #define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \ 596 (((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & WLAN_PLL_CONTROL_CLK_SEL_MASK) 597 #define WLAN_PLL_CONTROL_REFDIV_GET(x) \ 598 (((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB) 599 #define WLAN_PLL_CONTROL_REFDIV_SET(x) \ 600 (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK) 601 #define WLAN_PLL_CONTROL_DIV_GET(x) \ 602 (((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB) 603 #define WLAN_PLL_CONTROL_DIV_SET(x) \ 604 (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK) 605 #define SOC_CORE_CLK_CTRL_DIV_GET(x) \ 606 (((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB) 607 #define SOC_CORE_CLK_CTRL_DIV_SET(x) \ 608 (((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK) 609 #define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \ 610 (((x) & RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \ 611 RTC_SYNC_STATUS_PLL_CHANGING_LSB) 612 #define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \ 613 (((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \ 614 RTC_SYNC_STATUS_PLL_CHANGING_MASK) 615 #define SOC_CPU_CLOCK_STANDARD_GET(x) \ 616 (((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB) 617 #define SOC_CPU_CLOCK_STANDARD_SET(x) \ 618 (((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK) 619 /* PLL end */ 620 621 #ifdef QCA_WIFI_3_0_ADRASTEA 622 #define Q6_ENABLE_REGISTER_0 \ 623 (scn->targetdef->d_Q6_ENABLE_REGISTER_0) 624 #define Q6_ENABLE_REGISTER_1 \ 625 (scn->targetdef->d_Q6_ENABLE_REGISTER_1) 626 #define Q6_CAUSE_REGISTER_0 \ 627 (scn->targetdef->d_Q6_CAUSE_REGISTER_0) 628 #define Q6_CAUSE_REGISTER_1 \ 629 (scn->targetdef->d_Q6_CAUSE_REGISTER_1) 630 #define Q6_CLEAR_REGISTER_0 \ 631 (scn->targetdef->d_Q6_CLEAR_REGISTER_0) 632 #define Q6_CLEAR_REGISTER_1 \ 633 (scn->targetdef->d_Q6_CLEAR_REGISTER_1) 634 #endif 635 636 struct hostdef_s { 637 uint32_t d_INT_STATUS_ENABLE_ERROR_LSB; 638 uint32_t d_INT_STATUS_ENABLE_ERROR_MASK; 639 uint32_t d_INT_STATUS_ENABLE_CPU_LSB; 640 uint32_t d_INT_STATUS_ENABLE_CPU_MASK; 641 uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB; 642 uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK; 643 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB; 644 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK; 645 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB; 646 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK; 647 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB; 648 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK; 649 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB; 650 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK; 651 uint32_t d_INT_STATUS_ENABLE_ADDRESS; 652 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB; 653 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK; 654 uint32_t d_HOST_INT_STATUS_ADDRESS; 655 uint32_t d_CPU_INT_STATUS_ADDRESS; 656 uint32_t d_ERROR_INT_STATUS_ADDRESS; 657 uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK; 658 uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB; 659 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK; 660 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB; 661 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK; 662 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB; 663 uint32_t d_COUNT_DEC_ADDRESS; 664 uint32_t d_HOST_INT_STATUS_CPU_MASK; 665 uint32_t d_HOST_INT_STATUS_CPU_LSB; 666 uint32_t d_HOST_INT_STATUS_ERROR_MASK; 667 uint32_t d_HOST_INT_STATUS_ERROR_LSB; 668 uint32_t d_HOST_INT_STATUS_COUNTER_MASK; 669 uint32_t d_HOST_INT_STATUS_COUNTER_LSB; 670 uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS; 671 uint32_t d_WINDOW_DATA_ADDRESS; 672 uint32_t d_WINDOW_READ_ADDR_ADDRESS; 673 uint32_t d_WINDOW_WRITE_ADDR_ADDRESS; 674 uint32_t d_SOC_GLOBAL_RESET_ADDRESS; 675 uint32_t d_RTC_STATE_ADDRESS; 676 uint32_t d_RTC_STATE_COLD_RESET_MASK; 677 uint32_t d_RTC_STATE_V_MASK; 678 uint32_t d_RTC_STATE_V_LSB; 679 uint32_t d_FW_IND_EVENT_PENDING; 680 uint32_t d_FW_IND_INITIALIZED; 681 uint32_t d_FW_IND_HELPER; 682 uint32_t d_RTC_STATE_V_ON; 683 #if defined(SDIO_3_0) 684 uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK; 685 uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB; 686 #endif 687 uint32_t d_MSI_MAGIC_ADR_ADDRESS; 688 uint32_t d_MSI_MAGIC_ADDRESS; 689 uint32_t d_ENABLE_MSI; 690 uint32_t d_MUX_ID_MASK; 691 uint32_t d_TRANSACTION_ID_MASK; 692 uint32_t d_DESC_DATA_FLAG_MASK; 693 }; 694 #define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK) 695 #define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK) 696 #define TRANSACTION_ID_MASK (scn->hostdef->d_TRANSACTION_ID_MASK) 697 #define ENABLE_MSI (scn->hostdef->d_ENABLE_MSI) 698 #define INT_STATUS_ENABLE_ERROR_LSB \ 699 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB) 700 #define INT_STATUS_ENABLE_ERROR_MASK \ 701 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK) 702 #define INT_STATUS_ENABLE_CPU_LSB (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB) 703 #define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK) 704 #define INT_STATUS_ENABLE_COUNTER_LSB \ 705 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB) 706 #define INT_STATUS_ENABLE_COUNTER_MASK \ 707 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK) 708 #define INT_STATUS_ENABLE_MBOX_DATA_LSB \ 709 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB) 710 #define INT_STATUS_ENABLE_MBOX_DATA_MASK \ 711 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK) 712 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \ 713 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) 714 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \ 715 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 716 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB \ 717 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) 718 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \ 719 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 720 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB \ 721 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB) 722 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK \ 723 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK) 724 #define INT_STATUS_ENABLE_ADDRESS \ 725 (scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS) 726 #define CPU_INT_STATUS_ENABLE_BIT_LSB \ 727 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB) 728 #define CPU_INT_STATUS_ENABLE_BIT_MASK \ 729 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK) 730 #define HOST_INT_STATUS_ADDRESS (scn->hostdef->d_HOST_INT_STATUS_ADDRESS) 731 #define CPU_INT_STATUS_ADDRESS (scn->hostdef->d_CPU_INT_STATUS_ADDRESS) 732 #define ERROR_INT_STATUS_ADDRESS (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS) 733 #define ERROR_INT_STATUS_WAKEUP_MASK \ 734 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK) 735 #define ERROR_INT_STATUS_WAKEUP_LSB \ 736 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB) 737 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \ 738 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK) 739 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \ 740 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 741 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK \ 742 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK) 743 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB \ 744 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB) 745 #define COUNT_DEC_ADDRESS (scn->hostdef->d_COUNT_DEC_ADDRESS) 746 #define HOST_INT_STATUS_CPU_MASK (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK) 747 #define HOST_INT_STATUS_CPU_LSB (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB) 748 #define HOST_INT_STATUS_ERROR_MASK (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK) 749 #define HOST_INT_STATUS_ERROR_LSB (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB) 750 #define HOST_INT_STATUS_COUNTER_MASK \ 751 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK) 752 #define HOST_INT_STATUS_COUNTER_LSB \ 753 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB) 754 #define RX_LOOKAHEAD_VALID_ADDRESS (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS) 755 #define WINDOW_DATA_ADDRESS (scn->hostdef->d_WINDOW_DATA_ADDRESS) 756 #define WINDOW_READ_ADDR_ADDRESS (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS) 757 #define WINDOW_WRITE_ADDR_ADDRESS (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS) 758 #define SOC_GLOBAL_RESET_ADDRESS (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS) 759 #define RTC_STATE_ADDRESS (scn->hostdef->d_RTC_STATE_ADDRESS) 760 #define RTC_STATE_COLD_RESET_MASK (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK) 761 #define RTC_STATE_V_MASK (scn->hostdef->d_RTC_STATE_V_MASK) 762 #define RTC_STATE_V_LSB (scn->hostdef->d_RTC_STATE_V_LSB) 763 #define FW_IND_EVENT_PENDING (scn->hostdef->d_FW_IND_EVENT_PENDING) 764 #define FW_IND_INITIALIZED (scn->hostdef->d_FW_IND_INITIALIZED) 765 #define FW_IND_HELPER (scn->hostdef->d_FW_IND_HELPER) 766 #define RTC_STATE_V_ON (scn->hostdef->d_RTC_STATE_V_ON) 767 #if defined(SDIO_3_0) 768 #define HOST_INT_STATUS_MBOX_DATA_MASK \ 769 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK) 770 #define HOST_INT_STATUS_MBOX_DATA_LSB \ 771 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB) 772 #endif 773 774 #if !defined(MSI_MAGIC_ADR_ADDRESS) 775 #define MSI_MAGIC_ADR_ADDRESS 0 776 #define MSI_MAGIC_ADDRESS 0 777 #endif 778 779 /* SET/GET macros */ 780 #define INT_STATUS_ENABLE_ERROR_SET(x) \ 781 (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) 782 #define INT_STATUS_ENABLE_CPU_SET(x) \ 783 (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) 784 #define INT_STATUS_ENABLE_COUNTER_SET(x) \ 785 (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \ 786 INT_STATUS_ENABLE_COUNTER_MASK) 787 #define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \ 788 (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \ 789 INT_STATUS_ENABLE_MBOX_DATA_MASK) 790 #define CPU_INT_STATUS_ENABLE_BIT_SET(x) \ 791 (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \ 792 CPU_INT_STATUS_ENABLE_BIT_MASK) 793 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \ 794 (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \ 795 ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 796 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) \ 797 (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \ 798 ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 799 #define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \ 800 (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \ 801 COUNTER_INT_STATUS_ENABLE_BIT_MASK) 802 #define ERROR_INT_STATUS_WAKEUP_GET(x) \ 803 (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \ 804 ERROR_INT_STATUS_WAKEUP_LSB) 805 #define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \ 806 (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \ 807 ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 808 #define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \ 809 (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \ 810 ERROR_INT_STATUS_TX_OVERFLOW_LSB) 811 #define HOST_INT_STATUS_CPU_GET(x) \ 812 (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) 813 #define HOST_INT_STATUS_ERROR_GET(x) \ 814 (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) 815 #define HOST_INT_STATUS_COUNTER_GET(x) \ 816 (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) 817 #define RTC_STATE_V_GET(x) \ 818 (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 819 #if defined(SDIO_3_0) 820 #define HOST_INT_STATUS_MBOX_DATA_GET(x) \ 821 (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \ 822 HOST_INT_STATUS_MBOX_DATA_LSB) 823 #endif 824 825 #define INVALID_REG_LOC_DUMMY_DATA 0xAA 826 827 #define AR6320_CORE_CLK_DIV_ADDR 0x403fa8 828 #define AR6320_CPU_PLL_INIT_DONE_ADDR 0x403fd0 829 #define AR6320_CPU_SPEED_ADDR 0x403fa4 830 #define AR6320V2_CORE_CLK_DIV_ADDR 0x403fd8 831 #define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0 832 #define AR6320V2_CPU_SPEED_ADDR 0x403fd4 833 #define AR6320V3_CORE_CLK_DIV_ADDR 0x404028 834 #define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020 835 #define AR6320V3_CPU_SPEED_ADDR 0x404024 836 837 enum a_refclk_speed_t { 838 SOC_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */ 839 SOC_REFCLK_48_MHZ = 0, 840 SOC_REFCLK_19_2_MHZ = 1, 841 SOC_REFCLK_24_MHZ = 2, 842 SOC_REFCLK_26_MHZ = 3, 843 SOC_REFCLK_37_4_MHZ = 4, 844 SOC_REFCLK_38_4_MHZ = 5, 845 SOC_REFCLK_40_MHZ = 6, 846 SOC_REFCLK_52_MHZ = 7, 847 }; 848 849 #define A_REFCLK_UNKNOWN SOC_REFCLK_UNKNOWN 850 #define A_REFCLK_48_MHZ SOC_REFCLK_48_MHZ 851 #define A_REFCLK_19_2_MHZ SOC_REFCLK_19_2_MHZ 852 #define A_REFCLK_24_MHZ SOC_REFCLK_24_MHZ 853 #define A_REFCLK_26_MHZ SOC_REFCLK_26_MHZ 854 #define A_REFCLK_37_4_MHZ SOC_REFCLK_37_4_MHZ 855 #define A_REFCLK_38_4_MHZ SOC_REFCLK_38_4_MHZ 856 #define A_REFCLK_40_MHZ SOC_REFCLK_40_MHZ 857 #define A_REFCLK_52_MHZ SOC_REFCLK_52_MHZ 858 859 #define TARGET_CPU_FREQ 176000000 860 861 struct wlan_pll_s { 862 uint32_t refdiv; 863 uint32_t div; 864 uint32_t rnfrac; 865 uint32_t outdiv; 866 }; 867 868 struct cmnos_clock_s { 869 enum a_refclk_speed_t refclk_speed; 870 uint32_t refclk_hz; 871 uint32_t pll_settling_time; /* 50us */ 872 struct wlan_pll_s wlan_pll; 873 }; 874 875 struct tgt_reg_section { 876 uint32_t start_addr; 877 uint32_t end_addr; 878 }; 879 880 881 struct tgt_reg_table { 882 const struct tgt_reg_section *section; 883 uint32_t section_size; 884 }; 885 #endif /* _REGTABLE_SDIO_H_ */ 886