1 /* 2 * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _REGTABLE_SDIO_H_ 20 #define _REGTABLE_SDIO_H_ 21 22 #define MISSING 0 23 extern struct hif_sdio_softc *scn; 24 25 struct targetdef_s { 26 uint32_t d_RTC_SOC_BASE_ADDRESS; 27 uint32_t d_RTC_WMAC_BASE_ADDRESS; 28 uint32_t d_SYSTEM_SLEEP_OFFSET; 29 uint32_t d_WLAN_SYSTEM_SLEEP_OFFSET; 30 uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB; 31 uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK; 32 uint32_t d_CLOCK_CONTROL_OFFSET; 33 uint32_t d_CLOCK_CONTROL_SI0_CLK_MASK; 34 uint32_t d_RESET_CONTROL_OFFSET; 35 uint32_t d_RESET_CONTROL_MBOX_RST_MASK; 36 uint32_t d_RESET_CONTROL_SI0_RST_MASK; 37 uint32_t d_WLAN_RESET_CONTROL_OFFSET; 38 uint32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK; 39 uint32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK; 40 uint32_t d_GPIO_BASE_ADDRESS; 41 uint32_t d_GPIO_PIN0_OFFSET; 42 uint32_t d_GPIO_PIN1_OFFSET; 43 uint32_t d_GPIO_PIN0_CONFIG_MASK; 44 uint32_t d_GPIO_PIN1_CONFIG_MASK; 45 uint32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB; 46 uint32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK; 47 uint32_t d_SI_CONFIG_I2C_LSB; 48 uint32_t d_SI_CONFIG_I2C_MASK; 49 uint32_t d_SI_CONFIG_POS_SAMPLE_LSB; 50 uint32_t d_SI_CONFIG_POS_SAMPLE_MASK; 51 uint32_t d_SI_CONFIG_INACTIVE_CLK_LSB; 52 uint32_t d_SI_CONFIG_INACTIVE_CLK_MASK; 53 uint32_t d_SI_CONFIG_INACTIVE_DATA_LSB; 54 uint32_t d_SI_CONFIG_INACTIVE_DATA_MASK; 55 uint32_t d_SI_CONFIG_DIVIDER_LSB; 56 uint32_t d_SI_CONFIG_DIVIDER_MASK; 57 uint32_t d_SI_BASE_ADDRESS; 58 uint32_t d_SI_CONFIG_OFFSET; 59 uint32_t d_SI_TX_DATA0_OFFSET; 60 uint32_t d_SI_TX_DATA1_OFFSET; 61 uint32_t d_SI_RX_DATA0_OFFSET; 62 uint32_t d_SI_RX_DATA1_OFFSET; 63 uint32_t d_SI_CS_OFFSET; 64 uint32_t d_SI_CS_DONE_ERR_MASK; 65 uint32_t d_SI_CS_DONE_INT_MASK; 66 uint32_t d_SI_CS_START_LSB; 67 uint32_t d_SI_CS_START_MASK; 68 uint32_t d_SI_CS_RX_CNT_LSB; 69 uint32_t d_SI_CS_RX_CNT_MASK; 70 uint32_t d_SI_CS_TX_CNT_LSB; 71 uint32_t d_SI_CS_TX_CNT_MASK; 72 uint32_t d_BOARD_DATA_SZ; 73 uint32_t d_BOARD_EXT_DATA_SZ; 74 uint32_t d_MBOX_BASE_ADDRESS; 75 uint32_t d_LOCAL_SCRATCH_OFFSET; 76 uint32_t d_CPU_CLOCK_OFFSET; 77 uint32_t d_LPO_CAL_OFFSET; 78 uint32_t d_GPIO_PIN10_OFFSET; 79 uint32_t d_GPIO_PIN11_OFFSET; 80 uint32_t d_GPIO_PIN12_OFFSET; 81 uint32_t d_GPIO_PIN13_OFFSET; 82 uint32_t d_CLOCK_GPIO_OFFSET; 83 uint32_t d_CPU_CLOCK_STANDARD_LSB; 84 uint32_t d_CPU_CLOCK_STANDARD_MASK; 85 uint32_t d_LPO_CAL_ENABLE_LSB; 86 uint32_t d_LPO_CAL_ENABLE_MASK; 87 uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB; 88 uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK; 89 uint32_t d_ANALOG_INTF_BASE_ADDRESS; 90 uint32_t d_WLAN_MAC_BASE_ADDRESS; 91 uint32_t d_FW_INDICATOR_ADDRESS; 92 uint32_t d_DRAM_BASE_ADDRESS; 93 uint32_t d_SOC_CORE_BASE_ADDRESS; 94 uint32_t d_CORE_CTRL_ADDRESS; 95 uint32_t d_MSI_NUM_REQUEST; 96 uint32_t d_MSI_ASSIGN_FW; 97 uint32_t d_CORE_CTRL_CPU_INTR_MASK; 98 uint32_t d_SR_WR_INDEX_ADDRESS; 99 uint32_t d_DST_WATERMARK_ADDRESS; 100 101 /* htt_rx.c */ 102 uint32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK; 103 uint32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB; 104 uint32_t d_RX_MPDU_START_0_RETRY_LSB; 105 uint32_t d_RX_MPDU_START_0_RETRY_MASK; 106 uint32_t d_RX_MPDU_START_0_SEQ_NUM_MASK; 107 uint32_t d_RX_MPDU_START_0_SEQ_NUM_LSB; 108 uint32_t d_RX_MPDU_START_2_PN_47_32_LSB; 109 uint32_t d_RX_MPDU_START_2_PN_47_32_MASK; 110 uint32_t d_RX_MPDU_START_2_TID_LSB; 111 uint32_t d_RX_MPDU_START_2_TID_MASK; 112 uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK; 113 uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB; 114 uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK; 115 uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB; 116 uint32_t d_RX_MSDU_END_4_LAST_MSDU_MASK; 117 uint32_t d_RX_MSDU_END_4_LAST_MSDU_LSB; 118 uint32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK; 119 uint32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB; 120 uint32_t d_RX_ATTENTION_0_FRAGMENT_MASK; 121 uint32_t d_RX_ATTENTION_0_FRAGMENT_LSB; 122 uint32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK; 123 uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK; 124 uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB; 125 uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK; 126 uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB; 127 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET; 128 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK; 129 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB; 130 uint32_t d_RX_MPDU_START_0_ENCRYPTED_MASK; 131 uint32_t d_RX_MPDU_START_0_ENCRYPTED_LSB; 132 uint32_t d_RX_ATTENTION_0_MORE_DATA_MASK; 133 uint32_t d_RX_ATTENTION_0_MSDU_DONE_MASK; 134 uint32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK; 135 /* end */ 136 137 /* PLL start */ 138 uint32_t d_EFUSE_OFFSET; 139 uint32_t d_EFUSE_XTAL_SEL_MSB; 140 uint32_t d_EFUSE_XTAL_SEL_LSB; 141 uint32_t d_EFUSE_XTAL_SEL_MASK; 142 uint32_t d_BB_PLL_CONFIG_OFFSET; 143 uint32_t d_BB_PLL_CONFIG_OUTDIV_MSB; 144 uint32_t d_BB_PLL_CONFIG_OUTDIV_LSB; 145 uint32_t d_BB_PLL_CONFIG_OUTDIV_MASK; 146 uint32_t d_BB_PLL_CONFIG_FRAC_MSB; 147 uint32_t d_BB_PLL_CONFIG_FRAC_LSB; 148 uint32_t d_BB_PLL_CONFIG_FRAC_MASK; 149 uint32_t d_WLAN_PLL_SETTLE_TIME_MSB; 150 uint32_t d_WLAN_PLL_SETTLE_TIME_LSB; 151 uint32_t d_WLAN_PLL_SETTLE_TIME_MASK; 152 uint32_t d_WLAN_PLL_SETTLE_OFFSET; 153 uint32_t d_WLAN_PLL_SETTLE_SW_MASK; 154 uint32_t d_WLAN_PLL_SETTLE_RSTMASK; 155 uint32_t d_WLAN_PLL_SETTLE_RESET; 156 uint32_t d_WLAN_PLL_CONTROL_NOPWD_MSB; 157 uint32_t d_WLAN_PLL_CONTROL_NOPWD_LSB; 158 uint32_t d_WLAN_PLL_CONTROL_NOPWD_MASK; 159 uint32_t d_WLAN_PLL_CONTROL_BYPASS_MSB; 160 uint32_t d_WLAN_PLL_CONTROL_BYPASS_LSB; 161 uint32_t d_WLAN_PLL_CONTROL_BYPASS_MASK; 162 uint32_t d_WLAN_PLL_CONTROL_BYPASS_RESET; 163 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB; 164 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB; 165 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK; 166 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET; 167 uint32_t d_WLAN_PLL_CONTROL_REFDIV_MSB; 168 uint32_t d_WLAN_PLL_CONTROL_REFDIV_LSB; 169 uint32_t d_WLAN_PLL_CONTROL_REFDIV_MASK; 170 uint32_t d_WLAN_PLL_CONTROL_REFDIV_RESET; 171 uint32_t d_WLAN_PLL_CONTROL_DIV_MSB; 172 uint32_t d_WLAN_PLL_CONTROL_DIV_LSB; 173 uint32_t d_WLAN_PLL_CONTROL_DIV_MASK; 174 uint32_t d_WLAN_PLL_CONTROL_DIV_RESET; 175 uint32_t d_WLAN_PLL_CONTROL_OFFSET; 176 uint32_t d_WLAN_PLL_CONTROL_SW_MASK; 177 uint32_t d_WLAN_PLL_CONTROL_RSTMASK; 178 uint32_t d_WLAN_PLL_CONTROL_RESET; 179 uint32_t d_SOC_CORE_CLK_CTRL_OFFSET; 180 uint32_t d_SOC_CORE_CLK_CTRL_DIV_MSB; 181 uint32_t d_SOC_CORE_CLK_CTRL_DIV_LSB; 182 uint32_t d_SOC_CORE_CLK_CTRL_DIV_MASK; 183 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB; 184 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB; 185 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK; 186 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET; 187 uint32_t d_RTC_SYNC_STATUS_OFFSET; 188 uint32_t d_SOC_CPU_CLOCK_OFFSET; 189 uint32_t d_SOC_CPU_CLOCK_STANDARD_MSB; 190 uint32_t d_SOC_CPU_CLOCK_STANDARD_LSB; 191 uint32_t d_SOC_CPU_CLOCK_STANDARD_MASK; 192 /* PLL end */ 193 194 uint32_t d_SOC_POWER_REG_OFFSET; 195 uint32_t d_SOC_RESET_CONTROL_ADDRESS; 196 uint32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK; 197 uint32_t d_CPU_INTR_ADDRESS; 198 uint32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS; 199 uint32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK; 200 uint32_t d_SOC_LF_TIMER_STATUS0_ADDRESS; 201 202 /* chip id start */ 203 uint32_t d_SOC_CHIP_ID_ADDRESS; 204 uint32_t d_SOC_CHIP_ID_VERSION_MASK; 205 uint32_t d_SOC_CHIP_ID_VERSION_LSB; 206 uint32_t d_SOC_CHIP_ID_REVISION_MASK; 207 uint32_t d_SOC_CHIP_ID_REVISION_LSB; 208 /* chip id end */ 209 210 uint32_t d_A_SOC_CORE_SCRATCH_0_ADDRESS; 211 uint32_t d_A_SOC_CORE_SCRATCH_1_ADDRESS; 212 uint32_t d_A_SOC_CORE_SCRATCH_2_ADDRESS; 213 uint32_t d_A_SOC_CORE_SCRATCH_3_ADDRESS; 214 uint32_t d_A_SOC_CORE_SCRATCH_4_ADDRESS; 215 uint32_t d_A_SOC_CORE_SCRATCH_5_ADDRESS; 216 uint32_t d_A_SOC_CORE_SCRATCH_6_ADDRESS; 217 uint32_t d_A_SOC_CORE_SCRATCH_7_ADDRESS; 218 uint32_t d_A_SOC_CORE_SPARE_0_REGISTER; 219 uint32_t d_A_SOC_CORE_SPARE_1_REGISTER; 220 221 uint32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET; 222 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB; 223 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB; 224 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK; 225 uint32_t d_WLAN_DEBUG_CONTROL_OFFSET; 226 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB; 227 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB; 228 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK; 229 uint32_t d_WLAN_DEBUG_OUT_OFFSET; 230 uint32_t d_WLAN_DEBUG_OUT_DATA_MSB; 231 uint32_t d_WLAN_DEBUG_OUT_DATA_LSB; 232 uint32_t d_WLAN_DEBUG_OUT_DATA_MASK; 233 uint32_t d_AMBA_DEBUG_BUS_OFFSET; 234 uint32_t d_AMBA_DEBUG_BUS_SEL_MSB; 235 uint32_t d_AMBA_DEBUG_BUS_SEL_LSB; 236 uint32_t d_AMBA_DEBUG_BUS_SEL_MASK; 237 238 #ifdef QCA_WIFI_3_0_ADRASTEA 239 uint32_t d_Q6_ENABLE_REGISTER_0; 240 uint32_t d_Q6_ENABLE_REGISTER_1; 241 uint32_t d_Q6_CAUSE_REGISTER_0; 242 uint32_t d_Q6_CAUSE_REGISTER_1; 243 uint32_t d_Q6_CLEAR_REGISTER_0; 244 uint32_t d_Q6_CLEAR_REGISTER_1; 245 #endif 246 }; 247 248 #define A_SOC_CORE_SPARE_0_REGISTER \ 249 (scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER) 250 #define A_SOC_CORE_SCRATCH_0_ADDRESS \ 251 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS) 252 #define A_SOC_CORE_SCRATCH_1_ADDRESS \ 253 (scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS) 254 #define A_SOC_CORE_SCRATCH_2_ADDRESS \ 255 (scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS) 256 #define A_SOC_CORE_SCRATCH_3_ADDRESS \ 257 (scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS) 258 #define A_SOC_CORE_SCRATCH_4_ADDRESS \ 259 (scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS) 260 #define A_SOC_CORE_SCRATCH_5_ADDRESS \ 261 (scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS) 262 #define A_SOC_CORE_SCRATCH_6_ADDRESS \ 263 (scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS) 264 #define A_SOC_CORE_SCRATCH_7_ADDRESS \ 265 (scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS) 266 #define RTC_SOC_BASE_ADDRESS (scn->targetdef->d_RTC_SOC_BASE_ADDRESS) 267 #define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS) 268 #define SYSTEM_SLEEP_OFFSET (scn->targetdef->d_SYSTEM_SLEEP_OFFSET) 269 #define WLAN_SYSTEM_SLEEP_OFFSET \ 270 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET) 271 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB \ 272 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB) 273 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK \ 274 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK) 275 #define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET) 276 #define CLOCK_CONTROL_SI0_CLK_MASK \ 277 (scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK) 278 #define RESET_CONTROL_OFFSET (scn->targetdef->d_RESET_CONTROL_OFFSET) 279 #define RESET_CONTROL_MBOX_RST_MASK \ 280 (scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK) 281 #define RESET_CONTROL_SI0_RST_MASK \ 282 (scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK) 283 #define WLAN_RESET_CONTROL_OFFSET \ 284 (scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET) 285 #define WLAN_RESET_CONTROL_COLD_RST_MASK \ 286 (scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK) 287 #define WLAN_RESET_CONTROL_WARM_RST_MASK \ 288 (scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK) 289 #define GPIO_BASE_ADDRESS (scn->targetdef->d_GPIO_BASE_ADDRESS) 290 #define GPIO_PIN0_OFFSET (scn->targetdef->d_GPIO_PIN0_OFFSET) 291 #define GPIO_PIN1_OFFSET (scn->targetdef->d_GPIO_PIN1_OFFSET) 292 #define GPIO_PIN0_CONFIG_MASK (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK) 293 #define GPIO_PIN1_CONFIG_MASK (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK) 294 #define A_SOC_CORE_SCRATCH_0 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0) 295 #define SI_CONFIG_BIDIR_OD_DATA_LSB \ 296 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB) 297 #define SI_CONFIG_BIDIR_OD_DATA_MASK \ 298 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK) 299 #define SI_CONFIG_I2C_LSB (scn->targetdef->d_SI_CONFIG_I2C_LSB) 300 #define SI_CONFIG_I2C_MASK \ 301 (scn->targetdef->d_SI_CONFIG_I2C_MASK) 302 #define SI_CONFIG_POS_SAMPLE_LSB \ 303 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB) 304 #define SI_CONFIG_POS_SAMPLE_MASK \ 305 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK) 306 #define SI_CONFIG_INACTIVE_CLK_LSB \ 307 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB) 308 #define SI_CONFIG_INACTIVE_CLK_MASK \ 309 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK) 310 #define SI_CONFIG_INACTIVE_DATA_LSB \ 311 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB) 312 #define SI_CONFIG_INACTIVE_DATA_MASK \ 313 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK) 314 #define SI_CONFIG_DIVIDER_LSB (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB) 315 #define SI_CONFIG_DIVIDER_MASK (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK) 316 #define SI_BASE_ADDRESS (scn->targetdef->d_SI_BASE_ADDRESS) 317 #define SI_CONFIG_OFFSET (scn->targetdef->d_SI_CONFIG_OFFSET) 318 #define SI_TX_DATA0_OFFSET (scn->targetdef->d_SI_TX_DATA0_OFFSET) 319 #define SI_TX_DATA1_OFFSET (scn->targetdef->d_SI_TX_DATA1_OFFSET) 320 #define SI_RX_DATA0_OFFSET (scn->targetdef->d_SI_RX_DATA0_OFFSET) 321 #define SI_RX_DATA1_OFFSET (scn->targetdef->d_SI_RX_DATA1_OFFSET) 322 #define SI_CS_OFFSET (scn->targetdef->d_SI_CS_OFFSET) 323 #define SI_CS_DONE_ERR_MASK (scn->targetdef->d_SI_CS_DONE_ERR_MASK) 324 #define SI_CS_DONE_INT_MASK (scn->targetdef->d_SI_CS_DONE_INT_MASK) 325 #define SI_CS_START_LSB (scn->targetdef->d_SI_CS_START_LSB) 326 #define SI_CS_START_MASK (scn->targetdef->d_SI_CS_START_MASK) 327 #define SI_CS_RX_CNT_LSB (scn->targetdef->d_SI_CS_RX_CNT_LSB) 328 #define SI_CS_RX_CNT_MASK (scn->targetdef->d_SI_CS_RX_CNT_MASK) 329 #define SI_CS_TX_CNT_LSB (scn->targetdef->d_SI_CS_TX_CNT_LSB) 330 #define SI_CS_TX_CNT_MASK (scn->targetdef->d_SI_CS_TX_CNT_MASK) 331 #define EEPROM_SZ (scn->targetdef->d_BOARD_DATA_SZ) 332 #define EEPROM_EXT_SZ (scn->targetdef->d_BOARD_EXT_DATA_SZ) 333 #define MBOX_BASE_ADDRESS (scn->targetdef->d_MBOX_BASE_ADDRESS) 334 #define LOCAL_SCRATCH_OFFSET (scn->targetdef->d_LOCAL_SCRATCH_OFFSET) 335 #define CPU_CLOCK_OFFSET (scn->targetdef->d_CPU_CLOCK_OFFSET) 336 #define LPO_CAL_OFFSET (scn->targetdef->d_LPO_CAL_OFFSET) 337 #define GPIO_PIN10_OFFSET (scn->targetdef->d_GPIO_PIN10_OFFSET) 338 #define GPIO_PIN11_OFFSET (scn->targetdef->d_GPIO_PIN11_OFFSET) 339 #define GPIO_PIN12_OFFSET (scn->targetdef->d_GPIO_PIN12_OFFSET) 340 #define GPIO_PIN13_OFFSET (scn->targetdef->d_GPIO_PIN13_OFFSET) 341 #define CLOCK_GPIO_OFFSET (scn->targetdef->d_CLOCK_GPIO_OFFSET) 342 #define CPU_CLOCK_STANDARD_LSB (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB) 343 #define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK) 344 #define LPO_CAL_ENABLE_LSB (scn->targetdef->d_LPO_CAL_ENABLE_LSB) 345 #define LPO_CAL_ENABLE_MASK (scn->targetdef->d_LPO_CAL_ENABLE_MASK) 346 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \ 347 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB) 348 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \ 349 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 350 #define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS) 351 #define WLAN_MAC_BASE_ADDRESS (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS) 352 #define FW_INDICATOR_ADDRESS (scn->targetdef->d_FW_INDICATOR_ADDRESS) 353 #define DRAM_BASE_ADDRESS (scn->targetdef->d_DRAM_BASE_ADDRESS) 354 #define SOC_CORE_BASE_ADDRESS (scn->targetdef->d_SOC_CORE_BASE_ADDRESS) 355 #define CORE_CTRL_ADDRESS (scn->targetdef->d_CORE_CTRL_ADDRESS) 356 #define CORE_CTRL_CPU_INTR_MASK (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK) 357 #define SOC_RESET_CONTROL_ADDRESS (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS) 358 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \ 359 (scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK) 360 #define CPU_INTR_ADDRESS (scn->targetdef->d_CPU_INTR_ADDRESS) 361 #define SOC_LF_TIMER_CONTROL0_ADDRESS \ 362 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS) 363 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \ 364 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK) 365 #define SOC_LF_TIMER_STATUS0_ADDRESS \ 366 (scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS) 367 368 369 #define CHIP_ID_ADDRESS (scn->targetdef->d_SOC_CHIP_ID_ADDRESS) 370 #define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK) 371 #define SOC_CHIP_ID_REVISION_LSB (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB) 372 #define SOC_CHIP_ID_VERSION_MASK (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK) 373 #define SOC_CHIP_ID_VERSION_LSB (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB) 374 #define CHIP_ID_REVISION_GET(x) \ 375 (((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB) 376 #define CHIP_ID_VERSION_GET(x) \ 377 (((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB) 378 379 /* misc */ 380 #define SR_WR_INDEX_ADDRESS (scn->targetdef->d_SR_WR_INDEX_ADDRESS) 381 #define DST_WATERMARK_ADDRESS (scn->targetdef->d_DST_WATERMARK_ADDRESS) 382 #define SOC_POWER_REG_OFFSET (scn->targetdef->d_SOC_POWER_REG_OFFSET) 383 /* end */ 384 385 /* htt_rx.c */ 386 #define RX_MSDU_END_4_FIRST_MSDU_MASK \ 387 (pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_MASK) 388 #define RX_MSDU_END_4_FIRST_MSDU_LSB \ 389 (pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_LSB) 390 #define RX_MPDU_START_0_RETRY_LSB \ 391 (pdev->targetdef->d_RX_MPDU_START_0_RETRY_LSB) 392 #define RX_MPDU_START_0_RETRY_MASK \ 393 (pdev->targetdef->d_RX_MPDU_START_0_RETRY_MASK) 394 #define RX_MPDU_START_0_SEQ_NUM_MASK \ 395 (pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_MASK) 396 #define RX_MPDU_START_0_SEQ_NUM_LSB \ 397 (pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_LSB) 398 #define RX_MPDU_START_2_PN_47_32_LSB \ 399 (pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_LSB) 400 #define RX_MPDU_START_2_PN_47_32_MASK \ 401 (pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_MASK) 402 #define RX_MPDU_START_2_TID_LSB \ 403 (pdev->targetdef->d_RX_MPDU_START_2_TID_LSB) 404 #define RX_MPDU_START_2_TID_MASK \ 405 (pdev->targetdef->d_RX_MPDU_START_2_TID_MASK) 406 #define RX_MSDU_END_1_KEY_ID_OCT_MASK \ 407 (pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_MASK) 408 #define RX_MSDU_END_1_KEY_ID_OCT_LSB \ 409 (pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_LSB) 410 #define RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK \ 411 (pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK) 412 #define RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB \ 413 (pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB) 414 #define RX_MSDU_END_4_LAST_MSDU_MASK \ 415 (pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_MASK) 416 #define RX_MSDU_END_4_LAST_MSDU_LSB \ 417 (pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_LSB) 418 #define RX_ATTENTION_0_MCAST_BCAST_MASK \ 419 (pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_MASK) 420 #define RX_ATTENTION_0_MCAST_BCAST_LSB \ 421 (pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_LSB) 422 #define RX_ATTENTION_0_FRAGMENT_MASK \ 423 (pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_MASK) 424 #define RX_ATTENTION_0_FRAGMENT_LSB \ 425 (pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_LSB) 426 #define RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK \ 427 (pdev->targetdef->d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK) 428 #define RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK \ 429 (pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK) 430 #define RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB \ 431 (pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB) 432 #define RX_MSDU_START_0_MSDU_LENGTH_MASK \ 433 (pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_MASK) 434 #define RX_MSDU_START_0_MSDU_LENGTH_LSB \ 435 (pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_LSB) 436 #define RX_MSDU_START_2_DECAP_FORMAT_OFFSET \ 437 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET) 438 #define RX_MSDU_START_2_DECAP_FORMAT_MASK \ 439 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_MASK) 440 #define RX_MSDU_START_2_DECAP_FORMAT_LSB \ 441 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_LSB) 442 #define RX_MPDU_START_0_ENCRYPTED_MASK \ 443 (pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_MASK) 444 #define RX_MPDU_START_0_ENCRYPTED_LSB \ 445 (pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_LSB) 446 #define RX_ATTENTION_0_MORE_DATA_MASK \ 447 (pdev->targetdef->d_RX_ATTENTION_0_MORE_DATA_MASK) 448 #define RX_ATTENTION_0_MSDU_DONE_MASK \ 449 (pdev->targetdef->d_RX_ATTENTION_0_MSDU_DONE_MASK) 450 #define RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK \ 451 (pdev->targetdef->d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK) 452 /* end */ 453 454 /* copy_engine.c */ 455 /* end */ 456 /* PLL start */ 457 #define EFUSE_OFFSET (scn->targetdef->d_EFUSE_OFFSET) 458 #define EFUSE_XTAL_SEL_MSB (scn->targetdef->d_EFUSE_XTAL_SEL_MSB) 459 #define EFUSE_XTAL_SEL_LSB (scn->targetdef->d_EFUSE_XTAL_SEL_LSB) 460 #define EFUSE_XTAL_SEL_MASK (scn->targetdef->d_EFUSE_XTAL_SEL_MASK) 461 #define BB_PLL_CONFIG_OFFSET (scn->targetdef->d_BB_PLL_CONFIG_OFFSET) 462 #define BB_PLL_CONFIG_OUTDIV_MSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB) 463 #define BB_PLL_CONFIG_OUTDIV_LSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB) 464 #define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK) 465 #define BB_PLL_CONFIG_FRAC_MSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB) 466 #define BB_PLL_CONFIG_FRAC_LSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB) 467 #define BB_PLL_CONFIG_FRAC_MASK (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK) 468 #define WLAN_PLL_SETTLE_TIME_MSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB) 469 #define WLAN_PLL_SETTLE_TIME_LSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB) 470 #define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK) 471 #define WLAN_PLL_SETTLE_OFFSET (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET) 472 #define WLAN_PLL_SETTLE_SW_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK) 473 #define WLAN_PLL_SETTLE_RSTMASK (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK) 474 #define WLAN_PLL_SETTLE_RESET (scn->targetdef->d_WLAN_PLL_SETTLE_RESET) 475 #define WLAN_PLL_CONTROL_NOPWD_MSB \ 476 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB) 477 #define WLAN_PLL_CONTROL_NOPWD_LSB \ 478 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB) 479 #define WLAN_PLL_CONTROL_NOPWD_MASK \ 480 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK) 481 #define WLAN_PLL_CONTROL_BYPASS_MSB \ 482 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB) 483 #define WLAN_PLL_CONTROL_BYPASS_LSB \ 484 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB) 485 #define WLAN_PLL_CONTROL_BYPASS_MASK \ 486 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK) 487 #define WLAN_PLL_CONTROL_BYPASS_RESET \ 488 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET) 489 #define WLAN_PLL_CONTROL_CLK_SEL_MSB \ 490 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB) 491 #define WLAN_PLL_CONTROL_CLK_SEL_LSB \ 492 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB) 493 #define WLAN_PLL_CONTROL_CLK_SEL_MASK \ 494 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK) 495 #define WLAN_PLL_CONTROL_CLK_SEL_RESET \ 496 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET) 497 #define WLAN_PLL_CONTROL_REFDIV_MSB \ 498 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB) 499 #define WLAN_PLL_CONTROL_REFDIV_LSB \ 500 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB) 501 #define WLAN_PLL_CONTROL_REFDIV_MASK \ 502 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK) 503 #define WLAN_PLL_CONTROL_REFDIV_RESET \ 504 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET) 505 #define WLAN_PLL_CONTROL_DIV_MSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB) 506 #define WLAN_PLL_CONTROL_DIV_LSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB) 507 #define WLAN_PLL_CONTROL_DIV_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK) 508 #define WLAN_PLL_CONTROL_DIV_RESET \ 509 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET) 510 #define WLAN_PLL_CONTROL_OFFSET (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET) 511 #define WLAN_PLL_CONTROL_SW_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK) 512 #define WLAN_PLL_CONTROL_RSTMASK (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK) 513 #define WLAN_PLL_CONTROL_RESET (scn->targetdef->d_WLAN_PLL_CONTROL_RESET) 514 #define SOC_CORE_CLK_CTRL_OFFSET (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET) 515 #define SOC_CORE_CLK_CTRL_DIV_MSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB) 516 #define SOC_CORE_CLK_CTRL_DIV_LSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB) 517 #define SOC_CORE_CLK_CTRL_DIV_MASK \ 518 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK) 519 #define RTC_SYNC_STATUS_PLL_CHANGING_MSB \ 520 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB) 521 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB \ 522 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB) 523 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK \ 524 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK) 525 #define RTC_SYNC_STATUS_PLL_CHANGING_RESET \ 526 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET) 527 #define RTC_SYNC_STATUS_OFFSET (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET) 528 #define SOC_CPU_CLOCK_OFFSET (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET) 529 #define SOC_CPU_CLOCK_STANDARD_MSB \ 530 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB) 531 #define SOC_CPU_CLOCK_STANDARD_LSB \ 532 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB) 533 #define SOC_CPU_CLOCK_STANDARD_MASK \ 534 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK) 535 /* PLL end */ 536 537 /* SET macros */ 538 #define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \ 539 (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \ 540 WLAN_SYSTEM_SLEEP_DISABLE_MASK) 541 #define SI_CONFIG_BIDIR_OD_DATA_SET(x) \ 542 (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) 543 #define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) 544 #define SI_CONFIG_POS_SAMPLE_SET(x) \ 545 (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) 546 #define SI_CONFIG_INACTIVE_CLK_SET(x) \ 547 (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) 548 #define SI_CONFIG_INACTIVE_DATA_SET(x) \ 549 (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) 550 #define SI_CONFIG_DIVIDER_SET(x) \ 551 (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) 552 #define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) 553 #define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) 554 #define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) 555 #define LPO_CAL_ENABLE_SET(x) \ 556 (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) 557 #define CPU_CLOCK_STANDARD_SET(x) \ 558 (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) 559 #define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \ 560 (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 561 /* copy_engine.c */ 562 /* end */ 563 /* PLL start */ 564 #define EFUSE_XTAL_SEL_GET(x) \ 565 (((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB) 566 #define EFUSE_XTAL_SEL_SET(x) \ 567 (((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK) 568 #define BB_PLL_CONFIG_OUTDIV_GET(x) \ 569 (((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB) 570 #define BB_PLL_CONFIG_OUTDIV_SET(x) \ 571 (((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK) 572 #define BB_PLL_CONFIG_FRAC_GET(x) \ 573 (((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB) 574 #define BB_PLL_CONFIG_FRAC_SET(x) \ 575 (((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK) 576 #define WLAN_PLL_SETTLE_TIME_GET(x) \ 577 (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB) 578 #define WLAN_PLL_SETTLE_TIME_SET(x) \ 579 (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK) 580 #define WLAN_PLL_CONTROL_NOPWD_GET(x) \ 581 (((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB) 582 #define WLAN_PLL_CONTROL_NOPWD_SET(x) \ 583 (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK) 584 #define WLAN_PLL_CONTROL_BYPASS_GET(x) \ 585 (((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB) 586 #define WLAN_PLL_CONTROL_BYPASS_SET(x) \ 587 (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK) 588 #define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \ 589 (((x) & WLAN_PLL_CONTROL_CLK_SEL_MASK) >> WLAN_PLL_CONTROL_CLK_SEL_LSB) 590 #define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \ 591 (((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & WLAN_PLL_CONTROL_CLK_SEL_MASK) 592 #define WLAN_PLL_CONTROL_REFDIV_GET(x) \ 593 (((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB) 594 #define WLAN_PLL_CONTROL_REFDIV_SET(x) \ 595 (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK) 596 #define WLAN_PLL_CONTROL_DIV_GET(x) \ 597 (((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB) 598 #define WLAN_PLL_CONTROL_DIV_SET(x) \ 599 (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK) 600 #define SOC_CORE_CLK_CTRL_DIV_GET(x) \ 601 (((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB) 602 #define SOC_CORE_CLK_CTRL_DIV_SET(x) \ 603 (((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK) 604 #define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \ 605 (((x) & RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \ 606 RTC_SYNC_STATUS_PLL_CHANGING_LSB) 607 #define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \ 608 (((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \ 609 RTC_SYNC_STATUS_PLL_CHANGING_MASK) 610 #define SOC_CPU_CLOCK_STANDARD_GET(x) \ 611 (((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB) 612 #define SOC_CPU_CLOCK_STANDARD_SET(x) \ 613 (((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK) 614 /* PLL end */ 615 616 #ifdef QCA_WIFI_3_0_ADRASTEA 617 #define Q6_ENABLE_REGISTER_0 \ 618 (scn->targetdef->d_Q6_ENABLE_REGISTER_0) 619 #define Q6_ENABLE_REGISTER_1 \ 620 (scn->targetdef->d_Q6_ENABLE_REGISTER_1) 621 #define Q6_CAUSE_REGISTER_0 \ 622 (scn->targetdef->d_Q6_CAUSE_REGISTER_0) 623 #define Q6_CAUSE_REGISTER_1 \ 624 (scn->targetdef->d_Q6_CAUSE_REGISTER_1) 625 #define Q6_CLEAR_REGISTER_0 \ 626 (scn->targetdef->d_Q6_CLEAR_REGISTER_0) 627 #define Q6_CLEAR_REGISTER_1 \ 628 (scn->targetdef->d_Q6_CLEAR_REGISTER_1) 629 #endif 630 631 struct hostdef_s { 632 uint32_t d_INT_STATUS_ENABLE_ERROR_LSB; 633 uint32_t d_INT_STATUS_ENABLE_ERROR_MASK; 634 uint32_t d_INT_STATUS_ENABLE_CPU_LSB; 635 uint32_t d_INT_STATUS_ENABLE_CPU_MASK; 636 uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB; 637 uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK; 638 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB; 639 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK; 640 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB; 641 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK; 642 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB; 643 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK; 644 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB; 645 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK; 646 uint32_t d_INT_STATUS_ENABLE_ADDRESS; 647 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB; 648 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK; 649 uint32_t d_HOST_INT_STATUS_ADDRESS; 650 uint32_t d_CPU_INT_STATUS_ADDRESS; 651 uint32_t d_ERROR_INT_STATUS_ADDRESS; 652 uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK; 653 uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB; 654 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK; 655 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB; 656 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK; 657 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB; 658 uint32_t d_COUNT_DEC_ADDRESS; 659 uint32_t d_HOST_INT_STATUS_CPU_MASK; 660 uint32_t d_HOST_INT_STATUS_CPU_LSB; 661 uint32_t d_HOST_INT_STATUS_ERROR_MASK; 662 uint32_t d_HOST_INT_STATUS_ERROR_LSB; 663 uint32_t d_HOST_INT_STATUS_COUNTER_MASK; 664 uint32_t d_HOST_INT_STATUS_COUNTER_LSB; 665 uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS; 666 uint32_t d_WINDOW_DATA_ADDRESS; 667 uint32_t d_WINDOW_READ_ADDR_ADDRESS; 668 uint32_t d_WINDOW_WRITE_ADDR_ADDRESS; 669 uint32_t d_SOC_GLOBAL_RESET_ADDRESS; 670 uint32_t d_RTC_STATE_ADDRESS; 671 uint32_t d_RTC_STATE_COLD_RESET_MASK; 672 uint32_t d_RTC_STATE_V_MASK; 673 uint32_t d_RTC_STATE_V_LSB; 674 uint32_t d_FW_IND_EVENT_PENDING; 675 uint32_t d_FW_IND_INITIALIZED; 676 uint32_t d_FW_IND_HELPER; 677 uint32_t d_RTC_STATE_V_ON; 678 #if defined(SDIO_3_0) 679 uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK; 680 uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB; 681 #endif 682 uint32_t d_MSI_MAGIC_ADR_ADDRESS; 683 uint32_t d_MSI_MAGIC_ADDRESS; 684 uint32_t d_ENABLE_MSI; 685 uint32_t d_MUX_ID_MASK; 686 uint32_t d_TRANSACTION_ID_MASK; 687 uint32_t d_DESC_DATA_FLAG_MASK; 688 }; 689 #define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK) 690 #define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK) 691 #define TRANSACTION_ID_MASK (scn->hostdef->d_TRANSACTION_ID_MASK) 692 #define ENABLE_MSI (scn->hostdef->d_ENABLE_MSI) 693 #define INT_STATUS_ENABLE_ERROR_LSB \ 694 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB) 695 #define INT_STATUS_ENABLE_ERROR_MASK \ 696 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK) 697 #define INT_STATUS_ENABLE_CPU_LSB (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB) 698 #define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK) 699 #define INT_STATUS_ENABLE_COUNTER_LSB \ 700 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB) 701 #define INT_STATUS_ENABLE_COUNTER_MASK \ 702 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK) 703 #define INT_STATUS_ENABLE_MBOX_DATA_LSB \ 704 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB) 705 #define INT_STATUS_ENABLE_MBOX_DATA_MASK \ 706 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK) 707 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \ 708 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) 709 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \ 710 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 711 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB \ 712 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) 713 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \ 714 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 715 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB \ 716 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB) 717 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK \ 718 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK) 719 #define INT_STATUS_ENABLE_ADDRESS \ 720 (scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS) 721 #define CPU_INT_STATUS_ENABLE_BIT_LSB \ 722 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB) 723 #define CPU_INT_STATUS_ENABLE_BIT_MASK \ 724 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK) 725 #define HOST_INT_STATUS_ADDRESS (scn->hostdef->d_HOST_INT_STATUS_ADDRESS) 726 #define CPU_INT_STATUS_ADDRESS (scn->hostdef->d_CPU_INT_STATUS_ADDRESS) 727 #define ERROR_INT_STATUS_ADDRESS (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS) 728 #define ERROR_INT_STATUS_WAKEUP_MASK \ 729 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK) 730 #define ERROR_INT_STATUS_WAKEUP_LSB \ 731 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB) 732 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \ 733 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK) 734 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \ 735 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 736 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK \ 737 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK) 738 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB \ 739 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB) 740 #define COUNT_DEC_ADDRESS (scn->hostdef->d_COUNT_DEC_ADDRESS) 741 #define HOST_INT_STATUS_CPU_MASK (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK) 742 #define HOST_INT_STATUS_CPU_LSB (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB) 743 #define HOST_INT_STATUS_ERROR_MASK (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK) 744 #define HOST_INT_STATUS_ERROR_LSB (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB) 745 #define HOST_INT_STATUS_COUNTER_MASK \ 746 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK) 747 #define HOST_INT_STATUS_COUNTER_LSB \ 748 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB) 749 #define RX_LOOKAHEAD_VALID_ADDRESS (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS) 750 #define WINDOW_DATA_ADDRESS (scn->hostdef->d_WINDOW_DATA_ADDRESS) 751 #define WINDOW_READ_ADDR_ADDRESS (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS) 752 #define WINDOW_WRITE_ADDR_ADDRESS (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS) 753 #define SOC_GLOBAL_RESET_ADDRESS (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS) 754 #define RTC_STATE_ADDRESS (scn->hostdef->d_RTC_STATE_ADDRESS) 755 #define RTC_STATE_COLD_RESET_MASK (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK) 756 #define RTC_STATE_V_MASK (scn->hostdef->d_RTC_STATE_V_MASK) 757 #define RTC_STATE_V_LSB (scn->hostdef->d_RTC_STATE_V_LSB) 758 #define FW_IND_EVENT_PENDING (scn->hostdef->d_FW_IND_EVENT_PENDING) 759 #define FW_IND_INITIALIZED (scn->hostdef->d_FW_IND_INITIALIZED) 760 #define FW_IND_HELPER (scn->hostdef->d_FW_IND_HELPER) 761 #define RTC_STATE_V_ON (scn->hostdef->d_RTC_STATE_V_ON) 762 #if defined(SDIO_3_0) 763 #define HOST_INT_STATUS_MBOX_DATA_MASK \ 764 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK) 765 #define HOST_INT_STATUS_MBOX_DATA_LSB \ 766 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB) 767 #endif 768 769 #if !defined(MSI_MAGIC_ADR_ADDRESS) 770 #define MSI_MAGIC_ADR_ADDRESS 0 771 #define MSI_MAGIC_ADDRESS 0 772 #endif 773 774 /* SET/GET macros */ 775 #define INT_STATUS_ENABLE_ERROR_SET(x) \ 776 (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) 777 #define INT_STATUS_ENABLE_CPU_SET(x) \ 778 (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) 779 #define INT_STATUS_ENABLE_COUNTER_SET(x) \ 780 (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \ 781 INT_STATUS_ENABLE_COUNTER_MASK) 782 #define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \ 783 (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \ 784 INT_STATUS_ENABLE_MBOX_DATA_MASK) 785 #define CPU_INT_STATUS_ENABLE_BIT_SET(x) \ 786 (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \ 787 CPU_INT_STATUS_ENABLE_BIT_MASK) 788 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \ 789 (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \ 790 ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 791 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) \ 792 (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \ 793 ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 794 #define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \ 795 (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \ 796 COUNTER_INT_STATUS_ENABLE_BIT_MASK) 797 #define ERROR_INT_STATUS_WAKEUP_GET(x) \ 798 (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \ 799 ERROR_INT_STATUS_WAKEUP_LSB) 800 #define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \ 801 (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \ 802 ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 803 #define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \ 804 (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \ 805 ERROR_INT_STATUS_TX_OVERFLOW_LSB) 806 #define HOST_INT_STATUS_CPU_GET(x) \ 807 (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) 808 #define HOST_INT_STATUS_ERROR_GET(x) \ 809 (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) 810 #define HOST_INT_STATUS_COUNTER_GET(x) \ 811 (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) 812 #define RTC_STATE_V_GET(x) \ 813 (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 814 #if defined(SDIO_3_0) 815 #define HOST_INT_STATUS_MBOX_DATA_GET(x) \ 816 (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \ 817 HOST_INT_STATUS_MBOX_DATA_LSB) 818 #endif 819 820 #define INVALID_REG_LOC_DUMMY_DATA 0xAA 821 822 #define AR6320_CORE_CLK_DIV_ADDR 0x403fa8 823 #define AR6320_CPU_PLL_INIT_DONE_ADDR 0x403fd0 824 #define AR6320_CPU_SPEED_ADDR 0x403fa4 825 #define AR6320V2_CORE_CLK_DIV_ADDR 0x403fd8 826 #define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0 827 #define AR6320V2_CPU_SPEED_ADDR 0x403fd4 828 #define AR6320V3_CORE_CLK_DIV_ADDR 0x404028 829 #define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020 830 #define AR6320V3_CPU_SPEED_ADDR 0x404024 831 832 enum a_refclk_speed_t { 833 SOC_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */ 834 SOC_REFCLK_48_MHZ = 0, 835 SOC_REFCLK_19_2_MHZ = 1, 836 SOC_REFCLK_24_MHZ = 2, 837 SOC_REFCLK_26_MHZ = 3, 838 SOC_REFCLK_37_4_MHZ = 4, 839 SOC_REFCLK_38_4_MHZ = 5, 840 SOC_REFCLK_40_MHZ = 6, 841 SOC_REFCLK_52_MHZ = 7, 842 }; 843 844 #define A_REFCLK_UNKNOWN SOC_REFCLK_UNKNOWN 845 #define A_REFCLK_48_MHZ SOC_REFCLK_48_MHZ 846 #define A_REFCLK_19_2_MHZ SOC_REFCLK_19_2_MHZ 847 #define A_REFCLK_24_MHZ SOC_REFCLK_24_MHZ 848 #define A_REFCLK_26_MHZ SOC_REFCLK_26_MHZ 849 #define A_REFCLK_37_4_MHZ SOC_REFCLK_37_4_MHZ 850 #define A_REFCLK_38_4_MHZ SOC_REFCLK_38_4_MHZ 851 #define A_REFCLK_40_MHZ SOC_REFCLK_40_MHZ 852 #define A_REFCLK_52_MHZ SOC_REFCLK_52_MHZ 853 854 #define TARGET_CPU_FREQ 176000000 855 856 struct wlan_pll_s { 857 uint32_t refdiv; 858 uint32_t div; 859 uint32_t rnfrac; 860 uint32_t outdiv; 861 }; 862 863 struct cmnos_clock_s { 864 enum a_refclk_speed_t refclk_speed; 865 uint32_t refclk_hz; 866 uint32_t pll_settling_time; /* 50us */ 867 struct wlan_pll_s wlan_pll; 868 }; 869 870 struct tgt_reg_section { 871 uint32_t start_addr; 872 uint32_t end_addr; 873 }; 874 875 876 struct tgt_reg_table { 877 const struct tgt_reg_section *section; 878 uint32_t section_size; 879 }; 880 #endif /* _REGTABLE_SDIO_H_ */ 881