1 /* 2 * Copyright (c) 2013-2014, 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HIF_SDIO_INTERNAL_H_ 20 #define _HIF_SDIO_INTERNAL_H_ 21 22 #include "a_debug.h" 23 #include "hif_sdio_dev.h" 24 #include "htc_packet.h" 25 #include "htc_api.h" 26 #include "hif_internal.h" 27 28 #define INVALID_MAILBOX_NUMBER 0xFF 29 30 #define HIF_SDIO_RX_BUFFER_SIZE 1792 31 #define HIF_SDIO_RX_DATA_OFFSET 64 32 33 /* TODO: print output level and mask control */ 34 #define ATH_DEBUG_IRQ ATH_DEBUG_MAKE_MODULE_MASK(4) 35 #define ATH_DEBUG_XMIT ATH_DEBUG_MAKE_MODULE_MASK(5) 36 #define ATH_DEBUG_RECV ATH_DEBUG_MAKE_MODULE_MASK(6) 37 38 #define ATH_DEBUG_MAX_MASK 32 39 40 #define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \ 41 INT_STATUS_ENABLE_CPU_MASK | \ 42 INT_STATUS_ENABLE_COUNTER_MASK) 43 44 /* HTC operational parameters */ 45 #define HTC_TARGET_RESPONSE_TIMEOUT 2000 /* in ms */ 46 #define HTC_TARGET_DEBUG_INTR_MASK 0x01 47 #define HTC_TARGET_CREDIT_INTR_MASK 0xF0 48 49 #define MAILBOX_COUNT 4 50 #define MAILBOX_FOR_BLOCK_SIZE 1 51 #define MAILBOX_USED_COUNT 2 52 #if defined(SDIO_3_0) 53 #define MAILBOX_LOOKAHEAD_SIZE_IN_WORD 2 54 #else 55 #define MAILBOX_LOOKAHEAD_SIZE_IN_WORD 1 56 #endif 57 #define AR6K_TARGET_DEBUG_INTR_MASK 0x01 58 59 PREPACK struct MBOX_IRQ_PROC_REGISTERS { 60 uint8_t host_int_status; 61 uint8_t cpu_int_status; 62 uint8_t error_int_status; 63 uint8_t counter_int_status; 64 uint8_t mbox_frame; 65 uint8_t rx_lookahead_valid; 66 uint8_t host_int_status2; 67 uint8_t gmbox_rx_avail; 68 uint32_t rx_lookahead[MAILBOX_LOOKAHEAD_SIZE_IN_WORD * MAILBOX_COUNT]; 69 uint32_t int_status_enable; 70 } POSTPACK; 71 72 PREPACK struct MBOX_IRQ_ENABLE_REGISTERS { 73 uint8_t int_status_enable; 74 uint8_t cpu_int_status_enable; 75 uint8_t error_status_enable; 76 uint8_t counter_int_status_enable; 77 } POSTPACK; 78 79 #define TOTAL_CREDIT_COUNTER_CNT 4 80 81 PREPACK struct MBOX_COUNTER_REGISTERS { 82 uint32_t counter[TOTAL_CREDIT_COUNTER_CNT]; 83 } POSTPACK; 84 85 #define SDIO_NUM_DATA_RX_BUFFERS 64 86 #define SDIO_DATA_RX_SIZE 1664 87 88 struct hif_sdio_device { 89 struct hif_sdio_dev *HIFDevice; 90 qdf_spinlock_t Lock; 91 qdf_spinlock_t TxLock; 92 qdf_spinlock_t RxLock; 93 struct MBOX_IRQ_PROC_REGISTERS IrqProcRegisters; 94 struct MBOX_IRQ_ENABLE_REGISTERS IrqEnableRegisters; 95 struct MBOX_COUNTER_REGISTERS MailBoxCounterRegisters; 96 struct hif_msg_callbacks hif_callbacks; 97 struct hif_device_mbox_info MailBoxInfo; 98 uint32_t BlockSize; 99 uint32_t BlockMask; 100 enum hif_device_irq_mode HifIRQProcessingMode; 101 struct hif_device_irq_yield_params HifIRQYieldParams; 102 bool DSRCanYield; 103 HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent; 104 int CurrentDSRRecvCount; 105 int RecheckIRQStatusCnt; 106 uint32_t RecvStateFlags; 107 void *pTarget; 108 }; 109 110 #define LOCK_HIF_DEV(device) qdf_spin_lock(&(device)->Lock) 111 #define UNLOCK_HIF_DEV(device) qdf_spin_unlock(&(device)->Lock) 112 #define LOCK_HIF_DEV_RX(t) qdf_spin_lock(&(t)->RxLock) 113 #define UNLOCK_HIF_DEV_RX(t) qdf_spin_unlock(&(t)->RxLock) 114 #define LOCK_HIF_DEV_TX(t) qdf_spin_lock(&(t)->TxLock) 115 #define UNLOCK_HIF_DEV_TX(t) qdf_spin_unlock(&(t)->TxLock) 116 117 #define DEV_CALC_RECV_PADDED_LEN(pDev, length) \ 118 (((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask))) 119 #define DEV_CALC_SEND_PADDED_LEN(pDev, length) \ 120 DEV_CALC_RECV_PADDED_LEN(pDev, length) 121 #define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) \ 122 (((length) % (pDev)->BlockSize) == 0) 123 124 #define HTC_RECV_WAIT_BUFFERS (1 << 0) 125 #define HTC_OP_STATE_STOPPING (1 << 0) 126 127 #define HTC_RX_PKT_IGNORE_LOOKAHEAD (1 << 0) 128 #define HTC_RX_PKT_REFRESH_HDR (1 << 1) 129 #define HTC_RX_PKT_PART_OF_BUNDLE (1 << 2) 130 #define HTC_RX_PKT_NO_RECYCLE (1 << 3) 131 #define HTC_RX_PKT_LAST_BUNDLED_PKT_HAS_ADDTIONAL_BLOCK (1 << 4) 132 133 #define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) \ 134 ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY) 135 136 /* hif_sdio_dev.c */ 137 HTC_PACKET *hif_dev_alloc_rx_buffer(struct hif_sdio_device *pDev); 138 139 uint8_t hif_dev_map_pipe_to_mail_box(struct hif_sdio_device *pDev, 140 uint8_t pipeid); 141 uint8_t hif_dev_map_mail_box_to_pipe(struct hif_sdio_device *pDev, 142 uint8_t mboxIndex, 143 bool upload); 144 145 /* hif_sdio_recv.c */ 146 QDF_STATUS hif_dev_rw_completion_handler(void *context, QDF_STATUS status); 147 QDF_STATUS hif_dev_dsr_handler(void *context); 148 149 #endif /* _HIF_SDIO_INTERNAL_H_ */ 150