1 /* 2 * Copyright (c) 2013-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HIF_SDIO_COMMON_H_ 20 #define _HIF_SDIO_COMMON_H_ 21 22 /* SDIO manufacturer ID and Codes */ 23 #define MANUFACTURER_ID_AR6002_BASE 0x200 24 #define MANUFACTURER_ID_AR6003_BASE 0x300 25 #define MANUFACTURER_ID_AR6004_BASE 0x400 26 #define MANUFACTURER_ID_AR6320_BASE 0x500 27 #define MANUFACTURER_ID_QCA9377_BASE 0x700 28 #define MANUFACTURER_ID_QCA9379_BASE 0x800 29 #define MANUFACTURER_ID_AR6K_BASE_MASK 0xFF00 30 #define MANUFACTURER_ID_AR6K_REV_MASK 0x00FF 31 #define FUNCTION_CLASS 0x0 32 #define MANUFACTURER_CODE 0x271 33 34 /* Mailbox address in SDIO address space */ 35 #if defined(SDIO_3_0) 36 #define HIF_MBOX_BASE_ADDR 0x1000 37 #define HIF_MBOX_DUMMY_WIDTH 0x800 38 #else 39 #define HIF_MBOX_BASE_ADDR 0x800 40 #define HIF_MBOX_DUMMY_WIDTH 0 41 #endif 42 43 #define HIF_MBOX_WIDTH 0x800 44 45 #define HIF_MBOX_START_ADDR(mbox) \ 46 (HIF_MBOX_BASE_ADDR + mbox * (HIF_MBOX_WIDTH + HIF_MBOX_DUMMY_WIDTH)) 47 48 #define HIF_MBOX_END_ADDR(mbox) \ 49 (HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1) 50 51 /* extended MBOX address for larger MBOX writes to MBOX 0*/ 52 #if defined(SDIO_3_0) 53 #define HIF_MBOX0_EXTENDED_BASE_ADDR 0x5000 54 #else 55 #define HIF_MBOX0_EXTENDED_BASE_ADDR 0x2800 56 #endif 57 #define HIF_MBOX0_EXTENDED_WIDTH_AR6002 (6*1024) 58 #define HIF_MBOX0_EXTENDED_WIDTH_AR6003 (18*1024) 59 60 /* version 1 of the chip has only a 12K extended mbox range */ 61 #define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1 0x4000 62 #define HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1 (12*1024) 63 64 #define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6004 0x2800 65 #define HIF_MBOX0_EXTENDED_WIDTH_AR6004 (18*1024) 66 67 68 #if defined(SDIO_3_0) 69 #define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6320 0x5000 70 #define HIF_MBOX0_EXTENDED_WIDTH_AR6320 (36*1024) 71 #define HIF_MBOX0_EXTENDED_WIDTH_AR6320_ROME_2_0 (56*1024) 72 #define HIF_MBOX1_EXTENDED_WIDTH_AR6320 (36*1024) 73 #define HIF_MBOX_DUMMY_SPACE_SIZE_AR6320 (2*1024) 74 #else 75 #define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6320 0x2800 76 #define HIF_MBOX0_EXTENDED_WIDTH_AR6320 (24*1024) 77 #define HIF_MBOX1_EXTENDED_WIDTH_AR6320 (24*1024) 78 #define HIF_MBOX_DUMMY_SPACE_SIZE_AR6320 0 79 #endif 80 81 82 /* GMBOX addresses */ 83 #define HIF_GMBOX_BASE_ADDR 0x7000 84 #define HIF_GMBOX_WIDTH 0x4000 85 86 /* for SDIO we recommend a 128-byte block size */ 87 #if defined(WITH_BACKPORTS) 88 #define HIF_DEFAULT_IO_BLOCK_SIZE 128 89 #else 90 #define HIF_DEFAULT_IO_BLOCK_SIZE 256 91 #endif 92 93 #define FIFO_TIMEOUT_AND_CHIP_CONTROL 0x00000868 94 #define FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF 0xFFFEFFFF 95 #define FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON 0x10000 96 /* In SDIO 2.0, asynchronous interrupt is not in SPEC 97 * requirement, but AR6003 support it, so the register 98 * is placed in vendor specific field 0xF0(bit0) 99 * In SDIO 3.0, the register is defined in SPEC, and its 100 * address is 0x16(bit1) 101 */ 102 /* interrupt mode register of AR6003 */ 103 #define CCCR_SDIO_IRQ_MODE_REG_AR6003 0xF0 104 /* mode to enable special 4-bit interrupt assertion without clock */ 105 #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_AR6003 (1 << 0) 106 /* interrupt mode register of AR6320 */ 107 #define CCCR_SDIO_IRQ_MODE_REG_AR6320 0x16 108 /* mode to enable special 4-bit interrupt assertion without clock */ 109 #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_AR6320 (1 << 1) 110 111 #define CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS 0xF0 112 #define CCCR_SDIO_ASYNC_INT_DELAY_LSB 0x06 113 #define CCCR_SDIO_ASYNC_INT_DELAY_MASK 0xC0 114 115 /* Vendor Specific Driver Strength Settings */ 116 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR 0xf2 117 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_MASK 0x0e 118 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A 0x02 119 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C 0x04 120 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D 0x08 121 122 #endif /* _HIF_SDIO_COMMON_H_ */ 123