1 /* 2 * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef __ATH_PCI_H__ 20 #define __ATH_PCI_H__ 21 22 #include <linux/version.h> 23 #include <linux/semaphore.h> 24 #include <linux/interrupt.h> 25 26 #define ATH_DBG_DEFAULT 0 27 #define DRAM_SIZE 0x000a8000 28 #include "hif.h" 29 #include "hif_runtime_pm.h" 30 #include "cepci.h" 31 #include "ce_main.h" 32 33 #ifdef FORCE_WAKE 34 /* Register to wake the UMAC from power collapse */ 35 #define PCIE_SOC_PCIE_REG_PCIE_SCRATCH_0_SOC_PCIE_REG (0x01E04000 + 0x40) 36 /* Register used for handshake mechanism to validate UMAC is awake */ 37 #define PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG (0x01E00000 + 0x3004) 38 /* Timeout duration to validate UMAC wake status */ 39 #ifdef HAL_CONFIG_SLUB_DEBUG_ON 40 #define FORCE_WAKE_DELAY_TIMEOUT_MS 500 41 #else 42 #define FORCE_WAKE_DELAY_TIMEOUT_MS 50 43 #endif /* HAL_CONFIG_SLUB_DEBUG_ON */ 44 /* Validate UMAC status every 5ms */ 45 #define FORCE_WAKE_DELAY_MS 5 46 #endif /* FORCE_WAKE */ 47 48 #ifdef QCA_HIF_HIA_EXTND 49 extern int32_t frac, intval, ar900b_20_targ_clk, qca9888_20_targ_clk; 50 #endif 51 52 /* An address (e.g. of a buffer) in Copy Engine space. */ 53 54 #define HIF_MAX_TASKLET_NUM 11 55 struct hif_tasklet_entry { 56 uint8_t id; /* 0 - 9: maps to CE, 10: fw */ 57 void *hif_handler; /* struct hif_pci_softc */ 58 }; 59 60 struct hang_event_bus_info { 61 uint16_t tlv_header; 62 uint16_t dev_id; 63 } qdf_packed; 64 65 /** 66 * struct hif_msi_info - Structure to hold msi info 67 * @magic: cookie 68 * @magic_da: dma address 69 * @dmaContext: dma address 70 * 71 * Structure to hold MSI information for PCIe interrupts 72 */ 73 struct hif_msi_info { 74 void *magic; 75 dma_addr_t magic_da; 76 OS_DMA_MEM_CONTEXT(dmacontext); 77 }; 78 79 /** 80 * struct hif_pci_stats - Account for hif pci based statistics 81 * @mhi_force_wake_request_vote: vote for mhi 82 * @mhi_force_wake_failure: mhi force wake failure 83 * @mhi_force_wake_success: mhi force wake success 84 * @soc_force_wake_register_write_success: write to soc wake 85 * @soc_force_wake_failure: soc force wake failure 86 * @soc_force_wake_success: soc force wake success 87 * @mhi_force_wake_release_success: mhi force wake release success 88 * @soc_force_wake_release_success: soc force wake release 89 */ 90 struct hif_pci_stats { 91 uint32_t mhi_force_wake_request_vote; 92 uint32_t mhi_force_wake_failure; 93 uint32_t mhi_force_wake_success; 94 uint32_t soc_force_wake_register_write_success; 95 uint32_t soc_force_wake_failure; 96 uint32_t soc_force_wake_success; 97 uint32_t mhi_force_wake_release_failure; 98 uint32_t mhi_force_wake_release_success; 99 uint32_t soc_force_wake_release_success; 100 }; 101 102 struct hif_pci_softc { 103 struct HIF_CE_state ce_sc; 104 void __iomem *mem; /* PCI address. */ 105 void __iomem *mem_ce; /* PCI address for CE. */ 106 size_t mem_len; 107 108 struct device *dev; /* For efficiency, should be first in struct */ 109 struct pci_dev *pdev; 110 int num_msi_intrs; /* number of MSI interrupts granted */ 111 /* 0 --> using legacy PCI line interrupts */ 112 struct tasklet_struct intr_tq; /* tasklet */ 113 struct hif_msi_info msi_info; 114 int ce_msi_irq_num[CE_COUNT_MAX]; 115 int irq; 116 int irq_event; 117 int cacheline_sz; 118 u16 devid; 119 struct hif_tasklet_entry tasklet_entries[HIF_MAX_TASKLET_NUM]; 120 bool pci_enabled; 121 bool use_register_windowing; 122 uint32_t register_window; 123 qdf_spinlock_t register_access_lock; 124 qdf_spinlock_t irq_lock; 125 qdf_work_t reschedule_tasklet_work; 126 uint32_t lcr_val; 127 #ifdef FEATURE_RUNTIME_PM 128 struct hif_runtime_pm_ctx rpm_ctx; 129 #endif 130 int (*hif_enable_pci)(struct hif_pci_softc *sc, struct pci_dev *pdev, 131 const struct pci_device_id *id); 132 void (*hif_pci_deinit)(struct hif_pci_softc *sc); 133 void (*hif_pci_get_soc_info)(struct hif_pci_softc *sc, 134 struct device *dev); 135 struct hif_pci_stats stats; 136 #ifdef HIF_CPU_PERF_AFFINE_MASK 137 /* Stores the affinity hint mask for each CE IRQ */ 138 qdf_cpu_mask ce_irq_cpu_mask[CE_COUNT_MAX]; 139 #endif 140 }; 141 142 bool hif_pci_targ_is_present(struct hif_softc *scn, void *__iomem *mem); 143 int hif_configure_irq(struct hif_softc *sc); 144 void hif_pci_cancel_deferred_target_sleep(struct hif_softc *scn); 145 void wlan_tasklet(unsigned long data); 146 irqreturn_t hif_pci_legacy_ce_interrupt_handler(int irq, void *arg); 147 int hif_pci_addr_in_boundary(struct hif_softc *scn, uint32_t offset); 148 149 /* 150 * A firmware interrupt to the Host is indicated by the 151 * low bit of SCRATCH_3_ADDRESS being set. 152 */ 153 #define FW_EVENT_PENDING_REG_ADDRESS SCRATCH_3_ADDRESS 154 155 /* 156 * Typically, MSI Interrupts are used with PCIe. To force use of legacy 157 * "ABCD" PCI line interrupts rather than MSI, define 158 * FORCE_LEGACY_PCI_INTERRUPTS. 159 * Even when NOT forced, the driver may attempt to use legacy PCI interrupts 160 * MSI allocation fails 161 */ 162 #define LEGACY_INTERRUPTS(sc) ((sc)->num_msi_intrs == 0) 163 164 /* 165 * There may be some pending tx frames during platform suspend. 166 * Suspend operation should be delayed until those tx frames are 167 * transferred from the host to target. This macro specifies how 168 * long suspend thread has to sleep before checking pending tx 169 * frame count. 170 */ 171 #define OL_ATH_TX_DRAIN_WAIT_DELAY 50 /* ms */ 172 173 #define HIF_CE_DRAIN_WAIT_DELAY 10 /* ms */ 174 /* 175 * Wait time (in unit of OL_ATH_TX_DRAIN_WAIT_DELAY) for pending 176 * tx frame completion before suspend. Refer: hif_pci_suspend() 177 */ 178 #ifndef QCA_WIFI_3_0_EMU 179 #define OL_ATH_TX_DRAIN_WAIT_CNT 10 180 #else 181 #define OL_ATH_TX_DRAIN_WAIT_CNT 60 182 #endif 183 184 #ifdef FORCE_WAKE 185 /** 186 * hif_print_pci_stats() - Display HIF PCI stats 187 * @hif_ctx - HIF pci handle 188 * 189 * Return: None 190 */ 191 void hif_print_pci_stats(struct hif_pci_softc *pci_scn); 192 #else 193 static inline 194 void hif_print_pci_stats(struct hif_pci_softc *pci_scn) 195 { 196 } 197 #endif /* FORCE_WAKE */ 198 #ifdef HIF_BUS_LOG_INFO 199 bool hif_log_pcie_info(struct hif_softc *scn, uint8_t *data, 200 unsigned int *offset); 201 #else 202 static inline 203 bool hif_log_pcie_info(struct hif_softc *scn, uint8_t *data, 204 unsigned int *offset) 205 { 206 return false; 207 } 208 #endif 209 #endif /* __ATH_PCI_H__ */ 210