1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef __ATH_PCI_H__ 20 #define __ATH_PCI_H__ 21 22 #include <linux/version.h> 23 #include <linux/semaphore.h> 24 #include <linux/interrupt.h> 25 26 #define ATH_DBG_DEFAULT 0 27 #define DRAM_SIZE 0x000a8000 28 #include "hif.h" 29 #include "hif_runtime_pm.h" 30 #include "cepci.h" 31 #include "ce_main.h" 32 33 #ifdef FORCE_WAKE 34 /* Register offset to wake the UMAC from power collapse */ 35 #define PCIE_REG_WAKE_UMAC_OFFSET 0x3004 36 /* Register used for handshake mechanism to validate UMAC is awake */ 37 #define PCIE_SOC_PCIE_REG_PCIE_SCRATCH_0_SOC_PCIE_REG (0x01E04000 + 0x40) 38 39 /* Timeout duration to validate UMAC wake status */ 40 #ifdef HAL_CONFIG_SLUB_DEBUG_ON 41 #define FORCE_WAKE_DELAY_TIMEOUT_MS 500 42 #else 43 #define FORCE_WAKE_DELAY_TIMEOUT_MS 50 44 #endif /* HAL_CONFIG_SLUB_DEBUG_ON */ 45 /* Validate UMAC status every 5ms */ 46 #define FORCE_WAKE_DELAY_MS 5 47 #endif /* FORCE_WAKE */ 48 49 #ifdef CONFIG_PCI_LOW_POWER_INT_REG 50 /* PCIe low power interrupt mask register */ 51 #define PCIE_LOW_POWER_INT_MASK_OFFSET 0x38044 52 #define INTR_L1SS BIT(3) 53 #define INTR_CLKPM BIT(4) 54 #endif 55 56 #ifdef QCA_HIF_HIA_EXTND 57 extern int32_t frac, intval, ar900b_20_targ_clk, qca9888_20_targ_clk; 58 #endif 59 60 /* An address (e.g. of a buffer) in Copy Engine space. */ 61 62 #define HIF_MAX_TASKLET_NUM 11 63 struct hif_tasklet_entry { 64 uint8_t id; /* 0 - 9: maps to CE, 10: fw */ 65 void *hif_handler; /* struct hif_pci_softc */ 66 }; 67 68 struct hang_event_bus_info { 69 uint16_t tlv_header; 70 uint16_t dev_id; 71 } qdf_packed; 72 73 /** 74 * struct hif_msi_info - Structure to hold msi info 75 * @magic: cookie 76 * @magic_da: dma address 77 * @dmaContext: dma address 78 * 79 * Structure to hold MSI information for PCIe interrupts 80 */ 81 struct hif_msi_info { 82 void *magic; 83 dma_addr_t magic_da; 84 OS_DMA_MEM_CONTEXT(dmacontext); 85 }; 86 87 /** 88 * struct hif_pci_stats - Account for hif pci based statistics 89 * @mhi_force_wake_request_vote: vote for mhi 90 * @mhi_force_wake_failure: mhi force wake failure 91 * @mhi_force_wake_success: mhi force wake success 92 * @soc_force_wake_register_write_success: write to soc wake 93 * @soc_force_wake_failure: soc force wake failure 94 * @soc_force_wake_success: soc force wake success 95 * @mhi_force_wake_release_success: mhi force wake release success 96 * @soc_force_wake_release_success: soc force wake release 97 */ 98 struct hif_pci_stats { 99 uint32_t mhi_force_wake_request_vote; 100 uint32_t mhi_force_wake_failure; 101 uint32_t mhi_force_wake_success; 102 uint32_t soc_force_wake_register_write_success; 103 uint32_t soc_force_wake_failure; 104 uint32_t soc_force_wake_success; 105 uint32_t mhi_force_wake_release_failure; 106 uint32_t mhi_force_wake_release_success; 107 uint32_t soc_force_wake_release_success; 108 }; 109 110 struct hif_soc_info { 111 u32 family_number; 112 u32 device_number; 113 u32 major_version; 114 u32 minor_version; 115 }; 116 117 struct hif_pci_softc { 118 struct HIF_CE_state ce_sc; 119 void __iomem *mem; /* PCI address. */ 120 void __iomem *mem_ce; /* PCI address for CE. */ 121 size_t mem_len; 122 123 struct device *dev; /* For efficiency, should be first in struct */ 124 struct pci_dev *pdev; 125 int num_msi_intrs; /* number of MSI interrupts granted */ 126 /* 0 --> using legacy PCI line interrupts */ 127 struct tasklet_struct intr_tq; /* tasklet */ 128 struct hif_msi_info msi_info; 129 int ce_msi_irq_num[CE_COUNT_MAX]; 130 int irq; 131 int irq_event; 132 int cacheline_sz; 133 u16 devid; 134 struct hif_tasklet_entry tasklet_entries[HIF_MAX_TASKLET_NUM]; 135 bool pci_enabled; 136 bool use_register_windowing; 137 uint32_t register_window; 138 qdf_spinlock_t register_access_lock; 139 qdf_spinlock_t irq_lock; 140 qdf_work_t reschedule_tasklet_work; 141 uint32_t lcr_val; 142 #ifdef FEATURE_RUNTIME_PM 143 struct hif_runtime_pm_ctx rpm_ctx; 144 #endif 145 int (*hif_enable_pci)(struct hif_pci_softc *sc, struct pci_dev *pdev, 146 const struct pci_device_id *id); 147 void (*hif_pci_deinit)(struct hif_pci_softc *sc); 148 void (*hif_pci_get_soc_info)(struct hif_pci_softc *sc, 149 struct device *dev); 150 struct hif_pci_stats stats; 151 #ifdef HIF_CPU_PERF_AFFINE_MASK 152 /* Stores the affinity hint mask for each CE IRQ */ 153 qdf_cpu_mask ce_irq_cpu_mask[CE_COUNT_MAX]; 154 #endif 155 struct hif_soc_info device_version; 156 }; 157 158 bool hif_pci_targ_is_present(struct hif_softc *scn, void *__iomem *mem); 159 int hif_configure_irq(struct hif_softc *sc); 160 void hif_pci_cancel_deferred_target_sleep(struct hif_softc *scn); 161 void wlan_tasklet(unsigned long data); 162 irqreturn_t hif_pci_legacy_ce_interrupt_handler(int irq, void *arg); 163 int hif_pci_addr_in_boundary(struct hif_softc *scn, uint32_t offset); 164 165 /* 166 * A firmware interrupt to the Host is indicated by the 167 * low bit of SCRATCH_3_ADDRESS being set. 168 */ 169 #define FW_EVENT_PENDING_REG_ADDRESS SCRATCH_3_ADDRESS 170 171 /* 172 * Typically, MSI Interrupts are used with PCIe. To force use of legacy 173 * "ABCD" PCI line interrupts rather than MSI, define 174 * FORCE_LEGACY_PCI_INTERRUPTS. 175 * Even when NOT forced, the driver may attempt to use legacy PCI interrupts 176 * MSI allocation fails 177 */ 178 #define LEGACY_INTERRUPTS(sc) ((sc)->num_msi_intrs == 0) 179 180 /* 181 * There may be some pending tx frames during platform suspend. 182 * Suspend operation should be delayed until those tx frames are 183 * transferred from the host to target. This macro specifies how 184 * long suspend thread has to sleep before checking pending tx 185 * frame count. 186 */ 187 #define OL_ATH_TX_DRAIN_WAIT_DELAY 50 /* ms */ 188 189 #define HIF_CE_DRAIN_WAIT_DELAY 10 /* ms */ 190 /* 191 * Wait time (in unit of OL_ATH_TX_DRAIN_WAIT_DELAY) for pending 192 * tx frame completion before suspend. Refer: hif_pci_suspend() 193 */ 194 #ifndef QCA_WIFI_3_0_EMU 195 #define OL_ATH_TX_DRAIN_WAIT_CNT 10 196 #else 197 #define OL_ATH_TX_DRAIN_WAIT_CNT 60 198 #endif 199 200 #ifdef FORCE_WAKE 201 /** 202 * hif_print_pci_stats() - Display HIF PCI stats 203 * @hif_ctx - HIF pci handle 204 * 205 * Return: None 206 */ 207 void hif_print_pci_stats(struct hif_pci_softc *pci_scn); 208 #else 209 static inline 210 void hif_print_pci_stats(struct hif_pci_softc *pci_scn) 211 { 212 } 213 #endif /* FORCE_WAKE */ 214 #ifdef HIF_BUS_LOG_INFO 215 bool hif_log_pcie_info(struct hif_softc *scn, uint8_t *data, 216 unsigned int *offset); 217 #else 218 static inline 219 bool hif_log_pcie_info(struct hif_softc *scn, uint8_t *data, 220 unsigned int *offset) 221 { 222 return false; 223 } 224 #endif 225 #endif /* __ATH_PCI_H__ */ 226