1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/pci.h> 21 #include <linux/slab.h> 22 #include <linux/interrupt.h> 23 #include <linux/if_arp.h> 24 #include <linux/of_pci.h> 25 #include <linux/version.h> 26 #include "hif_io32.h" 27 #include "if_pci.h" 28 #include "hif.h" 29 #include "target_type.h" 30 #include "hif_main.h" 31 #include "ce_main.h" 32 #include "ce_api.h" 33 #include "ce_internal.h" 34 #include "ce_reg.h" 35 #include "ce_bmi.h" 36 #include "regtable.h" 37 #include "hif_hw_version.h" 38 #include <linux/debugfs.h> 39 #include <linux/seq_file.h> 40 #include "qdf_status.h" 41 #include "qdf_atomic.h" 42 #include "qdf_platform.h" 43 #include "pld_common.h" 44 #include "mp_dev.h" 45 #include "hif_debug.h" 46 47 #ifdef QCA_SUPPORT_LEGACY_INTERRUPTS 48 char *legacy_ic_irqname[] = { 49 "ce0", 50 "ce1", 51 "ce2", 52 "ce3", 53 "ce4", 54 "ce5", 55 "ce6", 56 "ce7", 57 "ce8", 58 "ce9", 59 "ce10", 60 "ce11", 61 "ce12", 62 "ce13", 63 "ce14", 64 "ce15", 65 "reo2sw8_intr2", 66 "reo2sw7_intr2", 67 "reo2sw6_intr2", 68 "reo2sw5_intr2", 69 "reo2sw4_intr2", 70 "reo2sw3_intr2", 71 "reo2sw2_intr2", 72 "reo2sw1_intr2", 73 "reo2sw0_intr2", 74 "reo2sw8_intr", 75 "reo2sw7_intr", 76 "reo2sw6_inrr", 77 "reo2sw5_intr", 78 "reo2sw4_intr", 79 "reo2sw3_intr", 80 "reo2sw2_intr", 81 "reo2sw1_intr", 82 "reo2sw0_intr", 83 "reo2status_intr2", 84 "reo_status", 85 "reo2rxdma_out_2", 86 "reo2rxdma_out_1", 87 "reo_cmd", 88 "sw2reo6", 89 "sw2reo5", 90 "sw2reo1", 91 "sw2reo", 92 "rxdma2reo_mlo_0_dst_ring1", 93 "rxdma2reo_mlo_0_dst_ring0", 94 "rxdma2reo_mlo_1_dst_ring1", 95 "rxdma2reo_mlo_1_dst_ring0", 96 "rxdma2reo_dst_ring1", 97 "rxdma2reo_dst_ring0", 98 "rxdma2sw_dst_ring1", 99 "rxdma2sw_dst_ring0", 100 "rxdma2release_dst_ring1", 101 "rxdma2release_dst_ring0", 102 "sw2rxdma_2_src_ring", 103 "sw2rxdma_1_src_ring", 104 "sw2rxdma_0", 105 "wbm2sw6_release2", 106 "wbm2sw5_release2", 107 "wbm2sw4_release2", 108 "wbm2sw3_release2", 109 "wbm2sw2_release2", 110 "wbm2sw1_release2", 111 "wbm2sw0_release2", 112 "wbm2sw6_release", 113 "wbm2sw5_release", 114 "wbm2sw4_release", 115 "wbm2sw3_release", 116 "wbm2sw2_release", 117 "wbm2sw1_release", 118 "wbm2sw0_release", 119 "wbm2sw_link", 120 "wbm_error_release", 121 "sw2txmon_src_ring", 122 "sw2rxmon_src_ring", 123 "txmon2sw_p1_intr1", 124 "txmon2sw_p1_intr0", 125 "txmon2sw_p0_dest1", 126 "txmon2sw_p0_dest0", 127 "rxmon2sw_p1_intr1", 128 "rxmon2sw_p1_intr0", 129 "rxmon2sw_p0_dest1", 130 "rxmon2sw_p0_dest0", 131 "sw_release", 132 "sw2tcl_credit2", 133 "sw2tcl_credit", 134 "sw2tcl4", 135 "sw2tcl5", 136 "sw2tcl3", 137 "sw2tcl2", 138 "sw2tcl1", 139 "sw2wbm1", 140 "misc_8", 141 "misc_7", 142 "misc_6", 143 "misc_5", 144 "misc_4", 145 "misc_3", 146 "misc_2", 147 "misc_1", 148 "misc_0", 149 }; 150 #endif 151 152 #if (defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 153 defined(QCA_WIFI_KIWI)) 154 #include "hal_api.h" 155 #endif 156 157 #include "if_pci_internal.h" 158 #include "ce_tasklet.h" 159 #include "targaddrs.h" 160 #include "hif_exec.h" 161 162 #include "pci_api.h" 163 #include "ahb_api.h" 164 #include "wlan_cfg.h" 165 #include "qdf_hang_event_notifier.h" 166 #include "qdf_platform.h" 167 #include "qal_devnode.h" 168 #include "qdf_irq.h" 169 170 /* Maximum ms timeout for host to wake up target */ 171 #define PCIE_WAKE_TIMEOUT 1000 172 #define RAMDUMP_EVENT_TIMEOUT 2500 173 174 /* Setting SOC_GLOBAL_RESET during driver unload causes intermittent 175 * PCIe data bus error 176 * As workaround for this issue - changing the reset sequence to 177 * use TargetCPU warm reset * instead of SOC_GLOBAL_RESET 178 */ 179 #define CPU_WARM_RESET_WAR 180 #define WLAN_CFG_MAX_PCIE_GROUPS 5 181 #ifdef QCA_WIFI_QCN9224 182 #define WLAN_CFG_MAX_CE_COUNT 16 183 #else 184 #define WLAN_CFG_MAX_CE_COUNT 12 185 #endif 186 #define DP_IRQ_NAME_LEN 25 187 char dp_irqname[WLAN_CFG_MAX_PCIE_GROUPS][WLAN_CFG_INT_NUM_CONTEXTS][DP_IRQ_NAME_LEN] = {}; 188 char ce_irqname[WLAN_CFG_MAX_PCIE_GROUPS][WLAN_CFG_MAX_CE_COUNT][DP_IRQ_NAME_LEN] = {}; 189 190 #ifdef QCA_SUPPORT_LEGACY_INTERRUPTS 191 #define WLAN_CFG_MAX_LEGACY_IRQ_COUNT 160 192 char dp_legacy_irqname[WLAN_CFG_MAX_PCIE_GROUPS][WLAN_CFG_MAX_LEGACY_IRQ_COUNT][DP_IRQ_NAME_LEN] = {}; 193 #endif 194 195 static inline int hif_get_pci_slot(struct hif_softc *scn) 196 { 197 int pci_slot = pld_get_pci_slot(scn->qdf_dev->dev); 198 199 if (pci_slot < 0) { 200 hif_err("Invalid PCI SLOT %d", pci_slot); 201 qdf_assert_always(0); 202 return 0; 203 } else { 204 return pci_slot; 205 } 206 } 207 208 /* 209 * Top-level interrupt handler for all PCI interrupts from a Target. 210 * When a block of MSI interrupts is allocated, this top-level handler 211 * is not used; instead, we directly call the correct sub-handler. 212 */ 213 struct ce_irq_reg_table { 214 uint32_t irq_enable; 215 uint32_t irq_status; 216 }; 217 218 #ifndef QCA_WIFI_3_0_ADRASTEA 219 static inline void hif_pci_route_adrastea_interrupt(struct hif_pci_softc *sc) 220 { 221 } 222 #else 223 static void hif_pci_route_adrastea_interrupt(struct hif_pci_softc *sc) 224 { 225 struct hif_softc *scn = HIF_GET_SOFTC(sc); 226 unsigned int target_enable0, target_enable1; 227 unsigned int target_cause0, target_cause1; 228 229 target_enable0 = hif_read32_mb(sc, sc->mem + Q6_ENABLE_REGISTER_0); 230 target_enable1 = hif_read32_mb(sc, sc->mem + Q6_ENABLE_REGISTER_1); 231 target_cause0 = hif_read32_mb(sc, sc->mem + Q6_CAUSE_REGISTER_0); 232 target_cause1 = hif_read32_mb(sc, sc->mem + Q6_CAUSE_REGISTER_1); 233 234 if ((target_enable0 & target_cause0) || 235 (target_enable1 & target_cause1)) { 236 hif_write32_mb(sc, sc->mem + Q6_ENABLE_REGISTER_0, 0); 237 hif_write32_mb(sc, sc->mem + Q6_ENABLE_REGISTER_1, 0); 238 239 if (scn->notice_send) 240 pld_intr_notify_q6(sc->dev); 241 } 242 } 243 #endif 244 245 246 /** 247 * pci_dispatch_interrupt() - PCI interrupt dispatcher 248 * @scn: scn 249 * 250 * Return: N/A 251 */ 252 static void pci_dispatch_interrupt(struct hif_softc *scn) 253 { 254 uint32_t intr_summary; 255 int id; 256 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 257 258 if (scn->hif_init_done != true) 259 return; 260 261 if (Q_TARGET_ACCESS_BEGIN(scn) < 0) 262 return; 263 264 intr_summary = CE_INTERRUPT_SUMMARY(scn); 265 266 if (intr_summary == 0) { 267 if ((scn->target_status != TARGET_STATUS_RESET) && 268 (!qdf_atomic_read(&scn->link_suspended))) { 269 270 hif_write32_mb(scn, scn->mem + 271 (SOC_CORE_BASE_ADDRESS | 272 PCIE_INTR_ENABLE_ADDRESS), 273 HOST_GROUP0_MASK); 274 275 hif_read32_mb(scn, scn->mem + 276 (SOC_CORE_BASE_ADDRESS | 277 PCIE_INTR_ENABLE_ADDRESS)); 278 } 279 Q_TARGET_ACCESS_END(scn); 280 return; 281 } 282 Q_TARGET_ACCESS_END(scn); 283 284 scn->ce_irq_summary = intr_summary; 285 for (id = 0; intr_summary && (id < scn->ce_count); id++) { 286 if (intr_summary & (1 << id)) { 287 intr_summary &= ~(1 << id); 288 ce_dispatch_interrupt(id, &hif_state->tasklets[id]); 289 } 290 } 291 } 292 293 irqreturn_t hif_pci_legacy_ce_interrupt_handler(int irq, void *arg) 294 { 295 struct hif_pci_softc *sc = (struct hif_pci_softc *)arg; 296 struct hif_softc *scn = HIF_GET_SOFTC(sc); 297 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(arg); 298 299 volatile int tmp; 300 uint16_t val = 0; 301 uint32_t bar0 = 0; 302 uint32_t fw_indicator_address, fw_indicator; 303 bool ssr_irq = false; 304 unsigned int host_cause, host_enable; 305 306 if (LEGACY_INTERRUPTS(sc)) { 307 if (Q_TARGET_ACCESS_BEGIN(scn) < 0) 308 return IRQ_HANDLED; 309 310 if (ADRASTEA_BU) { 311 host_enable = hif_read32_mb(sc, sc->mem + 312 PCIE_INTR_ENABLE_ADDRESS); 313 host_cause = hif_read32_mb(sc, sc->mem + 314 PCIE_INTR_CAUSE_ADDRESS); 315 if (!(host_enable & host_cause)) { 316 hif_pci_route_adrastea_interrupt(sc); 317 return IRQ_HANDLED; 318 } 319 } 320 321 /* Clear Legacy PCI line interrupts 322 * IMPORTANT: INTR_CLR register has to be set 323 * after INTR_ENABLE is set to 0, 324 * otherwise interrupt can not be really cleared 325 */ 326 hif_write32_mb(sc, sc->mem + 327 (SOC_CORE_BASE_ADDRESS | 328 PCIE_INTR_ENABLE_ADDRESS), 0); 329 330 hif_write32_mb(sc, sc->mem + 331 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_CLR_ADDRESS), 332 ADRASTEA_BU ? 333 (host_enable & host_cause) : 334 HOST_GROUP0_MASK); 335 336 if (ADRASTEA_BU) 337 hif_write32_mb(sc, sc->mem + 0x2f100c, 338 (host_cause >> 1)); 339 340 /* IMPORTANT: this extra read transaction is required to 341 * flush the posted write buffer 342 */ 343 if (!ADRASTEA_BU) { 344 tmp = 345 hif_read32_mb(sc, sc->mem + 346 (SOC_CORE_BASE_ADDRESS | 347 PCIE_INTR_ENABLE_ADDRESS)); 348 349 if (tmp == 0xdeadbeef) { 350 hif_err("SoC returns 0xdeadbeef!!"); 351 352 pci_read_config_word(sc->pdev, PCI_VENDOR_ID, &val); 353 hif_err("PCI Vendor ID = 0x%04x", val); 354 355 pci_read_config_word(sc->pdev, PCI_DEVICE_ID, &val); 356 hif_err("PCI Device ID = 0x%04x", val); 357 358 pci_read_config_word(sc->pdev, PCI_COMMAND, &val); 359 hif_err("PCI Command = 0x%04x", val); 360 361 pci_read_config_word(sc->pdev, PCI_STATUS, &val); 362 hif_err("PCI Status = 0x%04x", val); 363 364 pci_read_config_dword(sc->pdev, PCI_BASE_ADDRESS_0, 365 &bar0); 366 hif_err("PCI BAR0 = 0x%08x", bar0); 367 368 hif_err("RTC_STATE_ADDRESS = 0x%08x", 369 hif_read32_mb(sc, sc->mem + 370 PCIE_LOCAL_BASE_ADDRESS 371 + RTC_STATE_ADDRESS)); 372 hif_err("PCIE_SOC_WAKE_ADDRESS = 0x%08x", 373 hif_read32_mb(sc, sc->mem + 374 PCIE_LOCAL_BASE_ADDRESS 375 + PCIE_SOC_WAKE_ADDRESS)); 376 hif_err("0x80008 = 0x%08x, 0x8000c = 0x%08x", 377 hif_read32_mb(sc, sc->mem + 0x80008), 378 hif_read32_mb(sc, sc->mem + 0x8000c)); 379 hif_err("0x80010 = 0x%08x, 0x80014 = 0x%08x", 380 hif_read32_mb(sc, sc->mem + 0x80010), 381 hif_read32_mb(sc, sc->mem + 0x80014)); 382 hif_err("0x80018 = 0x%08x, 0x8001c = 0x%08x", 383 hif_read32_mb(sc, sc->mem + 0x80018), 384 hif_read32_mb(sc, sc->mem + 0x8001c)); 385 QDF_BUG(0); 386 } 387 388 PCI_CLR_CAUSE0_REGISTER(sc); 389 } 390 391 if (HAS_FW_INDICATOR) { 392 fw_indicator_address = hif_state->fw_indicator_address; 393 fw_indicator = A_TARGET_READ(scn, fw_indicator_address); 394 if ((fw_indicator != ~0) && 395 (fw_indicator & FW_IND_EVENT_PENDING)) 396 ssr_irq = true; 397 } 398 399 if (Q_TARGET_ACCESS_END(scn) < 0) 400 return IRQ_HANDLED; 401 } 402 /* TBDXXX: Add support for WMAC */ 403 404 if (ssr_irq) { 405 sc->irq_event = irq; 406 qdf_atomic_set(&scn->tasklet_from_intr, 1); 407 408 qdf_atomic_inc(&scn->active_tasklet_cnt); 409 tasklet_schedule(&sc->intr_tq); 410 } else { 411 pci_dispatch_interrupt(scn); 412 } 413 414 return IRQ_HANDLED; 415 } 416 417 bool hif_pci_targ_is_present(struct hif_softc *scn, void *__iomem *mem) 418 { 419 return 1; /* FIX THIS */ 420 } 421 422 int hif_get_irq_num(struct hif_opaque_softc *scn, int *irq, uint32_t size) 423 { 424 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 425 int i = 0; 426 427 if (!irq || !size) { 428 return -EINVAL; 429 } 430 431 if (!sc->num_msi_intrs || sc->num_msi_intrs == 1) { 432 irq[0] = sc->irq; 433 return 1; 434 } 435 436 if (sc->num_msi_intrs > size) { 437 qdf_print("Not enough space in irq buffer to return irqs"); 438 return -EINVAL; 439 } 440 441 for (i = 0; i < sc->num_msi_intrs; i++) { 442 irq[i] = sc->irq + i + MSI_ASSIGN_CE_INITIAL; 443 } 444 445 return sc->num_msi_intrs; 446 } 447 448 449 /** 450 * hif_pci_cancel_deferred_target_sleep() - cancels the deferred target sleep 451 * @scn: hif_softc 452 * 453 * Return: void 454 */ 455 #if CONFIG_ATH_PCIE_MAX_PERF == 0 456 void hif_pci_cancel_deferred_target_sleep(struct hif_softc *scn) 457 { 458 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 459 A_target_id_t pci_addr = scn->mem; 460 461 qdf_spin_lock_irqsave(&hif_state->keep_awake_lock); 462 /* 463 * If the deferred sleep timer is running cancel it 464 * and put the soc into sleep. 465 */ 466 if (hif_state->fake_sleep == true) { 467 qdf_timer_stop(&hif_state->sleep_timer); 468 if (hif_state->verified_awake == false) { 469 hif_write32_mb(scn, pci_addr + PCIE_LOCAL_BASE_ADDRESS + 470 PCIE_SOC_WAKE_ADDRESS, 471 PCIE_SOC_WAKE_RESET); 472 } 473 hif_state->fake_sleep = false; 474 } 475 qdf_spin_unlock_irqrestore(&hif_state->keep_awake_lock); 476 } 477 #else 478 inline void hif_pci_cancel_deferred_target_sleep(struct hif_softc *scn) 479 { 480 } 481 #endif 482 483 #define A_PCIE_LOCAL_REG_READ(sc, mem, addr) \ 484 hif_read32_mb(sc, (char *)(mem) + \ 485 PCIE_LOCAL_BASE_ADDRESS + (uint32_t)(addr)) 486 487 #define A_PCIE_LOCAL_REG_WRITE(sc, mem, addr, val) \ 488 hif_write32_mb(sc, ((char *)(mem) + \ 489 PCIE_LOCAL_BASE_ADDRESS + (uint32_t)(addr)), (val)) 490 491 #ifdef QCA_WIFI_3_0 492 /** 493 * hif_targ_is_awake() - check to see if the target is awake 494 * @hif_ctx: hif context 495 * @mem: 496 * 497 * emulation never goes to sleep 498 * 499 * Return: true if target is awake 500 */ 501 static bool hif_targ_is_awake(struct hif_softc *hif_ctx, void *__iomem *mem) 502 { 503 return true; 504 } 505 #else 506 /** 507 * hif_targ_is_awake() - check to see if the target is awake 508 * @scn: hif context 509 * @mem: 510 * 511 * Return: true if the targets clocks are on 512 */ 513 static bool hif_targ_is_awake(struct hif_softc *scn, void *__iomem *mem) 514 { 515 uint32_t val; 516 517 if (scn->recovery) 518 return false; 519 val = hif_read32_mb(scn, mem + PCIE_LOCAL_BASE_ADDRESS 520 + RTC_STATE_ADDRESS); 521 return (RTC_STATE_V_GET(val) & RTC_STATE_V_ON) == RTC_STATE_V_ON; 522 } 523 #endif 524 525 #define ATH_PCI_RESET_WAIT_MAX 10 /* Ms */ 526 static void hif_pci_device_reset(struct hif_pci_softc *sc) 527 { 528 void __iomem *mem = sc->mem; 529 int i; 530 uint32_t val; 531 struct hif_softc *scn = HIF_GET_SOFTC(sc); 532 533 if (!scn->hostdef) 534 return; 535 536 /* NB: Don't check resetok here. This form of reset 537 * is integral to correct operation. 538 */ 539 540 if (!SOC_GLOBAL_RESET_ADDRESS) 541 return; 542 543 if (!mem) 544 return; 545 546 hif_err("Reset Device"); 547 548 /* 549 * NB: If we try to write SOC_GLOBAL_RESET_ADDRESS without first 550 * writing WAKE_V, the Target may scribble over Host memory! 551 */ 552 A_PCIE_LOCAL_REG_WRITE(sc, mem, PCIE_SOC_WAKE_ADDRESS, 553 PCIE_SOC_WAKE_V_MASK); 554 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) { 555 if (hif_targ_is_awake(scn, mem)) 556 break; 557 558 qdf_mdelay(1); 559 } 560 561 /* Put Target, including PCIe, into RESET. */ 562 val = A_PCIE_LOCAL_REG_READ(sc, mem, SOC_GLOBAL_RESET_ADDRESS); 563 val |= 1; 564 A_PCIE_LOCAL_REG_WRITE(sc, mem, SOC_GLOBAL_RESET_ADDRESS, val); 565 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) { 566 if (A_PCIE_LOCAL_REG_READ(sc, mem, RTC_STATE_ADDRESS) & 567 RTC_STATE_COLD_RESET_MASK) 568 break; 569 570 qdf_mdelay(1); 571 } 572 573 /* Pull Target, including PCIe, out of RESET. */ 574 val &= ~1; 575 A_PCIE_LOCAL_REG_WRITE(sc, mem, SOC_GLOBAL_RESET_ADDRESS, val); 576 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) { 577 if (! 578 (A_PCIE_LOCAL_REG_READ(sc, mem, RTC_STATE_ADDRESS) & 579 RTC_STATE_COLD_RESET_MASK)) 580 break; 581 582 qdf_mdelay(1); 583 } 584 585 A_PCIE_LOCAL_REG_WRITE(sc, mem, PCIE_SOC_WAKE_ADDRESS, 586 PCIE_SOC_WAKE_RESET); 587 } 588 589 /* CPU warm reset function 590 * Steps: 591 * 1. Disable all pending interrupts - so no pending interrupts on WARM reset 592 * 2. Clear the FW_INDICATOR_ADDRESS -so Target CPU initializes FW 593 * correctly on WARM reset 594 * 3. Clear TARGET CPU LF timer interrupt 595 * 4. Reset all CEs to clear any pending CE tarnsactions 596 * 5. Warm reset CPU 597 */ 598 static void hif_pci_device_warm_reset(struct hif_pci_softc *sc) 599 { 600 void __iomem *mem = sc->mem; 601 int i; 602 uint32_t val; 603 uint32_t fw_indicator; 604 struct hif_softc *scn = HIF_GET_SOFTC(sc); 605 606 /* NB: Don't check resetok here. This form of reset is 607 * integral to correct operation. 608 */ 609 610 if (!mem) 611 return; 612 613 hif_debug("Target Warm Reset"); 614 615 /* 616 * NB: If we try to write SOC_GLOBAL_RESET_ADDRESS without first 617 * writing WAKE_V, the Target may scribble over Host memory! 618 */ 619 A_PCIE_LOCAL_REG_WRITE(sc, mem, PCIE_SOC_WAKE_ADDRESS, 620 PCIE_SOC_WAKE_V_MASK); 621 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) { 622 if (hif_targ_is_awake(scn, mem)) 623 break; 624 qdf_mdelay(1); 625 } 626 627 /* 628 * Disable Pending interrupts 629 */ 630 val = 631 hif_read32_mb(sc, mem + 632 (SOC_CORE_BASE_ADDRESS | 633 PCIE_INTR_CAUSE_ADDRESS)); 634 hif_debug("Host Intr Cause reg 0x%x: value : 0x%x", 635 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_CAUSE_ADDRESS), val); 636 /* Target CPU Intr Cause */ 637 val = hif_read32_mb(sc, mem + 638 (SOC_CORE_BASE_ADDRESS | CPU_INTR_ADDRESS)); 639 hif_debug("Target CPU Intr Cause 0x%x", val); 640 641 val = 642 hif_read32_mb(sc, mem + 643 (SOC_CORE_BASE_ADDRESS | 644 PCIE_INTR_ENABLE_ADDRESS)); 645 hif_write32_mb(sc, (mem + 646 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS)), 0); 647 hif_write32_mb(sc, (mem + 648 (SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS)), 649 HOST_GROUP0_MASK); 650 651 qdf_mdelay(100); 652 653 /* Clear FW_INDICATOR_ADDRESS */ 654 if (HAS_FW_INDICATOR) { 655 fw_indicator = hif_read32_mb(sc, mem + FW_INDICATOR_ADDRESS); 656 hif_write32_mb(sc, mem + FW_INDICATOR_ADDRESS, 0); 657 } 658 659 /* Clear Target LF Timer interrupts */ 660 val = 661 hif_read32_mb(sc, mem + 662 (RTC_SOC_BASE_ADDRESS + 663 SOC_LF_TIMER_CONTROL0_ADDRESS)); 664 hif_debug("addr 0x%x : 0x%x", 665 (RTC_SOC_BASE_ADDRESS + SOC_LF_TIMER_CONTROL0_ADDRESS), val); 666 val &= ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK; 667 hif_write32_mb(sc, mem + 668 (RTC_SOC_BASE_ADDRESS + SOC_LF_TIMER_CONTROL0_ADDRESS), 669 val); 670 671 /* Reset CE */ 672 val = 673 hif_read32_mb(sc, mem + 674 (RTC_SOC_BASE_ADDRESS | 675 SOC_RESET_CONTROL_ADDRESS)); 676 val |= SOC_RESET_CONTROL_CE_RST_MASK; 677 hif_write32_mb(sc, (mem + 678 (RTC_SOC_BASE_ADDRESS | SOC_RESET_CONTROL_ADDRESS)), 679 val); 680 val = 681 hif_read32_mb(sc, mem + 682 (RTC_SOC_BASE_ADDRESS | 683 SOC_RESET_CONTROL_ADDRESS)); 684 qdf_mdelay(10); 685 686 /* CE unreset */ 687 val &= ~SOC_RESET_CONTROL_CE_RST_MASK; 688 hif_write32_mb(sc, mem + (RTC_SOC_BASE_ADDRESS | 689 SOC_RESET_CONTROL_ADDRESS), val); 690 val = 691 hif_read32_mb(sc, mem + 692 (RTC_SOC_BASE_ADDRESS | 693 SOC_RESET_CONTROL_ADDRESS)); 694 qdf_mdelay(10); 695 696 /* Read Target CPU Intr Cause */ 697 val = hif_read32_mb(sc, mem + 698 (SOC_CORE_BASE_ADDRESS | CPU_INTR_ADDRESS)); 699 hif_debug("Target CPU Intr Cause after CE reset 0x%x", val); 700 701 /* CPU warm RESET */ 702 val = 703 hif_read32_mb(sc, mem + 704 (RTC_SOC_BASE_ADDRESS | 705 SOC_RESET_CONTROL_ADDRESS)); 706 val |= SOC_RESET_CONTROL_CPU_WARM_RST_MASK; 707 hif_write32_mb(sc, mem + (RTC_SOC_BASE_ADDRESS | 708 SOC_RESET_CONTROL_ADDRESS), val); 709 val = 710 hif_read32_mb(sc, mem + 711 (RTC_SOC_BASE_ADDRESS | 712 SOC_RESET_CONTROL_ADDRESS)); 713 hif_debug("RESET_CONTROL after cpu warm reset 0x%x", val); 714 715 qdf_mdelay(100); 716 hif_debug("Target Warm reset complete"); 717 718 } 719 720 #ifndef QCA_WIFI_3_0 721 /* only applicable to legacy ce */ 722 int hif_check_fw_reg(struct hif_opaque_softc *hif_ctx) 723 { 724 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 725 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 726 void __iomem *mem = sc->mem; 727 uint32_t val; 728 729 if (Q_TARGET_ACCESS_BEGIN(scn) < 0) 730 return ATH_ISR_NOSCHED; 731 val = hif_read32_mb(sc, mem + FW_INDICATOR_ADDRESS); 732 if (Q_TARGET_ACCESS_END(scn) < 0) 733 return ATH_ISR_SCHED; 734 735 hif_debug("FW_INDICATOR register is 0x%x", val); 736 737 if (val & FW_IND_HELPER) 738 return 0; 739 740 return 1; 741 } 742 #endif 743 744 int hif_check_soc_status(struct hif_opaque_softc *hif_ctx) 745 { 746 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 747 uint16_t device_id = 0; 748 uint32_t val; 749 uint16_t timeout_count = 0; 750 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 751 752 /* Check device ID from PCIe configuration space for link status */ 753 pfrm_read_config_word(sc->pdev, PCI_DEVICE_ID, &device_id); 754 if (device_id != sc->devid) { 755 hif_err("Device ID does match (read 0x%x, expect 0x%x)", 756 device_id, sc->devid); 757 return -EACCES; 758 } 759 760 /* Check PCIe local register for bar/memory access */ 761 val = hif_read32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS + 762 RTC_STATE_ADDRESS); 763 hif_debug("RTC_STATE_ADDRESS is %08x", val); 764 765 /* Try to wake up target if it sleeps */ 766 hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS + 767 PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_V_MASK); 768 hif_debug("PCIE_SOC_WAKE_ADDRESS is %08x", 769 hif_read32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS + 770 PCIE_SOC_WAKE_ADDRESS)); 771 772 /* Check if target can be woken up */ 773 while (!hif_targ_is_awake(scn, sc->mem)) { 774 if (timeout_count >= PCIE_WAKE_TIMEOUT) { 775 hif_err("wake up timeout, %08x, %08x", 776 hif_read32_mb(sc, sc->mem + 777 PCIE_LOCAL_BASE_ADDRESS + 778 RTC_STATE_ADDRESS), 779 hif_read32_mb(sc, sc->mem + 780 PCIE_LOCAL_BASE_ADDRESS + 781 PCIE_SOC_WAKE_ADDRESS)); 782 return -EACCES; 783 } 784 785 hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS + 786 PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_V_MASK); 787 788 qdf_mdelay(100); 789 timeout_count += 100; 790 } 791 792 /* Check Power register for SoC internal bus issues */ 793 val = 794 hif_read32_mb(sc, sc->mem + RTC_SOC_BASE_ADDRESS + 795 SOC_POWER_REG_OFFSET); 796 hif_debug("Power register is %08x", val); 797 798 return 0; 799 } 800 801 /** 802 * __hif_pci_dump_registers(): dump other PCI debug registers 803 * @scn: struct hif_softc 804 * 805 * This function dumps pci debug registers. The parent function 806 * dumps the copy engine registers before calling this function. 807 * 808 * Return: void 809 */ 810 static void __hif_pci_dump_registers(struct hif_softc *scn) 811 { 812 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 813 void __iomem *mem = sc->mem; 814 uint32_t val, i, j; 815 uint32_t wrapper_idx[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9 }; 816 uint32_t ce_base; 817 818 if (Q_TARGET_ACCESS_BEGIN(scn) < 0) 819 return; 820 821 /* DEBUG_INPUT_SEL_SRC = 0x6 */ 822 val = 823 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + 824 WLAN_DEBUG_INPUT_SEL_OFFSET); 825 val &= ~WLAN_DEBUG_INPUT_SEL_SRC_MASK; 826 val |= WLAN_DEBUG_INPUT_SEL_SRC_SET(0x6); 827 hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS + 828 WLAN_DEBUG_INPUT_SEL_OFFSET, val); 829 830 /* DEBUG_CONTROL_ENABLE = 0x1 */ 831 val = hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + 832 WLAN_DEBUG_CONTROL_OFFSET); 833 val &= ~WLAN_DEBUG_CONTROL_ENABLE_MASK; 834 val |= WLAN_DEBUG_CONTROL_ENABLE_SET(0x1); 835 hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS + 836 WLAN_DEBUG_CONTROL_OFFSET, val); 837 838 hif_debug("Debug: inputsel: %x dbgctrl: %x", 839 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + 840 WLAN_DEBUG_INPUT_SEL_OFFSET), 841 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + 842 WLAN_DEBUG_CONTROL_OFFSET)); 843 844 hif_debug("Debug CE"); 845 /* Loop CE debug output */ 846 /* AMBA_DEBUG_BUS_SEL = 0xc */ 847 val = hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + 848 AMBA_DEBUG_BUS_OFFSET); 849 val &= ~AMBA_DEBUG_BUS_SEL_MASK; 850 val |= AMBA_DEBUG_BUS_SEL_SET(0xc); 851 hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET, 852 val); 853 854 for (i = 0; i < sizeof(wrapper_idx) / sizeof(uint32_t); i++) { 855 /* For (i=1,2,3,4,8,9) write CE_WRAPPER_DEBUG_SEL = i */ 856 val = hif_read32_mb(sc, mem + CE_WRAPPER_BASE_ADDRESS + 857 CE_WRAPPER_DEBUG_OFFSET); 858 val &= ~CE_WRAPPER_DEBUG_SEL_MASK; 859 val |= CE_WRAPPER_DEBUG_SEL_SET(wrapper_idx[i]); 860 hif_write32_mb(sc, mem + CE_WRAPPER_BASE_ADDRESS + 861 CE_WRAPPER_DEBUG_OFFSET, val); 862 863 hif_debug("ce wrapper: %d amdbg: %x cewdbg: %x", 864 wrapper_idx[i], 865 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + 866 AMBA_DEBUG_BUS_OFFSET), 867 hif_read32_mb(sc, mem + CE_WRAPPER_BASE_ADDRESS + 868 CE_WRAPPER_DEBUG_OFFSET)); 869 870 if (wrapper_idx[i] <= 7) { 871 for (j = 0; j <= 5; j++) { 872 ce_base = CE_BASE_ADDRESS(wrapper_idx[i]); 873 /* For (j=0~5) write CE_DEBUG_SEL = j */ 874 val = 875 hif_read32_mb(sc, mem + ce_base + 876 CE_DEBUG_OFFSET); 877 val &= ~CE_DEBUG_SEL_MASK; 878 val |= CE_DEBUG_SEL_SET(j); 879 hif_write32_mb(sc, mem + ce_base + 880 CE_DEBUG_OFFSET, val); 881 882 /* read (@gpio_athr_wlan_reg) 883 * WLAN_DEBUG_OUT_DATA 884 */ 885 val = hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS 886 + WLAN_DEBUG_OUT_OFFSET); 887 val = WLAN_DEBUG_OUT_DATA_GET(val); 888 889 hif_debug("module%d: cedbg: %x out: %x", 890 j, 891 hif_read32_mb(sc, mem + ce_base + 892 CE_DEBUG_OFFSET), val); 893 } 894 } else { 895 /* read (@gpio_athr_wlan_reg) WLAN_DEBUG_OUT_DATA */ 896 val = 897 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + 898 WLAN_DEBUG_OUT_OFFSET); 899 val = WLAN_DEBUG_OUT_DATA_GET(val); 900 901 hif_debug("out: %x", val); 902 } 903 } 904 905 hif_debug("Debug PCIe:"); 906 /* Loop PCIe debug output */ 907 /* Write AMBA_DEBUG_BUS_SEL = 0x1c */ 908 val = hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + 909 AMBA_DEBUG_BUS_OFFSET); 910 val &= ~AMBA_DEBUG_BUS_SEL_MASK; 911 val |= AMBA_DEBUG_BUS_SEL_SET(0x1c); 912 hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS + 913 AMBA_DEBUG_BUS_OFFSET, val); 914 915 for (i = 0; i <= 8; i++) { 916 /* For (i=1~8) write AMBA_DEBUG_BUS_PCIE_DEBUG_SEL = i */ 917 val = 918 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + 919 AMBA_DEBUG_BUS_OFFSET); 920 val &= ~AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK; 921 val |= AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(i); 922 hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS + 923 AMBA_DEBUG_BUS_OFFSET, val); 924 925 /* read (@gpio_athr_wlan_reg) WLAN_DEBUG_OUT_DATA */ 926 val = 927 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + 928 WLAN_DEBUG_OUT_OFFSET); 929 val = WLAN_DEBUG_OUT_DATA_GET(val); 930 931 hif_debug("amdbg: %x out: %x %x", 932 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + 933 WLAN_DEBUG_OUT_OFFSET), val, 934 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + 935 WLAN_DEBUG_OUT_OFFSET)); 936 } 937 938 Q_TARGET_ACCESS_END(scn); 939 } 940 941 /** 942 * hif_pci_dump_registers(): dump bus debug registers 943 * @hif_ctx: struct hif_opaque_softc 944 * 945 * This function dumps hif bus debug registers 946 * 947 * Return: 0 for success or error code 948 */ 949 int hif_pci_dump_registers(struct hif_softc *hif_ctx) 950 { 951 int status; 952 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 953 954 status = hif_dump_ce_registers(scn); 955 956 if (status) 957 hif_err("Dump CE Registers Failed"); 958 959 /* dump non copy engine pci registers */ 960 __hif_pci_dump_registers(scn); 961 962 return 0; 963 } 964 965 #ifdef HIF_CONFIG_SLUB_DEBUG_ON 966 967 /* worker thread to schedule wlan_tasklet in SLUB debug build */ 968 static void reschedule_tasklet_work_handler(void *arg) 969 { 970 struct hif_pci_softc *sc = arg; 971 struct hif_softc *scn = HIF_GET_SOFTC(sc); 972 973 if (!scn) { 974 hif_err("hif_softc is NULL"); 975 return; 976 } 977 978 if (scn->hif_init_done == false) { 979 hif_err("wlan driver is unloaded"); 980 return; 981 } 982 983 tasklet_schedule(&sc->intr_tq); 984 } 985 986 /** 987 * hif_init_reschedule_tasklet_work() - API to initialize reschedule tasklet 988 * work 989 * @sc: HIF PCI Context 990 * 991 * Return: void 992 */ 993 static void hif_init_reschedule_tasklet_work(struct hif_pci_softc *sc) 994 { 995 qdf_create_work(0, &sc->reschedule_tasklet_work, 996 reschedule_tasklet_work_handler, NULL); 997 } 998 #else 999 static void hif_init_reschedule_tasklet_work(struct hif_pci_softc *sc) { } 1000 #endif /* HIF_CONFIG_SLUB_DEBUG_ON */ 1001 1002 void wlan_tasklet(unsigned long data) 1003 { 1004 struct hif_pci_softc *sc = (struct hif_pci_softc *)data; 1005 struct hif_softc *scn = HIF_GET_SOFTC(sc); 1006 1007 if (scn->hif_init_done == false) 1008 goto end; 1009 1010 if (qdf_atomic_read(&scn->link_suspended)) 1011 goto end; 1012 1013 if (!ADRASTEA_BU) { 1014 hif_fw_interrupt_handler(sc->irq_event, scn); 1015 if (scn->target_status == TARGET_STATUS_RESET) 1016 goto end; 1017 } 1018 1019 end: 1020 qdf_atomic_set(&scn->tasklet_from_intr, 0); 1021 qdf_atomic_dec(&scn->active_tasklet_cnt); 1022 } 1023 1024 /** 1025 * hif_disable_power_gating() - disable HW power gating 1026 * @hif_ctx: hif context 1027 * 1028 * disables pcie L1 power states 1029 */ 1030 static void hif_disable_power_gating(struct hif_opaque_softc *hif_ctx) 1031 { 1032 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 1033 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_ctx); 1034 1035 if (!scn) { 1036 hif_err("Could not disable ASPM scn is null"); 1037 return; 1038 } 1039 1040 /* Disable ASPM when pkt log is enabled */ 1041 pfrm_read_config_dword(sc->pdev, 0x80, &sc->lcr_val); 1042 pfrm_write_config_dword(sc->pdev, 0x80, (sc->lcr_val & 0xffffff00)); 1043 } 1044 1045 /** 1046 * hif_enable_power_gating() - enable HW power gating 1047 * @sc: hif context 1048 * 1049 * enables pcie L1 power states 1050 */ 1051 static void hif_enable_power_gating(struct hif_pci_softc *sc) 1052 { 1053 if (!sc) { 1054 hif_err("Could not disable ASPM scn is null"); 1055 return; 1056 } 1057 1058 /* Re-enable ASPM after firmware/OTP download is complete */ 1059 pfrm_write_config_dword(sc->pdev, 0x80, sc->lcr_val); 1060 } 1061 1062 /** 1063 * hif_pci_enable_power_management() - enable power management 1064 * @hif_sc: hif context 1065 * @is_packet_log_enabled: 1066 * 1067 * Enables runtime pm, aspm(PCI.. hif_enable_power_gating) and re-enabling 1068 * soc-sleep after driver load (hif_pci_target_sleep_state_adjust). 1069 * 1070 * note: epping mode does not call this function as it does not 1071 * care about saving power. 1072 */ 1073 void hif_pci_enable_power_management(struct hif_softc *hif_sc, 1074 bool is_packet_log_enabled) 1075 { 1076 struct hif_pci_softc *pci_ctx = HIF_GET_PCI_SOFTC(hif_sc); 1077 uint32_t mode; 1078 1079 if (!pci_ctx) { 1080 hif_err("hif_ctx null"); 1081 return; 1082 } 1083 1084 mode = hif_get_conparam(hif_sc); 1085 if (mode == QDF_GLOBAL_FTM_MODE) { 1086 hif_info("Enable power gating for FTM mode"); 1087 hif_enable_power_gating(pci_ctx); 1088 return; 1089 } 1090 1091 hif_rtpm_start(hif_sc); 1092 1093 if (!is_packet_log_enabled) 1094 hif_enable_power_gating(pci_ctx); 1095 1096 if (!CONFIG_ATH_PCIE_MAX_PERF && 1097 CONFIG_ATH_PCIE_AWAKE_WHILE_DRIVER_LOAD && 1098 !ce_srng_based(hif_sc)) { 1099 /* allow sleep for PCIE_AWAKE_WHILE_DRIVER_LOAD feature */ 1100 if (hif_pci_target_sleep_state_adjust(hif_sc, true, false) < 0) 1101 hif_err("Failed to set target to sleep"); 1102 } 1103 } 1104 1105 /** 1106 * hif_pci_disable_power_management() - disable power management 1107 * @hif_ctx: hif context 1108 * 1109 * Currently disables runtime pm. Should be updated to behave 1110 * if runtime pm is not started. Should be updated to take care 1111 * of aspm and soc sleep for driver load. 1112 */ 1113 void hif_pci_disable_power_management(struct hif_softc *hif_ctx) 1114 { 1115 struct hif_pci_softc *pci_ctx = HIF_GET_PCI_SOFTC(hif_ctx); 1116 1117 if (!pci_ctx) { 1118 hif_err("hif_ctx null"); 1119 return; 1120 } 1121 1122 hif_rtpm_stop(hif_ctx); 1123 } 1124 1125 void hif_pci_display_stats(struct hif_softc *hif_ctx) 1126 { 1127 struct hif_pci_softc *pci_ctx = HIF_GET_PCI_SOFTC(hif_ctx); 1128 1129 if (!pci_ctx) { 1130 hif_err("hif_ctx null"); 1131 return; 1132 } 1133 hif_display_ce_stats(hif_ctx); 1134 1135 hif_print_pci_stats(pci_ctx); 1136 } 1137 1138 void hif_pci_clear_stats(struct hif_softc *hif_ctx) 1139 { 1140 struct hif_pci_softc *pci_ctx = HIF_GET_PCI_SOFTC(hif_ctx); 1141 1142 if (!pci_ctx) { 1143 hif_err("hif_ctx null"); 1144 return; 1145 } 1146 hif_clear_ce_stats(&pci_ctx->ce_sc); 1147 } 1148 1149 #define ATH_PCI_PROBE_RETRY_MAX 3 1150 /** 1151 * hif_pci_open(): hif_bus_open 1152 * @hif_ctx: scn 1153 * @bus_type: bus type 1154 * 1155 * Return: n/a 1156 */ 1157 QDF_STATUS hif_pci_open(struct hif_softc *hif_ctx, enum qdf_bus_type bus_type) 1158 { 1159 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_ctx); 1160 1161 hif_ctx->bus_type = bus_type; 1162 hif_rtpm_open(hif_ctx); 1163 1164 qdf_spinlock_create(&sc->irq_lock); 1165 qdf_spinlock_create(&sc->force_wake_lock); 1166 1167 return hif_ce_open(hif_ctx); 1168 } 1169 1170 /** 1171 * hif_wake_target_cpu() - wake the target's cpu 1172 * @scn: hif context 1173 * 1174 * Send an interrupt to the device to wake up the Target CPU 1175 * so it has an opportunity to notice any changed state. 1176 */ 1177 static void hif_wake_target_cpu(struct hif_softc *scn) 1178 { 1179 QDF_STATUS rv; 1180 uint32_t core_ctrl; 1181 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 1182 1183 rv = hif_diag_read_access(hif_hdl, 1184 SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS, 1185 &core_ctrl); 1186 QDF_ASSERT(rv == QDF_STATUS_SUCCESS); 1187 /* A_INUM_FIRMWARE interrupt to Target CPU */ 1188 core_ctrl |= CORE_CTRL_CPU_INTR_MASK; 1189 1190 rv = hif_diag_write_access(hif_hdl, 1191 SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS, 1192 core_ctrl); 1193 QDF_ASSERT(rv == QDF_STATUS_SUCCESS); 1194 } 1195 1196 /** 1197 * soc_wake_reset() - allow the target to go to sleep 1198 * @scn: hif_softc 1199 * 1200 * Clear the force wake register. This is done by 1201 * hif_sleep_entry and cancel deferred timer sleep. 1202 */ 1203 static void soc_wake_reset(struct hif_softc *scn) 1204 { 1205 hif_write32_mb(scn, scn->mem + 1206 PCIE_LOCAL_BASE_ADDRESS + 1207 PCIE_SOC_WAKE_ADDRESS, 1208 PCIE_SOC_WAKE_RESET); 1209 } 1210 1211 /** 1212 * hif_sleep_entry() - gate target sleep 1213 * @arg: hif context 1214 * 1215 * This function is the callback for the sleep timer. 1216 * Check if last force awake critical section was at least 1217 * HIF_MIN_SLEEP_INACTIVITY_TIME_MS time ago. if it was, 1218 * allow the target to go to sleep and cancel the sleep timer. 1219 * otherwise reschedule the sleep timer. 1220 */ 1221 static void hif_sleep_entry(void *arg) 1222 { 1223 struct HIF_CE_state *hif_state = (struct HIF_CE_state *)arg; 1224 struct hif_softc *scn = HIF_GET_SOFTC(hif_state); 1225 uint32_t idle_ms; 1226 1227 if (scn->recovery) 1228 return; 1229 1230 if (hif_is_driver_unloading(scn)) 1231 return; 1232 1233 qdf_spin_lock_irqsave(&hif_state->keep_awake_lock); 1234 if (hif_state->fake_sleep) { 1235 idle_ms = qdf_system_ticks_to_msecs(qdf_system_ticks() 1236 - hif_state->sleep_ticks); 1237 if (!hif_state->verified_awake && 1238 idle_ms >= HIF_MIN_SLEEP_INACTIVITY_TIME_MS) { 1239 if (!qdf_atomic_read(&scn->link_suspended)) { 1240 soc_wake_reset(scn); 1241 hif_state->fake_sleep = false; 1242 } 1243 } else { 1244 qdf_timer_stop(&hif_state->sleep_timer); 1245 qdf_timer_start(&hif_state->sleep_timer, 1246 HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS); 1247 } 1248 } 1249 qdf_spin_unlock_irqrestore(&hif_state->keep_awake_lock); 1250 } 1251 1252 #define HIF_HIA_MAX_POLL_LOOP 1000000 1253 #define HIF_HIA_POLLING_DELAY_MS 10 1254 1255 #ifdef QCA_HIF_HIA_EXTND 1256 1257 static void hif_set_hia_extnd(struct hif_softc *scn) 1258 { 1259 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 1260 struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); 1261 uint32_t target_type = tgt_info->target_type; 1262 1263 hif_info("E"); 1264 1265 if ((target_type == TARGET_TYPE_AR900B) || 1266 target_type == TARGET_TYPE_QCA9984 || 1267 target_type == TARGET_TYPE_QCA9888) { 1268 /* CHIP revision is 8-11 bits of the CHIP_ID register 0xec 1269 * in RTC space 1270 */ 1271 tgt_info->target_revision 1272 = CHIP_ID_REVISION_GET(hif_read32_mb(scn, scn->mem 1273 + CHIP_ID_ADDRESS)); 1274 qdf_print("chip_id 0x%x chip_revision 0x%x", 1275 target_type, tgt_info->target_revision); 1276 } 1277 1278 { 1279 uint32_t flag2_value = 0; 1280 uint32_t flag2_targ_addr = 1281 host_interest_item_address(target_type, 1282 offsetof(struct host_interest_s, hi_skip_clock_init)); 1283 1284 if ((ar900b_20_targ_clk != -1) && 1285 (frac != -1) && (intval != -1)) { 1286 hif_diag_read_access(hif_hdl, flag2_targ_addr, 1287 &flag2_value); 1288 qdf_print("\n Setting clk_override"); 1289 flag2_value |= CLOCK_OVERRIDE; 1290 1291 hif_diag_write_access(hif_hdl, flag2_targ_addr, 1292 flag2_value); 1293 qdf_print("\n CLOCK PLL val set %d", flag2_value); 1294 } else { 1295 qdf_print("\n CLOCK PLL skipped"); 1296 } 1297 } 1298 1299 if (target_type == TARGET_TYPE_AR900B 1300 || target_type == TARGET_TYPE_QCA9984 1301 || target_type == TARGET_TYPE_QCA9888) { 1302 1303 /* for AR9980_2.0, 300 mhz clock is used, right now we assume 1304 * this would be supplied through module parameters, 1305 * if not supplied assumed default or same behavior as 1.0. 1306 * Assume 1.0 clock can't be tuned, reset to defaults 1307 */ 1308 1309 qdf_print(KERN_INFO 1310 "%s: setting the target pll frac %x intval %x", 1311 __func__, frac, intval); 1312 1313 /* do not touch frac, and int val, let them be default -1, 1314 * if desired, host can supply these through module params 1315 */ 1316 if (frac != -1 || intval != -1) { 1317 uint32_t flag2_value = 0; 1318 uint32_t flag2_targ_addr; 1319 1320 flag2_targ_addr = 1321 host_interest_item_address(target_type, 1322 offsetof(struct host_interest_s, 1323 hi_clock_info)); 1324 hif_diag_read_access(hif_hdl, 1325 flag2_targ_addr, &flag2_value); 1326 qdf_print("\n ====> FRAC Val %x Address %x", frac, 1327 flag2_value); 1328 hif_diag_write_access(hif_hdl, flag2_value, frac); 1329 qdf_print("\n INT Val %x Address %x", 1330 intval, flag2_value + 4); 1331 hif_diag_write_access(hif_hdl, 1332 flag2_value + 4, intval); 1333 } else { 1334 qdf_print(KERN_INFO 1335 "%s: no frac provided, skipping pre-configuring PLL", 1336 __func__); 1337 } 1338 1339 /* for 2.0 write 300 mhz into hi_desired_cpu_speed_hz */ 1340 if ((target_type == TARGET_TYPE_AR900B) 1341 && (tgt_info->target_revision == AR900B_REV_2) 1342 && ar900b_20_targ_clk != -1) { 1343 uint32_t flag2_value = 0; 1344 uint32_t flag2_targ_addr; 1345 1346 flag2_targ_addr 1347 = host_interest_item_address(target_type, 1348 offsetof(struct host_interest_s, 1349 hi_desired_cpu_speed_hz)); 1350 hif_diag_read_access(hif_hdl, flag2_targ_addr, 1351 &flag2_value); 1352 qdf_print("\n ==> hi_desired_cpu_speed_hz Address %x", 1353 flag2_value); 1354 hif_diag_write_access(hif_hdl, flag2_value, 1355 ar900b_20_targ_clk/*300000000u*/); 1356 } else if (target_type == TARGET_TYPE_QCA9888) { 1357 uint32_t flag2_targ_addr; 1358 1359 if (200000000u != qca9888_20_targ_clk) { 1360 qca9888_20_targ_clk = 300000000u; 1361 /* Setting the target clock speed to 300 mhz */ 1362 } 1363 1364 flag2_targ_addr 1365 = host_interest_item_address(target_type, 1366 offsetof(struct host_interest_s, 1367 hi_desired_cpu_speed_hz)); 1368 hif_diag_write_access(hif_hdl, flag2_targ_addr, 1369 qca9888_20_targ_clk); 1370 } else { 1371 qdf_print("%s: targ_clk is not provided, skipping pre-configuring PLL", 1372 __func__); 1373 } 1374 } else { 1375 if (frac != -1 || intval != -1) { 1376 uint32_t flag2_value = 0; 1377 uint32_t flag2_targ_addr = 1378 host_interest_item_address(target_type, 1379 offsetof(struct host_interest_s, 1380 hi_clock_info)); 1381 hif_diag_read_access(hif_hdl, flag2_targ_addr, 1382 &flag2_value); 1383 qdf_print("\n ====> FRAC Val %x Address %x", frac, 1384 flag2_value); 1385 hif_diag_write_access(hif_hdl, flag2_value, frac); 1386 qdf_print("\n INT Val %x Address %x", intval, 1387 flag2_value + 4); 1388 hif_diag_write_access(hif_hdl, flag2_value + 4, 1389 intval); 1390 } 1391 } 1392 } 1393 1394 #else 1395 1396 static void hif_set_hia_extnd(struct hif_softc *scn) 1397 { 1398 } 1399 1400 #endif 1401 1402 /** 1403 * hif_set_hia() - fill out the host interest area 1404 * @scn: hif context 1405 * 1406 * This is replaced by hif_wlan_enable for integrated targets. 1407 * This fills out the host interest area. The firmware will 1408 * process these memory addresses when it is first brought out 1409 * of reset. 1410 * 1411 * Return: 0 for success. 1412 */ 1413 static int hif_set_hia(struct hif_softc *scn) 1414 { 1415 QDF_STATUS rv; 1416 uint32_t interconnect_targ_addr = 0; 1417 uint32_t pcie_state_targ_addr = 0; 1418 uint32_t pipe_cfg_targ_addr = 0; 1419 uint32_t svc_to_pipe_map = 0; 1420 uint32_t pcie_config_flags = 0; 1421 uint32_t flag2_value = 0; 1422 uint32_t flag2_targ_addr = 0; 1423 #ifdef QCA_WIFI_3_0 1424 uint32_t host_interest_area = 0; 1425 uint8_t i; 1426 #else 1427 uint32_t ealloc_value = 0; 1428 uint32_t ealloc_targ_addr = 0; 1429 uint8_t banks_switched = 1; 1430 uint32_t chip_id; 1431 #endif 1432 uint32_t pipe_cfg_addr; 1433 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 1434 struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); 1435 uint32_t target_type = tgt_info->target_type; 1436 uint32_t target_ce_config_sz, target_service_to_ce_map_sz; 1437 static struct CE_pipe_config *target_ce_config; 1438 struct service_to_pipe *target_service_to_ce_map; 1439 1440 hif_info("E"); 1441 1442 hif_get_target_ce_config(scn, 1443 &target_ce_config, &target_ce_config_sz, 1444 &target_service_to_ce_map, 1445 &target_service_to_ce_map_sz, 1446 NULL, NULL); 1447 1448 if (ADRASTEA_BU) 1449 return 0; 1450 1451 #ifdef QCA_WIFI_3_0 1452 i = 0; 1453 while (i < HIF_HIA_MAX_POLL_LOOP) { 1454 host_interest_area = hif_read32_mb(scn, scn->mem + 1455 A_SOC_CORE_SCRATCH_0_ADDRESS); 1456 if ((host_interest_area & 0x01) == 0) { 1457 qdf_mdelay(HIF_HIA_POLLING_DELAY_MS); 1458 host_interest_area = 0; 1459 i++; 1460 if (i > HIF_HIA_MAX_POLL_LOOP && (i % 1000 == 0)) 1461 hif_err("poll timeout: %d", i); 1462 } else { 1463 host_interest_area &= (~0x01); 1464 hif_write32_mb(scn, scn->mem + 0x113014, 0); 1465 break; 1466 } 1467 } 1468 1469 if (i >= HIF_HIA_MAX_POLL_LOOP) { 1470 hif_err("hia polling timeout"); 1471 return -EIO; 1472 } 1473 1474 if (host_interest_area == 0) { 1475 hif_err("host_interest_area = 0"); 1476 return -EIO; 1477 } 1478 1479 interconnect_targ_addr = host_interest_area + 1480 offsetof(struct host_interest_area_t, 1481 hi_interconnect_state); 1482 1483 flag2_targ_addr = host_interest_area + 1484 offsetof(struct host_interest_area_t, hi_option_flag2); 1485 1486 #else 1487 interconnect_targ_addr = hif_hia_item_address(target_type, 1488 offsetof(struct host_interest_s, hi_interconnect_state)); 1489 ealloc_targ_addr = hif_hia_item_address(target_type, 1490 offsetof(struct host_interest_s, hi_early_alloc)); 1491 flag2_targ_addr = hif_hia_item_address(target_type, 1492 offsetof(struct host_interest_s, hi_option_flag2)); 1493 #endif 1494 /* Supply Target-side CE configuration */ 1495 rv = hif_diag_read_access(hif_hdl, interconnect_targ_addr, 1496 &pcie_state_targ_addr); 1497 if (rv != QDF_STATUS_SUCCESS) { 1498 hif_err("interconnect_targ_addr = 0x%0x, ret = %d", 1499 interconnect_targ_addr, rv); 1500 goto done; 1501 } 1502 if (pcie_state_targ_addr == 0) { 1503 rv = QDF_STATUS_E_FAILURE; 1504 hif_err("pcie state addr is 0"); 1505 goto done; 1506 } 1507 pipe_cfg_addr = pcie_state_targ_addr + 1508 offsetof(struct pcie_state_s, 1509 pipe_cfg_addr); 1510 rv = hif_diag_read_access(hif_hdl, 1511 pipe_cfg_addr, 1512 &pipe_cfg_targ_addr); 1513 if (rv != QDF_STATUS_SUCCESS) { 1514 hif_err("pipe_cfg_addr = 0x%0x, ret = %d", pipe_cfg_addr, rv); 1515 goto done; 1516 } 1517 if (pipe_cfg_targ_addr == 0) { 1518 rv = QDF_STATUS_E_FAILURE; 1519 hif_err("pipe cfg addr is 0"); 1520 goto done; 1521 } 1522 1523 rv = hif_diag_write_mem(hif_hdl, pipe_cfg_targ_addr, 1524 (uint8_t *) target_ce_config, 1525 target_ce_config_sz); 1526 1527 if (rv != QDF_STATUS_SUCCESS) { 1528 hif_err("write pipe cfg: %d", rv); 1529 goto done; 1530 } 1531 1532 rv = hif_diag_read_access(hif_hdl, 1533 pcie_state_targ_addr + 1534 offsetof(struct pcie_state_s, 1535 svc_to_pipe_map), 1536 &svc_to_pipe_map); 1537 if (rv != QDF_STATUS_SUCCESS) { 1538 hif_err("get svc/pipe map: %d", rv); 1539 goto done; 1540 } 1541 if (svc_to_pipe_map == 0) { 1542 rv = QDF_STATUS_E_FAILURE; 1543 hif_err("svc_to_pipe map is 0"); 1544 goto done; 1545 } 1546 1547 rv = hif_diag_write_mem(hif_hdl, 1548 svc_to_pipe_map, 1549 (uint8_t *) target_service_to_ce_map, 1550 target_service_to_ce_map_sz); 1551 if (rv != QDF_STATUS_SUCCESS) { 1552 hif_err("write svc/pipe map: %d", rv); 1553 goto done; 1554 } 1555 1556 rv = hif_diag_read_access(hif_hdl, 1557 pcie_state_targ_addr + 1558 offsetof(struct pcie_state_s, 1559 config_flags), 1560 &pcie_config_flags); 1561 if (rv != QDF_STATUS_SUCCESS) { 1562 hif_err("get pcie config_flags: %d", rv); 1563 goto done; 1564 } 1565 #if (CONFIG_PCIE_ENABLE_L1_CLOCK_GATE) 1566 pcie_config_flags |= PCIE_CONFIG_FLAG_ENABLE_L1; 1567 #else 1568 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1; 1569 #endif /* CONFIG_PCIE_ENABLE_L1_CLOCK_GATE */ 1570 pcie_config_flags |= PCIE_CONFIG_FLAG_CLK_SWITCH_WAIT; 1571 #if (CONFIG_PCIE_ENABLE_AXI_CLK_GATE) 1572 pcie_config_flags |= PCIE_CONFIG_FLAG_AXI_CLK_GATE; 1573 #endif 1574 rv = hif_diag_write_mem(hif_hdl, 1575 pcie_state_targ_addr + 1576 offsetof(struct pcie_state_s, 1577 config_flags), 1578 (uint8_t *) &pcie_config_flags, 1579 sizeof(pcie_config_flags)); 1580 if (rv != QDF_STATUS_SUCCESS) { 1581 hif_err("write pcie config_flags: %d", rv); 1582 goto done; 1583 } 1584 1585 #ifndef QCA_WIFI_3_0 1586 /* configure early allocation */ 1587 ealloc_targ_addr = hif_hia_item_address(target_type, 1588 offsetof( 1589 struct host_interest_s, 1590 hi_early_alloc)); 1591 1592 rv = hif_diag_read_access(hif_hdl, ealloc_targ_addr, 1593 &ealloc_value); 1594 if (rv != QDF_STATUS_SUCCESS) { 1595 hif_err("get early alloc val: %d", rv); 1596 goto done; 1597 } 1598 1599 /* 1 bank is switched to IRAM, except ROME 1.0 */ 1600 ealloc_value |= 1601 ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) & 1602 HI_EARLY_ALLOC_MAGIC_MASK); 1603 1604 rv = hif_diag_read_access(hif_hdl, 1605 CHIP_ID_ADDRESS | 1606 RTC_SOC_BASE_ADDRESS, &chip_id); 1607 if (rv != QDF_STATUS_SUCCESS) { 1608 hif_err("get chip id val: %d", rv); 1609 goto done; 1610 } 1611 if (CHIP_ID_VERSION_GET(chip_id) == 0xD) { 1612 tgt_info->target_revision = CHIP_ID_REVISION_GET(chip_id); 1613 switch (CHIP_ID_REVISION_GET(chip_id)) { 1614 case 0x2: /* ROME 1.3 */ 1615 /* 2 banks are switched to IRAM */ 1616 banks_switched = 2; 1617 break; 1618 case 0x4: /* ROME 2.1 */ 1619 case 0x5: /* ROME 2.2 */ 1620 banks_switched = 6; 1621 break; 1622 case 0x8: /* ROME 3.0 */ 1623 case 0x9: /* ROME 3.1 */ 1624 case 0xA: /* ROME 3.2 */ 1625 banks_switched = 9; 1626 break; 1627 case 0x0: /* ROME 1.0 */ 1628 case 0x1: /* ROME 1.1 */ 1629 default: 1630 /* 3 banks are switched to IRAM */ 1631 banks_switched = 3; 1632 break; 1633 } 1634 } 1635 1636 ealloc_value |= 1637 ((banks_switched << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) 1638 & HI_EARLY_ALLOC_IRAM_BANKS_MASK); 1639 1640 rv = hif_diag_write_access(hif_hdl, 1641 ealloc_targ_addr, 1642 ealloc_value); 1643 if (rv != QDF_STATUS_SUCCESS) { 1644 hif_err("set early alloc val: %d", rv); 1645 goto done; 1646 } 1647 #endif 1648 if ((target_type == TARGET_TYPE_AR900B) 1649 || (target_type == TARGET_TYPE_QCA9984) 1650 || (target_type == TARGET_TYPE_QCA9888) 1651 || (target_type == TARGET_TYPE_AR9888)) { 1652 hif_set_hia_extnd(scn); 1653 } 1654 1655 /* Tell Target to proceed with initialization */ 1656 flag2_targ_addr = hif_hia_item_address(target_type, 1657 offsetof( 1658 struct host_interest_s, 1659 hi_option_flag2)); 1660 1661 rv = hif_diag_read_access(hif_hdl, flag2_targ_addr, 1662 &flag2_value); 1663 if (rv != QDF_STATUS_SUCCESS) { 1664 hif_err("get option val: %d", rv); 1665 goto done; 1666 } 1667 1668 flag2_value |= HI_OPTION_EARLY_CFG_DONE; 1669 rv = hif_diag_write_access(hif_hdl, flag2_targ_addr, 1670 flag2_value); 1671 if (rv != QDF_STATUS_SUCCESS) { 1672 hif_err("set option val: %d", rv); 1673 goto done; 1674 } 1675 1676 hif_wake_target_cpu(scn); 1677 1678 done: 1679 1680 return qdf_status_to_os_return(rv); 1681 } 1682 1683 /** 1684 * hif_pci_bus_configure() - configure the pcie bus 1685 * @hif_sc: pointer to the hif context. 1686 * 1687 * return: 0 for success. nonzero for failure. 1688 */ 1689 int hif_pci_bus_configure(struct hif_softc *hif_sc) 1690 { 1691 int status = 0; 1692 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_sc); 1693 struct hif_opaque_softc *hif_osc = GET_HIF_OPAQUE_HDL(hif_sc); 1694 1695 hif_ce_prepare_config(hif_sc); 1696 1697 /* initialize sleep state adjust variables */ 1698 hif_state->sleep_timer_init = true; 1699 hif_state->keep_awake_count = 0; 1700 hif_state->fake_sleep = false; 1701 hif_state->sleep_ticks = 0; 1702 1703 qdf_timer_init(NULL, &hif_state->sleep_timer, 1704 hif_sleep_entry, (void *)hif_state, 1705 QDF_TIMER_TYPE_WAKE_APPS); 1706 hif_state->sleep_timer_init = true; 1707 1708 status = hif_wlan_enable(hif_sc); 1709 if (status) { 1710 hif_err("hif_wlan_enable error: %d", status); 1711 goto timer_free; 1712 } 1713 1714 A_TARGET_ACCESS_LIKELY(hif_sc); 1715 1716 if ((CONFIG_ATH_PCIE_MAX_PERF || 1717 CONFIG_ATH_PCIE_AWAKE_WHILE_DRIVER_LOAD) && 1718 !ce_srng_based(hif_sc)) { 1719 /* 1720 * prevent sleep for PCIE_AWAKE_WHILE_DRIVER_LOAD feature 1721 * prevent sleep when we want to keep firmware always awake 1722 * note: when we want to keep firmware always awake, 1723 * hif_target_sleep_state_adjust will point to a dummy 1724 * function, and hif_pci_target_sleep_state_adjust must 1725 * be called instead. 1726 * note: bus type check is here because AHB bus is reusing 1727 * hif_pci_bus_configure code. 1728 */ 1729 if (hif_sc->bus_type == QDF_BUS_TYPE_PCI) { 1730 if (hif_pci_target_sleep_state_adjust(hif_sc, 1731 false, true) < 0) { 1732 status = -EACCES; 1733 goto disable_wlan; 1734 } 1735 } 1736 } 1737 1738 /* todo: consider replacing this with an srng field */ 1739 if (((hif_sc->target_info.target_type == TARGET_TYPE_QCA8074) || 1740 (hif_sc->target_info.target_type == TARGET_TYPE_QCA8074V2) || 1741 (hif_sc->target_info.target_type == TARGET_TYPE_QCA9574) || 1742 (hif_sc->target_info.target_type == TARGET_TYPE_QCA5332) || 1743 (hif_sc->target_info.target_type == TARGET_TYPE_QCA5018) || 1744 (hif_sc->target_info.target_type == TARGET_TYPE_QCN6122) || 1745 (hif_sc->target_info.target_type == TARGET_TYPE_QCN9160) || 1746 (hif_sc->target_info.target_type == TARGET_TYPE_QCA6018) || 1747 (hif_sc->target_info.target_type == TARGET_TYPE_QCN6432)) && 1748 (hif_sc->bus_type == QDF_BUS_TYPE_AHB)) { 1749 hif_sc->per_ce_irq = true; 1750 } 1751 1752 status = hif_config_ce(hif_sc); 1753 if (status) 1754 goto disable_wlan; 1755 1756 if (hif_needs_bmi(hif_osc)) { 1757 status = hif_set_hia(hif_sc); 1758 if (status) 1759 goto unconfig_ce; 1760 1761 hif_debug("hif_set_hia done"); 1762 1763 } 1764 1765 if (((hif_sc->target_info.target_type == TARGET_TYPE_QCA8074) || 1766 (hif_sc->target_info.target_type == TARGET_TYPE_QCA8074V2) || 1767 (hif_sc->target_info.target_type == TARGET_TYPE_QCA9574) || 1768 (hif_sc->target_info.target_type == TARGET_TYPE_QCA5332) || 1769 (hif_sc->target_info.target_type == TARGET_TYPE_QCA5018) || 1770 (hif_sc->target_info.target_type == TARGET_TYPE_QCN6122) || 1771 (hif_sc->target_info.target_type == TARGET_TYPE_QCN9160) || 1772 (hif_sc->target_info.target_type == TARGET_TYPE_QCA6018) || 1773 (hif_sc->target_info.target_type == TARGET_TYPE_QCN6432)) && 1774 (hif_sc->bus_type == QDF_BUS_TYPE_PCI)) 1775 hif_debug("Skip irq config for PCI based 8074 target"); 1776 else { 1777 status = hif_configure_irq(hif_sc); 1778 if (status < 0) 1779 goto unconfig_ce; 1780 } 1781 1782 A_TARGET_ACCESS_UNLIKELY(hif_sc); 1783 1784 return status; 1785 1786 unconfig_ce: 1787 hif_unconfig_ce(hif_sc); 1788 disable_wlan: 1789 A_TARGET_ACCESS_UNLIKELY(hif_sc); 1790 hif_wlan_disable(hif_sc); 1791 1792 timer_free: 1793 qdf_timer_stop(&hif_state->sleep_timer); 1794 qdf_timer_free(&hif_state->sleep_timer); 1795 hif_state->sleep_timer_init = false; 1796 1797 hif_err("Failed, status: %d", status); 1798 return status; 1799 } 1800 1801 /** 1802 * hif_pci_close(): hif_bus_close 1803 * @hif_sc: HIF context 1804 * 1805 * Return: n/a 1806 */ 1807 void hif_pci_close(struct hif_softc *hif_sc) 1808 { 1809 hif_rtpm_close(hif_sc); 1810 hif_ce_close(hif_sc); 1811 } 1812 1813 #define BAR_NUM 0 1814 1815 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)) 1816 static inline int hif_pci_set_dma_mask(struct pci_dev *pci_dev, u64 mask) 1817 { 1818 return dma_set_mask(&pci_dev->dev, mask); 1819 } 1820 1821 static inline int hif_pci_set_coherent_dma_mask(struct pci_dev *pci_dev, 1822 u64 mask) 1823 { 1824 return dma_set_coherent_mask(&pci_dev->dev, mask); 1825 } 1826 #else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)) */ 1827 static inline int hif_pci_set_dma_mask(struct pci_dev *pci_dev, u64 mask) 1828 { 1829 return pci_set_dma_mask(pci_dev, mask); 1830 } 1831 1832 static inline int hif_pci_set_coherent_dma_mask(struct pci_dev *pci_dev, 1833 u64 mask) 1834 { 1835 return pci_set_consistent_dma_mask(pci_dev, mask); 1836 } 1837 #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)) */ 1838 1839 static int hif_enable_pci_nopld(struct hif_pci_softc *sc, 1840 struct pci_dev *pdev, 1841 const struct pci_device_id *id) 1842 { 1843 void __iomem *mem; 1844 int ret = 0; 1845 uint16_t device_id = 0; 1846 struct hif_softc *ol_sc = HIF_GET_SOFTC(sc); 1847 1848 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 1849 if (device_id != id->device) { 1850 hif_err( 1851 "dev id mismatch, config id = 0x%x, probing id = 0x%x", 1852 device_id, id->device); 1853 /* pci link is down, so returning with error code */ 1854 return -EIO; 1855 } 1856 1857 /* FIXME: temp. commenting out assign_resource 1858 * call for dev_attach to work on 2.6.38 kernel 1859 */ 1860 #if (!defined(__LINUX_ARM_ARCH__)) 1861 if (pci_assign_resource(pdev, BAR_NUM)) { 1862 hif_err("pci_assign_resource error"); 1863 return -EIO; 1864 } 1865 #endif 1866 if (pci_enable_device(pdev)) { 1867 hif_err("pci_enable_device error"); 1868 return -EIO; 1869 } 1870 1871 /* Request MMIO resources */ 1872 ret = pci_request_region(pdev, BAR_NUM, "ath"); 1873 if (ret) { 1874 hif_err("PCI MMIO reservation error"); 1875 ret = -EIO; 1876 goto err_region; 1877 } 1878 1879 #ifdef CONFIG_ARM_LPAE 1880 /* if CONFIG_ARM_LPAE is enabled, we have to set 64 bits mask 1881 * for 32 bits device also. 1882 */ 1883 ret = hif_pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1884 if (ret) { 1885 hif_err("Cannot enable 64-bit pci DMA"); 1886 goto err_dma; 1887 } 1888 ret = hif_pci_set_coherent_dma_mask(pdev, DMA_BIT_MASK(64)); 1889 if (ret) { 1890 hif_err("Cannot enable 64-bit DMA"); 1891 goto err_dma; 1892 } 1893 #else 1894 ret = hif_pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1895 if (ret) { 1896 hif_err("Cannot enable 32-bit pci DMA"); 1897 goto err_dma; 1898 } 1899 ret = hif_pci_set_coherent_dma_mask(pdev, DMA_BIT_MASK(32)); 1900 if (ret) { 1901 hif_err("Cannot enable 32-bit coherent DMA!"); 1902 goto err_dma; 1903 } 1904 #endif 1905 1906 PCI_CFG_TO_DISABLE_L1SS_STATES(pdev, 0x188); 1907 1908 /* Set bus master bit in PCI_COMMAND to enable DMA */ 1909 pci_set_master(pdev); 1910 1911 /* Arrange for access to Target SoC registers. */ 1912 mem = pci_iomap(pdev, BAR_NUM, 0); 1913 if (!mem) { 1914 hif_err("PCI iomap error"); 1915 ret = -EIO; 1916 goto err_iomap; 1917 } 1918 1919 hif_info("*****BAR is %pK", (void *)mem); 1920 1921 sc->mem = mem; 1922 1923 /* Hawkeye emulation specific change */ 1924 if ((device_id == RUMIM2M_DEVICE_ID_NODE0) || 1925 (device_id == RUMIM2M_DEVICE_ID_NODE1) || 1926 (device_id == RUMIM2M_DEVICE_ID_NODE2) || 1927 (device_id == RUMIM2M_DEVICE_ID_NODE3) || 1928 (device_id == RUMIM2M_DEVICE_ID_NODE4) || 1929 (device_id == RUMIM2M_DEVICE_ID_NODE5)) { 1930 mem = mem + 0x0c000000; 1931 sc->mem = mem; 1932 hif_info("Changing PCI mem base to %pK", sc->mem); 1933 } 1934 1935 sc->mem_len = pci_resource_len(pdev, BAR_NUM); 1936 ol_sc->mem = mem; 1937 ol_sc->mem_pa = pci_resource_start(pdev, BAR_NUM); 1938 sc->pci_enabled = true; 1939 return ret; 1940 1941 err_iomap: 1942 pci_clear_master(pdev); 1943 err_dma: 1944 pci_release_region(pdev, BAR_NUM); 1945 err_region: 1946 pci_disable_device(pdev); 1947 return ret; 1948 } 1949 1950 static int hif_enable_pci_pld(struct hif_pci_softc *sc, 1951 struct pci_dev *pdev, 1952 const struct pci_device_id *id) 1953 { 1954 PCI_CFG_TO_DISABLE_L1SS_STATES(pdev, 0x188); 1955 sc->pci_enabled = true; 1956 return 0; 1957 } 1958 1959 1960 static void hif_pci_deinit_nopld(struct hif_pci_softc *sc) 1961 { 1962 pci_disable_msi(sc->pdev); 1963 pci_iounmap(sc->pdev, sc->mem); 1964 pci_clear_master(sc->pdev); 1965 pci_release_region(sc->pdev, BAR_NUM); 1966 pci_disable_device(sc->pdev); 1967 } 1968 1969 static void hif_pci_deinit_pld(struct hif_pci_softc *sc) {} 1970 1971 static void hif_disable_pci(struct hif_pci_softc *sc) 1972 { 1973 struct hif_softc *ol_sc = HIF_GET_SOFTC(sc); 1974 1975 if (!ol_sc) { 1976 hif_err("ol_sc = NULL"); 1977 return; 1978 } 1979 hif_pci_device_reset(sc); 1980 sc->hif_pci_deinit(sc); 1981 1982 sc->mem = NULL; 1983 ol_sc->mem = NULL; 1984 } 1985 1986 static int hif_pci_probe_tgt_wakeup(struct hif_pci_softc *sc) 1987 { 1988 int ret = 0; 1989 int targ_awake_limit = 500; 1990 #ifndef QCA_WIFI_3_0 1991 uint32_t fw_indicator; 1992 #endif 1993 struct hif_softc *scn = HIF_GET_SOFTC(sc); 1994 1995 /* 1996 * Verify that the Target was started cleanly.* 1997 * The case where this is most likely is with an AUX-powered 1998 * Target and a Host in WoW mode. If the Host crashes, 1999 * loses power, or is restarted (without unloading the driver) 2000 * then the Target is left (aux) powered and running. On a 2001 * subsequent driver load, the Target is in an unexpected state. 2002 * We try to catch that here in order to reset the Target and 2003 * retry the probe. 2004 */ 2005 hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS + 2006 PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_V_MASK); 2007 while (!hif_targ_is_awake(scn, sc->mem)) { 2008 if (0 == targ_awake_limit) { 2009 hif_err("target awake timeout"); 2010 ret = -EAGAIN; 2011 goto end; 2012 } 2013 qdf_mdelay(1); 2014 targ_awake_limit--; 2015 } 2016 2017 #if PCIE_BAR0_READY_CHECKING 2018 { 2019 int wait_limit = 200; 2020 /* Synchronization point: wait the BAR0 is configured */ 2021 while (wait_limit-- && 2022 !(hif_read32_mb(sc, c->mem + 2023 PCIE_LOCAL_BASE_ADDRESS + 2024 PCIE_SOC_RDY_STATUS_ADDRESS) 2025 & PCIE_SOC_RDY_STATUS_BAR_MASK)) { 2026 qdf_mdelay(10); 2027 } 2028 if (wait_limit < 0) { 2029 /* AR6320v1 doesn't support checking of BAR0 2030 * configuration, takes one sec to wait BAR0 ready 2031 */ 2032 hif_debug("AR6320v1 waits two sec for BAR0"); 2033 } 2034 } 2035 #endif 2036 2037 #ifndef QCA_WIFI_3_0 2038 fw_indicator = hif_read32_mb(sc, sc->mem + FW_INDICATOR_ADDRESS); 2039 hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS + 2040 PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET); 2041 2042 if (fw_indicator & FW_IND_INITIALIZED) { 2043 hif_err("Target is in an unknown state. EAGAIN"); 2044 ret = -EAGAIN; 2045 goto end; 2046 } 2047 #endif 2048 2049 end: 2050 return ret; 2051 } 2052 2053 static int hif_pci_configure_legacy_irq(struct hif_pci_softc *sc) 2054 { 2055 int ret = 0; 2056 struct hif_softc *scn = HIF_GET_SOFTC(sc); 2057 uint32_t target_type = scn->target_info.target_type; 2058 2059 hif_info("E"); 2060 2061 /* do notn support MSI or MSI IRQ failed */ 2062 tasklet_init(&sc->intr_tq, wlan_tasklet, (unsigned long)sc); 2063 ret = request_irq(sc->pdev->irq, 2064 hif_pci_legacy_ce_interrupt_handler, IRQF_SHARED, 2065 "wlan_pci", sc); 2066 if (ret) { 2067 hif_err("request_irq failed, ret: %d", ret); 2068 goto end; 2069 } 2070 scn->wake_irq = sc->pdev->irq; 2071 /* Use sc->irq instead of sc->pdev-irq 2072 * platform_device pdev doesn't have an irq field 2073 */ 2074 sc->irq = sc->pdev->irq; 2075 /* Use Legacy PCI Interrupts */ 2076 hif_write32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS | 2077 PCIE_INTR_ENABLE_ADDRESS), 2078 HOST_GROUP0_MASK); 2079 hif_read32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS | 2080 PCIE_INTR_ENABLE_ADDRESS)); 2081 hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS + 2082 PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET); 2083 2084 if ((target_type == TARGET_TYPE_AR900B) || 2085 (target_type == TARGET_TYPE_QCA9984) || 2086 (target_type == TARGET_TYPE_AR9888) || 2087 (target_type == TARGET_TYPE_QCA9888) || 2088 (target_type == TARGET_TYPE_AR6320V1) || 2089 (target_type == TARGET_TYPE_AR6320V2) || 2090 (target_type == TARGET_TYPE_AR6320V3)) { 2091 hif_write32_mb(scn, scn->mem + PCIE_LOCAL_BASE_ADDRESS + 2092 PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_V_MASK); 2093 } 2094 end: 2095 QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_ERROR, 2096 "%s: X, ret = %d", __func__, ret); 2097 return ret; 2098 } 2099 2100 static int hif_ce_srng_free_irq(struct hif_softc *scn) 2101 { 2102 int ret = 0; 2103 int ce_id, irq; 2104 uint32_t msi_data_start; 2105 uint32_t msi_data_count; 2106 uint32_t msi_irq_start; 2107 struct HIF_CE_state *ce_sc = HIF_GET_CE_STATE(scn); 2108 struct CE_attr *host_ce_conf = ce_sc->host_ce_config; 2109 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 2110 2111 if (!pld_get_enable_intx(scn->qdf_dev->dev)) { 2112 ret = pld_get_user_msi_assignment(scn->qdf_dev->dev, "CE", 2113 &msi_data_count, 2114 &msi_data_start, 2115 &msi_irq_start); 2116 if (ret) 2117 return ret; 2118 } 2119 2120 /* needs to match the ce_id -> irq data mapping 2121 * used in the srng parameter configuration 2122 */ 2123 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 2124 if (host_ce_conf[ce_id].flags & CE_ATTR_DISABLE_INTR) 2125 continue; 2126 2127 if (!ce_sc->tasklets[ce_id].inited) 2128 continue; 2129 2130 irq = sc->ce_irq_num[ce_id]; 2131 2132 hif_irq_affinity_remove(irq); 2133 2134 hif_debug("%s: (ce_id %d, irq %d)", __func__, ce_id, irq); 2135 2136 pfrm_free_irq(scn->qdf_dev->dev, irq, &ce_sc->tasklets[ce_id]); 2137 } 2138 2139 return ret; 2140 } 2141 2142 void hif_pci_deconfigure_grp_irq(struct hif_softc *scn) 2143 { 2144 int i, j, irq; 2145 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2146 struct hif_exec_context *hif_ext_group; 2147 2148 for (i = 0; i < hif_state->hif_num_extgroup; i++) { 2149 hif_ext_group = hif_state->hif_ext_group[i]; 2150 if (hif_ext_group->irq_requested) { 2151 hif_ext_group->irq_requested = false; 2152 for (j = 0; j < hif_ext_group->numirq; j++) { 2153 irq = hif_ext_group->os_irq[j]; 2154 if (scn->irq_unlazy_disable) { 2155 qdf_dev_clear_irq_status_flags( 2156 irq, 2157 QDF_IRQ_DISABLE_UNLAZY); 2158 } 2159 hif_irq_affinity_remove(irq); 2160 pfrm_free_irq(scn->qdf_dev->dev, 2161 irq, hif_ext_group); 2162 } 2163 hif_ext_group->numirq = 0; 2164 } 2165 } 2166 } 2167 2168 /** 2169 * hif_pci_nointrs(): disable IRQ 2170 * @scn: struct hif_softc 2171 * 2172 * This function stops interrupt(s) 2173 * 2174 * Return: none 2175 */ 2176 void hif_pci_nointrs(struct hif_softc *scn) 2177 { 2178 int i, ret; 2179 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 2180 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2181 2182 scn->free_irq_done = true; 2183 ce_unregister_irq(hif_state, CE_ALL_BITMAP); 2184 2185 if (scn->request_irq_done == false) 2186 return; 2187 2188 hif_pci_deconfigure_grp_irq(scn); 2189 2190 ret = hif_ce_srng_free_irq(scn); 2191 if (ret != -EINVAL) { 2192 /* ce irqs freed in hif_ce_srng_free_irq */ 2193 2194 if (scn->wake_irq) 2195 pfrm_free_irq(scn->qdf_dev->dev, scn->wake_irq, scn); 2196 scn->wake_irq = 0; 2197 } else if (sc->num_msi_intrs > 0) { 2198 /* MSI interrupt(s) */ 2199 for (i = 0; i < sc->num_msi_intrs; i++) 2200 free_irq(sc->irq + i, sc); 2201 sc->num_msi_intrs = 0; 2202 } else { 2203 /* Legacy PCI line interrupt 2204 * Use sc->irq instead of sc->pdev-irq 2205 * platform_device pdev doesn't have an irq field 2206 */ 2207 free_irq(sc->irq, sc); 2208 } 2209 scn->request_irq_done = false; 2210 } 2211 2212 static inline 2213 bool hif_pci_default_link_up(struct hif_target_info *tgt_info) 2214 { 2215 if (ADRASTEA_BU && (tgt_info->target_type != TARGET_TYPE_QCN7605)) 2216 return true; 2217 else 2218 return false; 2219 } 2220 /** 2221 * hif_pci_disable_bus(): hif_disable_bus 2222 * @scn: hif context 2223 * 2224 * This function disables the bus 2225 * 2226 * Return: none 2227 */ 2228 void hif_pci_disable_bus(struct hif_softc *scn) 2229 { 2230 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 2231 struct pci_dev *pdev; 2232 void __iomem *mem; 2233 struct hif_target_info *tgt_info = &scn->target_info; 2234 2235 /* Attach did not succeed, all resources have been 2236 * freed in error handler 2237 */ 2238 if (!sc) 2239 return; 2240 2241 pdev = sc->pdev; 2242 if (hif_pci_default_link_up(tgt_info)) { 2243 hif_vote_link_down(GET_HIF_OPAQUE_HDL(scn)); 2244 2245 hif_write32_mb(sc, sc->mem + PCIE_INTR_ENABLE_ADDRESS, 0); 2246 hif_write32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS, 2247 HOST_GROUP0_MASK); 2248 } 2249 2250 #if defined(CPU_WARM_RESET_WAR) 2251 /* Currently CPU warm reset sequence is tested only for AR9888_REV2 2252 * Need to enable for AR9888_REV1 once CPU warm reset sequence is 2253 * verified for AR9888_REV1 2254 */ 2255 if ((tgt_info->target_version == AR9888_REV2_VERSION) || 2256 (tgt_info->target_version == AR9887_REV1_VERSION)) 2257 hif_pci_device_warm_reset(sc); 2258 else 2259 hif_pci_device_reset(sc); 2260 #else 2261 hif_pci_device_reset(sc); 2262 #endif 2263 mem = (void __iomem *)sc->mem; 2264 if (mem) { 2265 hif_dump_pipe_debug_count(scn); 2266 if (scn->athdiag_procfs_inited) { 2267 athdiag_procfs_remove(); 2268 scn->athdiag_procfs_inited = false; 2269 } 2270 sc->hif_pci_deinit(sc); 2271 scn->mem = NULL; 2272 } 2273 hif_info("X"); 2274 } 2275 2276 #define OL_ATH_PCI_PM_CONTROL 0x44 2277 2278 #ifdef CONFIG_PLD_PCIE_CNSS 2279 /** 2280 * hif_pci_prevent_linkdown(): allow or permit linkdown 2281 * @scn: hif context 2282 * @flag: true prevents linkdown, false allows 2283 * 2284 * Calls into the platform driver to vote against taking down the 2285 * pcie link. 2286 * 2287 * Return: n/a 2288 */ 2289 void hif_pci_prevent_linkdown(struct hif_softc *scn, bool flag) 2290 { 2291 int errno; 2292 2293 hif_info("wlan: %s pcie power collapse", flag ? "disable" : "enable"); 2294 hif_runtime_prevent_linkdown(scn, flag); 2295 2296 errno = pld_wlan_pm_control(scn->qdf_dev->dev, flag); 2297 if (errno) 2298 hif_err("Failed pld_wlan_pm_control; errno %d", errno); 2299 } 2300 #else 2301 void hif_pci_prevent_linkdown(struct hif_softc *scn, bool flag) 2302 { 2303 } 2304 #endif 2305 2306 #ifdef CONFIG_PCI_LOW_POWER_INT_REG 2307 /** 2308 * hif_pci_config_low_power_int_register() - configure pci low power 2309 * interrupt register. 2310 * @scn: hif context 2311 * @enable: true to enable the bits, false clear. 2312 * 2313 * Configure the bits INTR_L1SS and INTR_CLKPM of 2314 * PCIE_LOW_POWER_INT_MASK register. 2315 * 2316 * Return: n/a 2317 */ 2318 static void hif_pci_config_low_power_int_register(struct hif_softc *scn, 2319 bool enable) 2320 { 2321 void *address; 2322 uint32_t value; 2323 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 2324 struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); 2325 uint32_t target_type = tgt_info->target_type; 2326 2327 /* 2328 * Only configure the bits INTR_L1SS and INTR_CLKPM of 2329 * PCIE_LOW_POWER_INT_MASK register for QCA6174 for high 2330 * consumption issue. NFA344A power consumption is above 80mA 2331 * after entering Modern Standby. But the power will drop to normal 2332 * after PERST# de-assert. 2333 */ 2334 if ((target_type == TARGET_TYPE_AR6320) || 2335 (target_type == TARGET_TYPE_AR6320V1) || 2336 (target_type == TARGET_TYPE_AR6320V2) || 2337 (target_type == TARGET_TYPE_AR6320V3)) { 2338 hif_info("Configure PCI low power int mask register"); 2339 2340 address = scn->mem + PCIE_LOW_POWER_INT_MASK_OFFSET; 2341 2342 /* Configure bit3 INTR_L1SS */ 2343 value = hif_read32_mb(scn, address); 2344 if (enable) 2345 value |= INTR_L1SS; 2346 else 2347 value &= ~INTR_L1SS; 2348 hif_write32_mb(scn, address, value); 2349 2350 /* Configure bit4 INTR_CLKPM */ 2351 value = hif_read32_mb(scn, address); 2352 if (enable) 2353 value |= INTR_CLKPM; 2354 else 2355 value &= ~INTR_CLKPM; 2356 hif_write32_mb(scn, address, value); 2357 } 2358 } 2359 #else 2360 static inline void hif_pci_config_low_power_int_register(struct hif_softc *scn, 2361 bool enable) 2362 { 2363 } 2364 #endif 2365 2366 /** 2367 * hif_pci_bus_suspend(): prepare hif for suspend 2368 * @scn: hif context 2369 * 2370 * Return: Errno 2371 */ 2372 int hif_pci_bus_suspend(struct hif_softc *scn) 2373 { 2374 QDF_STATUS ret; 2375 2376 hif_apps_irqs_disable(GET_HIF_OPAQUE_HDL(scn)); 2377 2378 ret = hif_try_complete_tasks(scn); 2379 if (QDF_IS_STATUS_ERROR(ret)) { 2380 hif_apps_irqs_enable(GET_HIF_OPAQUE_HDL(scn)); 2381 return -EBUSY; 2382 } 2383 2384 /* 2385 * In an unlikely case, if draining becomes infinite loop, 2386 * it returns an error, shall abort the bus suspend. 2387 */ 2388 ret = hif_drain_fw_diag_ce(scn); 2389 if (ret) { 2390 hif_err("draining fw_diag_ce goes infinite, so abort suspend"); 2391 hif_apps_irqs_enable(GET_HIF_OPAQUE_HDL(scn)); 2392 return -EBUSY; 2393 } 2394 2395 /* Stop the HIF Sleep Timer */ 2396 hif_cancel_deferred_target_sleep(scn); 2397 2398 /* 2399 * Only need clear the bits INTR_L1SS/INTR_CLKPM after suspend. 2400 * No need do enable bits after resume, as firmware will restore 2401 * the bits after resume. 2402 */ 2403 hif_pci_config_low_power_int_register(scn, false); 2404 2405 scn->bus_suspended = true; 2406 2407 return 0; 2408 } 2409 2410 #ifdef PCI_LINK_STATUS_SANITY 2411 /** 2412 * __hif_check_link_status() - API to check if PCIe link is active/not 2413 * @scn: HIF Context 2414 * 2415 * API reads the PCIe config space to verify if PCIe link training is 2416 * successful or not. 2417 * 2418 * Return: Success/Failure 2419 */ 2420 static int __hif_check_link_status(struct hif_softc *scn) 2421 { 2422 uint16_t dev_id = 0; 2423 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 2424 struct hif_driver_state_callbacks *cbk = hif_get_callbacks_handle(scn); 2425 2426 if (!sc) { 2427 hif_err("HIF Bus Context is Invalid"); 2428 return -EINVAL; 2429 } 2430 2431 pfrm_read_config_word(sc->pdev, PCI_DEVICE_ID, &dev_id); 2432 2433 if (dev_id == sc->devid) 2434 return 0; 2435 2436 hif_err("Invalid PCIe Config Space; PCIe link down dev_id:0x%04x", 2437 dev_id); 2438 2439 scn->recovery = true; 2440 2441 if (cbk && cbk->set_recovery_in_progress) 2442 cbk->set_recovery_in_progress(cbk->context, true); 2443 else 2444 hif_err("Driver Global Recovery is not set"); 2445 2446 pld_is_pci_link_down(sc->dev); 2447 return -EACCES; 2448 } 2449 #else 2450 static inline int __hif_check_link_status(struct hif_softc *scn) 2451 { 2452 return 0; 2453 } 2454 #endif 2455 2456 2457 #ifdef HIF_BUS_LOG_INFO 2458 bool hif_log_pcie_info(struct hif_softc *scn, uint8_t *data, 2459 unsigned int *offset) 2460 { 2461 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 2462 struct hang_event_bus_info info = {0}; 2463 size_t size; 2464 2465 if (!sc) { 2466 hif_err("HIF Bus Context is Invalid"); 2467 return false; 2468 } 2469 2470 pfrm_read_config_word(sc->pdev, PCI_DEVICE_ID, &info.dev_id); 2471 2472 size = sizeof(info); 2473 QDF_HANG_EVT_SET_HDR(&info.tlv_header, HANG_EVT_TAG_BUS_INFO, 2474 size - QDF_HANG_EVENT_TLV_HDR_SIZE); 2475 2476 if (*offset + size > QDF_WLAN_HANG_FW_OFFSET) 2477 return false; 2478 2479 qdf_mem_copy(data + *offset, &info, size); 2480 *offset = *offset + size; 2481 2482 if (info.dev_id == sc->devid) 2483 return false; 2484 2485 qdf_recovery_reason_update(QCA_HANG_BUS_FAILURE); 2486 qdf_get_bus_reg_dump(scn->qdf_dev->dev, data, 2487 (QDF_WLAN_HANG_FW_OFFSET - size)); 2488 return true; 2489 } 2490 #endif 2491 2492 /** 2493 * hif_pci_bus_resume(): prepare hif for resume 2494 * @scn: hif context 2495 * 2496 * Return: Errno 2497 */ 2498 int hif_pci_bus_resume(struct hif_softc *scn) 2499 { 2500 int errno; 2501 2502 scn->bus_suspended = false; 2503 2504 errno = __hif_check_link_status(scn); 2505 if (errno) 2506 return errno; 2507 2508 hif_apps_irqs_enable(GET_HIF_OPAQUE_HDL(scn)); 2509 2510 return 0; 2511 } 2512 2513 /** 2514 * hif_pci_bus_suspend_noirq() - ensure there are no pending transactions 2515 * @scn: hif context 2516 * 2517 * Ensure that if we received the wakeup message before the irq 2518 * was disabled that the message is processed before suspending. 2519 * 2520 * Return: -EBUSY if we fail to flush the tasklets. 2521 */ 2522 int hif_pci_bus_suspend_noirq(struct hif_softc *scn) 2523 { 2524 if (hif_can_suspend_link(GET_HIF_OPAQUE_HDL(scn))) 2525 qdf_atomic_set(&scn->link_suspended, 1); 2526 2527 return 0; 2528 } 2529 2530 /** 2531 * hif_pci_bus_resume_noirq() - ensure there are no pending transactions 2532 * @scn: hif context 2533 * 2534 * Ensure that if we received the wakeup message before the irq 2535 * was disabled that the message is processed before suspending. 2536 * 2537 * Return: -EBUSY if we fail to flush the tasklets. 2538 */ 2539 int hif_pci_bus_resume_noirq(struct hif_softc *scn) 2540 { 2541 /* a vote for link up can come in the middle of the ongoing resume 2542 * process. hence, clear the link suspend flag once 2543 * hif_bus_resume_noirq() succeeds since PCIe link is already resumed 2544 * by this time 2545 */ 2546 qdf_atomic_set(&scn->link_suspended, 0); 2547 2548 return 0; 2549 } 2550 2551 #if CONFIG_PCIE_64BIT_MSI 2552 static void hif_free_msi_ctx(struct hif_softc *scn) 2553 { 2554 struct hif_pci_softc *sc = scn->hif_sc; 2555 struct hif_msi_info *info = &sc->msi_info; 2556 struct device *dev = scn->qdf_dev->dev; 2557 2558 OS_FREE_CONSISTENT(dev, 4, info->magic, info->magic_dma, 2559 OS_GET_DMA_MEM_CONTEXT(scn, dmacontext)); 2560 info->magic = NULL; 2561 info->magic_dma = 0; 2562 } 2563 #else 2564 static void hif_free_msi_ctx(struct hif_softc *scn) 2565 { 2566 } 2567 #endif 2568 2569 void hif_pci_disable_isr(struct hif_softc *scn) 2570 { 2571 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 2572 2573 hif_exec_kill(&scn->osc); 2574 hif_nointrs(scn); 2575 hif_free_msi_ctx(scn); 2576 /* Cancel the pending tasklet */ 2577 ce_tasklet_kill(scn); 2578 tasklet_kill(&sc->intr_tq); 2579 qdf_atomic_set(&scn->active_tasklet_cnt, 0); 2580 qdf_atomic_set(&scn->active_grp_tasklet_cnt, 0); 2581 } 2582 2583 /* Function to reset SoC */ 2584 void hif_pci_reset_soc(struct hif_softc *hif_sc) 2585 { 2586 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_sc); 2587 struct hif_opaque_softc *ol_sc = GET_HIF_OPAQUE_HDL(hif_sc); 2588 struct hif_target_info *tgt_info = hif_get_target_info_handle(ol_sc); 2589 2590 #if defined(CPU_WARM_RESET_WAR) 2591 /* Currently CPU warm reset sequence is tested only for AR9888_REV2 2592 * Need to enable for AR9888_REV1 once CPU warm reset sequence is 2593 * verified for AR9888_REV1 2594 */ 2595 if (tgt_info->target_version == AR9888_REV2_VERSION) 2596 hif_pci_device_warm_reset(sc); 2597 else 2598 hif_pci_device_reset(sc); 2599 #else 2600 hif_pci_device_reset(sc); 2601 #endif 2602 } 2603 2604 /** 2605 * hif_log_soc_wakeup_timeout() - API to log PCIe and SOC Info 2606 * @sc: HIF PCIe Context 2607 * 2608 * API to log PCIe Config space and SOC info when SOC wakeup timeout happens 2609 * 2610 * Return: Failure to caller 2611 */ 2612 static int hif_log_soc_wakeup_timeout(struct hif_pci_softc *sc) 2613 { 2614 uint16_t val = 0; 2615 uint32_t bar = 0; 2616 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(sc); 2617 struct hif_softc *scn = HIF_GET_SOFTC(sc); 2618 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(sc); 2619 struct hif_config_info *cfg = hif_get_ini_handle(hif_hdl); 2620 struct hif_driver_state_callbacks *cbk = hif_get_callbacks_handle(scn); 2621 A_target_id_t pci_addr = scn->mem; 2622 2623 hif_info("keep_awake_count = %d", hif_state->keep_awake_count); 2624 2625 pfrm_read_config_word(sc->pdev, PCI_VENDOR_ID, &val); 2626 2627 hif_info("PCI Vendor ID = 0x%04x", val); 2628 2629 pfrm_read_config_word(sc->pdev, PCI_DEVICE_ID, &val); 2630 2631 hif_info("PCI Device ID = 0x%04x", val); 2632 2633 pfrm_read_config_word(sc->pdev, PCI_COMMAND, &val); 2634 2635 hif_info("PCI Command = 0x%04x", val); 2636 2637 pfrm_read_config_word(sc->pdev, PCI_STATUS, &val); 2638 2639 hif_info("PCI Status = 0x%04x", val); 2640 2641 pfrm_read_config_dword(sc->pdev, PCI_BASE_ADDRESS_0, &bar); 2642 2643 hif_info("PCI BAR 0 = 0x%08x", bar); 2644 2645 hif_info("SOC_WAKE_ADDR 0%08x", 2646 hif_read32_mb(scn, pci_addr + PCIE_LOCAL_BASE_ADDRESS + 2647 PCIE_SOC_WAKE_ADDRESS)); 2648 2649 hif_info("RTC_STATE_ADDR 0x%08x", 2650 hif_read32_mb(scn, pci_addr + PCIE_LOCAL_BASE_ADDRESS + 2651 RTC_STATE_ADDRESS)); 2652 2653 hif_info("wakeup target"); 2654 2655 if (!cfg->enable_self_recovery) 2656 QDF_BUG(0); 2657 2658 scn->recovery = true; 2659 2660 if (cbk->set_recovery_in_progress) 2661 cbk->set_recovery_in_progress(cbk->context, true); 2662 2663 pld_is_pci_link_down(sc->dev); 2664 return -EACCES; 2665 } 2666 2667 /* 2668 * For now, we use simple on-demand sleep/wake. 2669 * Some possible improvements: 2670 * -Use the Host-destined A_INUM_PCIE_AWAKE interrupt rather than spin/delay 2671 * (or perhaps spin/delay for a short while, then convert to sleep/interrupt) 2672 * Careful, though, these functions may be used by 2673 * interrupt handlers ("atomic") 2674 * -Don't use host_reg_table for this code; instead use values directly 2675 * -Use a separate timer to track activity and allow Target to sleep only 2676 * if it hasn't done anything for a while; may even want to delay some 2677 * processing for a short while in order to "batch" (e.g.) transmit 2678 * requests with completion processing into "windows of up time". Costs 2679 * some performance, but improves power utilization. 2680 * -On some platforms, it might be possible to eliminate explicit 2681 * sleep/wakeup. Instead, take a chance that each access works OK. If not, 2682 * recover from the failure by forcing the Target awake. 2683 * -Change keep_awake_count to an atomic_t in order to avoid spin lock 2684 * overhead in some cases. Perhaps this makes more sense when 2685 * CONFIG_ATH_PCIE_ACCESS_LIKELY is used and less sense when LIKELY is 2686 * disabled. 2687 * -It is possible to compile this code out and simply force the Target 2688 * to remain awake. That would yield optimal performance at the cost of 2689 * increased power. See CONFIG_ATH_PCIE_MAX_PERF. 2690 * 2691 * Note: parameter wait_for_it has meaning only when waking (when sleep_ok==0). 2692 */ 2693 2694 /** 2695 * hif_pci_target_sleep_state_adjust() - on-demand sleep/wake 2696 * @scn: hif_softc pointer. 2697 * @sleep_ok: bool 2698 * @wait_for_it: bool 2699 * 2700 * Output the pipe error counts of each pipe to log file 2701 * 2702 * Return: int 2703 */ 2704 int hif_pci_target_sleep_state_adjust(struct hif_softc *scn, 2705 bool sleep_ok, bool wait_for_it) 2706 { 2707 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2708 A_target_id_t pci_addr = scn->mem; 2709 static int max_delay; 2710 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 2711 static int debug; 2712 if (scn->recovery) 2713 return -EACCES; 2714 2715 if (qdf_atomic_read(&scn->link_suspended)) { 2716 hif_err("Invalid access, PCIe link is down"); 2717 debug = true; 2718 QDF_ASSERT(0); 2719 return -EACCES; 2720 } 2721 2722 if (debug) { 2723 wait_for_it = true; 2724 hif_err("Invalid access, PCIe link is suspended"); 2725 QDF_ASSERT(0); 2726 } 2727 2728 if (sleep_ok) { 2729 qdf_spin_lock_irqsave(&hif_state->keep_awake_lock); 2730 hif_state->keep_awake_count--; 2731 if (hif_state->keep_awake_count == 0) { 2732 /* Allow sleep */ 2733 hif_state->verified_awake = false; 2734 hif_state->sleep_ticks = qdf_system_ticks(); 2735 } 2736 if (hif_state->fake_sleep == false) { 2737 /* Set the Fake Sleep */ 2738 hif_state->fake_sleep = true; 2739 2740 /* Start the Sleep Timer */ 2741 qdf_timer_stop(&hif_state->sleep_timer); 2742 qdf_timer_start(&hif_state->sleep_timer, 2743 HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS); 2744 } 2745 qdf_spin_unlock_irqrestore(&hif_state->keep_awake_lock); 2746 } else { 2747 qdf_spin_lock_irqsave(&hif_state->keep_awake_lock); 2748 2749 if (hif_state->fake_sleep) { 2750 hif_state->verified_awake = true; 2751 } else { 2752 if (hif_state->keep_awake_count == 0) { 2753 /* Force AWAKE */ 2754 hif_write32_mb(sc, pci_addr + 2755 PCIE_LOCAL_BASE_ADDRESS + 2756 PCIE_SOC_WAKE_ADDRESS, 2757 PCIE_SOC_WAKE_V_MASK); 2758 } 2759 } 2760 hif_state->keep_awake_count++; 2761 qdf_spin_unlock_irqrestore(&hif_state->keep_awake_lock); 2762 2763 if (wait_for_it && !hif_state->verified_awake) { 2764 #define PCIE_SLEEP_ADJUST_TIMEOUT 8000 /* 8Ms */ 2765 int tot_delay = 0; 2766 int curr_delay = 5; 2767 2768 for (;; ) { 2769 if (hif_targ_is_awake(scn, pci_addr)) { 2770 hif_state->verified_awake = true; 2771 break; 2772 } 2773 if (!hif_pci_targ_is_present(scn, pci_addr)) 2774 break; 2775 if (tot_delay > PCIE_SLEEP_ADJUST_TIMEOUT) 2776 return hif_log_soc_wakeup_timeout(sc); 2777 2778 OS_DELAY(curr_delay); 2779 tot_delay += curr_delay; 2780 2781 if (curr_delay < 50) 2782 curr_delay += 5; 2783 } 2784 2785 /* 2786 * NB: If Target has to come out of Deep Sleep, 2787 * this may take a few Msecs. Typically, though 2788 * this delay should be <30us. 2789 */ 2790 if (tot_delay > max_delay) 2791 max_delay = tot_delay; 2792 } 2793 } 2794 2795 if (debug && hif_state->verified_awake) { 2796 debug = 0; 2797 hif_err("INTR_ENABLE_REG = 0x%08x, INTR_CAUSE_REG = 0x%08x, CPU_INTR_REG = 0x%08x, INTR_CLR_REG = 0x%08x, CE_INTERRUPT_SUMMARY_REG = 0x%08x", 2798 hif_read32_mb(sc, sc->mem + SOC_CORE_BASE_ADDRESS + 2799 PCIE_INTR_ENABLE_ADDRESS), 2800 hif_read32_mb(sc, sc->mem + SOC_CORE_BASE_ADDRESS + 2801 PCIE_INTR_CAUSE_ADDRESS), 2802 hif_read32_mb(sc, sc->mem + SOC_CORE_BASE_ADDRESS + 2803 CPU_INTR_ADDRESS), 2804 hif_read32_mb(sc, sc->mem + SOC_CORE_BASE_ADDRESS + 2805 PCIE_INTR_CLR_ADDRESS), 2806 hif_read32_mb(sc, sc->mem + CE_WRAPPER_BASE_ADDRESS + 2807 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)); 2808 } 2809 2810 return 0; 2811 } 2812 2813 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 2814 uint32_t hif_target_read_checked(struct hif_softc *scn, uint32_t offset) 2815 { 2816 uint32_t value; 2817 void *addr; 2818 2819 addr = scn->mem + offset; 2820 value = hif_read32_mb(scn, addr); 2821 2822 { 2823 unsigned long irq_flags; 2824 int idx = pcie_access_log_seqnum % PCIE_ACCESS_LOG_NUM; 2825 2826 spin_lock_irqsave(&pcie_access_log_lock, irq_flags); 2827 pcie_access_log[idx].seqnum = pcie_access_log_seqnum; 2828 pcie_access_log[idx].is_write = false; 2829 pcie_access_log[idx].addr = addr; 2830 pcie_access_log[idx].value = value; 2831 pcie_access_log_seqnum++; 2832 spin_unlock_irqrestore(&pcie_access_log_lock, irq_flags); 2833 } 2834 2835 return value; 2836 } 2837 2838 void 2839 hif_target_write_checked(struct hif_softc *scn, uint32_t offset, uint32_t value) 2840 { 2841 void *addr; 2842 2843 addr = scn->mem + (offset); 2844 hif_write32_mb(scn, addr, value); 2845 2846 { 2847 unsigned long irq_flags; 2848 int idx = pcie_access_log_seqnum % PCIE_ACCESS_LOG_NUM; 2849 2850 spin_lock_irqsave(&pcie_access_log_lock, irq_flags); 2851 pcie_access_log[idx].seqnum = pcie_access_log_seqnum; 2852 pcie_access_log[idx].is_write = true; 2853 pcie_access_log[idx].addr = addr; 2854 pcie_access_log[idx].value = value; 2855 pcie_access_log_seqnum++; 2856 spin_unlock_irqrestore(&pcie_access_log_lock, irq_flags); 2857 } 2858 } 2859 2860 /** 2861 * hif_target_dump_access_log() - dump access log 2862 * 2863 * dump access log 2864 * 2865 * Return: n/a 2866 */ 2867 void hif_target_dump_access_log(void) 2868 { 2869 int idx, len, start_idx, cur_idx; 2870 unsigned long irq_flags; 2871 2872 spin_lock_irqsave(&pcie_access_log_lock, irq_flags); 2873 if (pcie_access_log_seqnum > PCIE_ACCESS_LOG_NUM) { 2874 len = PCIE_ACCESS_LOG_NUM; 2875 start_idx = pcie_access_log_seqnum % PCIE_ACCESS_LOG_NUM; 2876 } else { 2877 len = pcie_access_log_seqnum; 2878 start_idx = 0; 2879 } 2880 2881 for (idx = 0; idx < len; idx++) { 2882 cur_idx = (start_idx + idx) % PCIE_ACCESS_LOG_NUM; 2883 hif_debug("idx:%d sn:%u wr:%d addr:%pK val:%u", 2884 idx, 2885 pcie_access_log[cur_idx].seqnum, 2886 pcie_access_log[cur_idx].is_write, 2887 pcie_access_log[cur_idx].addr, 2888 pcie_access_log[cur_idx].value); 2889 } 2890 2891 pcie_access_log_seqnum = 0; 2892 spin_unlock_irqrestore(&pcie_access_log_lock, irq_flags); 2893 } 2894 #endif 2895 2896 #ifndef HIF_AHB 2897 int hif_ahb_configure_irq(struct hif_pci_softc *sc) 2898 { 2899 QDF_BUG(0); 2900 return -EINVAL; 2901 } 2902 #endif 2903 2904 static irqreturn_t hif_ce_interrupt_handler(int irq, void *context) 2905 { 2906 struct ce_tasklet_entry *tasklet_entry = context; 2907 return ce_dispatch_interrupt(tasklet_entry->ce_id, tasklet_entry); 2908 } 2909 extern const char *ce_name[]; 2910 2911 static int hif_ce_msi_map_ce_to_irq(struct hif_softc *scn, int ce_id) 2912 { 2913 struct hif_pci_softc *pci_scn = HIF_GET_PCI_SOFTC(scn); 2914 2915 return pci_scn->ce_irq_num[ce_id]; 2916 } 2917 2918 /* hif_srng_msi_irq_disable() - disable the irq for msi 2919 * @hif_sc: hif context 2920 * @ce_id: which ce to disable copy complete interrupts for 2921 * 2922 * since MSI interrupts are not level based, the system can function 2923 * without disabling these interrupts. Interrupt mitigation can be 2924 * added here for better system performance. 2925 */ 2926 static void hif_ce_srng_msi_irq_disable(struct hif_softc *hif_sc, int ce_id) 2927 { 2928 pfrm_disable_irq_nosync(hif_sc->qdf_dev->dev, 2929 hif_ce_msi_map_ce_to_irq(hif_sc, ce_id)); 2930 } 2931 2932 static void hif_ce_srng_msi_irq_enable(struct hif_softc *hif_sc, int ce_id) 2933 { 2934 if (__hif_check_link_status(hif_sc)) 2935 return; 2936 2937 pfrm_enable_irq(hif_sc->qdf_dev->dev, 2938 hif_ce_msi_map_ce_to_irq(hif_sc, ce_id)); 2939 } 2940 2941 static void hif_ce_legacy_msi_irq_disable(struct hif_softc *hif_sc, int ce_id) 2942 { 2943 disable_irq_nosync(hif_ce_msi_map_ce_to_irq(hif_sc, ce_id)); 2944 } 2945 2946 static void hif_ce_legacy_msi_irq_enable(struct hif_softc *hif_sc, int ce_id) 2947 { 2948 enable_irq(hif_ce_msi_map_ce_to_irq(hif_sc, ce_id)); 2949 } 2950 2951 #ifdef QCA_SUPPORT_LEGACY_INTERRUPTS 2952 /** 2953 * hif_ce_configure_legacyirq() - Configure CE interrupts 2954 * @scn: hif_softc pointer 2955 * 2956 * Configure CE legacy interrupts 2957 * 2958 * Return: int 2959 */ 2960 static int hif_ce_configure_legacyirq(struct hif_softc *scn) 2961 { 2962 int ret = 0; 2963 int irq, ce_id; 2964 struct HIF_CE_state *ce_sc = HIF_GET_CE_STATE(scn); 2965 struct CE_attr *host_ce_conf = ce_sc->host_ce_config; 2966 struct hif_pci_softc *pci_sc = HIF_GET_PCI_SOFTC(scn); 2967 int pci_slot; 2968 qdf_device_t qdf_dev = scn->qdf_dev; 2969 2970 if (!pld_get_enable_intx(scn->qdf_dev->dev)) 2971 return -EINVAL; 2972 2973 scn->bus_ops.hif_irq_disable = &hif_ce_srng_msi_irq_disable; 2974 scn->bus_ops.hif_irq_enable = &hif_ce_srng_msi_irq_enable; 2975 scn->bus_ops.hif_map_ce_to_irq = &hif_ce_msi_map_ce_to_irq; 2976 2977 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 2978 if (host_ce_conf[ce_id].flags & CE_ATTR_DISABLE_INTR) 2979 continue; 2980 2981 if (host_ce_conf[ce_id].flags & CE_ATTR_INIT_ON_DEMAND) 2982 continue; 2983 2984 ret = pfrm_get_irq(scn->qdf_dev->dev, 2985 (struct qdf_pfm_hndl *)qdf_dev->cnss_pdev, 2986 legacy_ic_irqname[ce_id], ce_id, &irq); 2987 if (ret) { 2988 dev_err(scn->qdf_dev->dev, "get irq failed\n"); 2989 ret = -EFAULT; 2990 goto skip; 2991 } 2992 2993 pci_slot = hif_get_pci_slot(scn); 2994 qdf_scnprintf(ce_irqname[pci_slot][ce_id], 2995 DP_IRQ_NAME_LEN, "pci%d_ce_%u", pci_slot, ce_id); 2996 pci_sc->ce_irq_num[ce_id] = irq; 2997 2998 ret = pfrm_request_irq(scn->qdf_dev->dev, irq, 2999 hif_ce_interrupt_handler, 3000 IRQF_SHARED, 3001 ce_irqname[pci_slot][ce_id], 3002 &ce_sc->tasklets[ce_id]); 3003 if (ret) { 3004 hif_err("error = %d", ret); 3005 return -EINVAL; 3006 } 3007 } 3008 3009 skip: 3010 return ret; 3011 } 3012 #else 3013 /** 3014 * hif_ce_configure_legacyirq() - Configure CE interrupts 3015 * @scn: hif_softc pointer 3016 * 3017 * Configure CE legacy interrupts 3018 * 3019 * Return: int 3020 */ 3021 static int hif_ce_configure_legacyirq(struct hif_softc *scn) 3022 { 3023 return 0; 3024 } 3025 #endif 3026 3027 int hif_ce_msi_configure_irq_by_ceid(struct hif_softc *scn, int ce_id) 3028 { 3029 int ret = 0; 3030 int irq; 3031 uint32_t msi_data_start; 3032 uint32_t msi_data_count; 3033 unsigned int msi_data; 3034 int irq_id; 3035 uint32_t msi_irq_start; 3036 struct HIF_CE_state *ce_sc = HIF_GET_CE_STATE(scn); 3037 struct hif_pci_softc *pci_sc = HIF_GET_PCI_SOFTC(scn); 3038 int pci_slot; 3039 unsigned long irq_flags; 3040 3041 if (ce_id >= CE_COUNT_MAX) 3042 return -EINVAL; 3043 3044 /* do ce irq assignments */ 3045 ret = pld_get_user_msi_assignment(scn->qdf_dev->dev, "CE", 3046 &msi_data_count, &msi_data_start, 3047 &msi_irq_start); 3048 3049 if (ret) { 3050 hif_err("Failed to get CE msi config"); 3051 return -EINVAL; 3052 } 3053 3054 irq_id = scn->int_assignment->msi_idx[ce_id]; 3055 /* needs to match the ce_id -> irq data mapping 3056 * used in the srng parameter configuration 3057 */ 3058 pci_slot = hif_get_pci_slot(scn); 3059 msi_data = irq_id + msi_irq_start; 3060 irq = pld_get_msi_irq(scn->qdf_dev->dev, msi_data); 3061 if (pld_is_one_msi(scn->qdf_dev->dev)) 3062 irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 3063 else 3064 irq_flags = IRQF_SHARED; 3065 hif_debug("%s: (ce_id %d, irq_id %d, msi_data %d, irq %d flag 0x%lx tasklet %pK)", 3066 __func__, ce_id, irq_id, msi_data, irq, irq_flags, 3067 &ce_sc->tasklets[ce_id]); 3068 3069 /* implies the ce is also initialized */ 3070 if (!ce_sc->tasklets[ce_id].inited) 3071 goto skip; 3072 3073 pci_sc->ce_irq_num[ce_id] = irq; 3074 3075 hif_affinity_mgr_init_ce_irq(scn, ce_id, irq); 3076 3077 qdf_scnprintf(ce_irqname[pci_slot][ce_id], 3078 DP_IRQ_NAME_LEN, "pci%u_wlan_ce_%u", 3079 pci_slot, ce_id); 3080 3081 ret = pfrm_request_irq(scn->qdf_dev->dev, 3082 irq, hif_ce_interrupt_handler, irq_flags, 3083 ce_irqname[pci_slot][ce_id], 3084 &ce_sc->tasklets[ce_id]); 3085 if (ret) 3086 return -EINVAL; 3087 3088 skip: 3089 return ret; 3090 } 3091 3092 static int hif_ce_msi_configure_irq(struct hif_softc *scn) 3093 { 3094 int ret; 3095 int ce_id, irq; 3096 uint32_t msi_data_start; 3097 uint32_t msi_data_count; 3098 uint32_t msi_irq_start; 3099 struct HIF_CE_state *ce_sc = HIF_GET_CE_STATE(scn); 3100 struct CE_attr *host_ce_conf = ce_sc->host_ce_config; 3101 3102 if (!scn->ini_cfg.disable_wake_irq) { 3103 /* do wake irq assignment */ 3104 ret = pld_get_user_msi_assignment(scn->qdf_dev->dev, "WAKE", 3105 &msi_data_count, 3106 &msi_data_start, 3107 &msi_irq_start); 3108 if (ret) 3109 return ret; 3110 3111 scn->wake_irq = pld_get_msi_irq(scn->qdf_dev->dev, 3112 msi_irq_start); 3113 scn->wake_irq_type = HIF_PM_MSI_WAKE; 3114 3115 ret = pfrm_request_irq(scn->qdf_dev->dev, scn->wake_irq, 3116 hif_wake_interrupt_handler, 3117 IRQF_NO_SUSPEND, "wlan_wake_irq", scn); 3118 3119 if (ret) 3120 return ret; 3121 } 3122 3123 /* do ce irq assignments */ 3124 ret = pld_get_user_msi_assignment(scn->qdf_dev->dev, "CE", 3125 &msi_data_count, &msi_data_start, 3126 &msi_irq_start); 3127 if (ret) 3128 goto free_wake_irq; 3129 3130 if (ce_srng_based(scn)) { 3131 scn->bus_ops.hif_irq_disable = &hif_ce_srng_msi_irq_disable; 3132 scn->bus_ops.hif_irq_enable = &hif_ce_srng_msi_irq_enable; 3133 } else { 3134 scn->bus_ops.hif_irq_disable = &hif_ce_legacy_msi_irq_disable; 3135 scn->bus_ops.hif_irq_enable = &hif_ce_legacy_msi_irq_enable; 3136 } 3137 3138 scn->bus_ops.hif_map_ce_to_irq = &hif_ce_msi_map_ce_to_irq; 3139 3140 /* needs to match the ce_id -> irq data mapping 3141 * used in the srng parameter configuration 3142 */ 3143 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 3144 if (host_ce_conf[ce_id].flags & CE_ATTR_DISABLE_INTR) 3145 continue; 3146 3147 if (host_ce_conf[ce_id].flags & CE_ATTR_INIT_ON_DEMAND) 3148 continue; 3149 3150 ret = hif_ce_msi_configure_irq_by_ceid(scn, ce_id); 3151 if (ret) 3152 goto free_irq; 3153 } 3154 3155 return ret; 3156 3157 free_irq: 3158 /* the request_irq for the last ce_id failed so skip it. */ 3159 while (ce_id > 0 && ce_id < scn->ce_count) { 3160 unsigned int msi_data; 3161 3162 ce_id--; 3163 msi_data = (ce_id % msi_data_count) + msi_irq_start; 3164 irq = pld_get_msi_irq(scn->qdf_dev->dev, msi_data); 3165 pfrm_free_irq(scn->qdf_dev->dev, 3166 irq, &ce_sc->tasklets[ce_id]); 3167 } 3168 3169 free_wake_irq: 3170 if (!scn->ini_cfg.disable_wake_irq) { 3171 pfrm_free_irq(scn->qdf_dev->dev, 3172 scn->wake_irq, scn->qdf_dev->dev); 3173 scn->wake_irq = 0; 3174 scn->wake_irq_type = HIF_PM_INVALID_WAKE; 3175 } 3176 3177 return ret; 3178 } 3179 3180 static void hif_exec_grp_irq_disable(struct hif_exec_context *hif_ext_group) 3181 { 3182 int i; 3183 struct hif_softc *scn = HIF_GET_SOFTC(hif_ext_group->hif); 3184 3185 for (i = 0; i < hif_ext_group->numirq; i++) 3186 pfrm_disable_irq_nosync(scn->qdf_dev->dev, 3187 hif_ext_group->os_irq[i]); 3188 } 3189 3190 static void hif_exec_grp_irq_enable(struct hif_exec_context *hif_ext_group) 3191 { 3192 int i; 3193 struct hif_softc *scn = HIF_GET_SOFTC(hif_ext_group->hif); 3194 3195 for (i = 0; i < hif_ext_group->numirq; i++) 3196 pfrm_enable_irq(scn->qdf_dev->dev, hif_ext_group->os_irq[i]); 3197 } 3198 3199 /** 3200 * hif_pci_get_irq_name() - get irqname 3201 * This function gives irqnumber to irqname 3202 * mapping. 3203 * 3204 * @irq_no: irq number 3205 * 3206 * Return: irq name 3207 */ 3208 const char *hif_pci_get_irq_name(int irq_no) 3209 { 3210 return "pci-dummy"; 3211 } 3212 3213 #if defined(FEATURE_IRQ_AFFINITY) || defined(HIF_CPU_PERF_AFFINE_MASK) 3214 void hif_pci_irq_set_affinity_hint(struct hif_exec_context *hif_ext_group, 3215 bool perf) 3216 { 3217 int i, ret; 3218 unsigned int cpus; 3219 bool mask_set = false; 3220 int package_id; 3221 int cpu_cluster = perf ? hif_get_perf_cluster_bitmap() : 3222 BIT(CPU_CLUSTER_TYPE_LITTLE); 3223 3224 for (i = 0; i < hif_ext_group->numirq; i++) 3225 qdf_cpumask_clear(&hif_ext_group->new_cpu_mask[i]); 3226 3227 for (i = 0; i < hif_ext_group->numirq; i++) { 3228 qdf_for_each_online_cpu(cpus) { 3229 package_id = qdf_topology_physical_package_id(cpus); 3230 if (package_id >= 0 && BIT(package_id) & cpu_cluster) { 3231 qdf_cpumask_set_cpu(cpus, 3232 &hif_ext_group-> 3233 new_cpu_mask[i]); 3234 mask_set = true; 3235 } 3236 } 3237 } 3238 for (i = 0; i < hif_ext_group->numirq; i++) { 3239 if (mask_set) { 3240 ret = hif_affinity_mgr_set_qrg_irq_affinity((struct hif_softc *)hif_ext_group->hif, 3241 hif_ext_group->os_irq[i], 3242 hif_ext_group->grp_id, i, 3243 &hif_ext_group->new_cpu_mask[i]); 3244 if (ret) 3245 qdf_debug("Set affinity %*pbl fails for IRQ %d ", 3246 qdf_cpumask_pr_args(&hif_ext_group-> 3247 new_cpu_mask[i]), 3248 hif_ext_group->os_irq[i]); 3249 } else { 3250 qdf_debug("Offline CPU: Set affinity fails for IRQ: %d", 3251 hif_ext_group->os_irq[i]); 3252 } 3253 } 3254 } 3255 #endif 3256 3257 #ifdef HIF_CPU_PERF_AFFINE_MASK 3258 void hif_pci_ce_irq_set_affinity_hint(struct hif_softc *scn) 3259 { 3260 int ret; 3261 unsigned int cpus; 3262 struct HIF_CE_state *ce_sc = HIF_GET_CE_STATE(scn); 3263 struct hif_pci_softc *pci_sc = HIF_GET_PCI_SOFTC(scn); 3264 struct CE_attr *host_ce_conf; 3265 int ce_id; 3266 qdf_cpu_mask ce_cpu_mask, updated_mask; 3267 int perf_cpu_cluster = hif_get_perf_cluster_bitmap(); 3268 int package_id; 3269 3270 host_ce_conf = ce_sc->host_ce_config; 3271 qdf_cpumask_clear(&ce_cpu_mask); 3272 3273 qdf_for_each_online_cpu(cpus) { 3274 package_id = qdf_topology_physical_package_id(cpus); 3275 if (package_id >= 0 && BIT(package_id) & perf_cpu_cluster) { 3276 qdf_cpumask_set_cpu(cpus, 3277 &ce_cpu_mask); 3278 } else { 3279 hif_err_rl("Unable to set cpu mask for offline CPU %d" 3280 , cpus); 3281 } 3282 } 3283 if (qdf_cpumask_empty(&ce_cpu_mask)) { 3284 hif_err_rl("Empty cpu_mask, unable to set CE IRQ affinity"); 3285 return; 3286 } 3287 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 3288 if (host_ce_conf[ce_id].flags & CE_ATTR_DISABLE_INTR) 3289 continue; 3290 qdf_cpumask_copy(&updated_mask, &ce_cpu_mask); 3291 ret = hif_affinity_mgr_set_ce_irq_affinity(scn, pci_sc->ce_irq_num[ce_id], 3292 ce_id, 3293 &updated_mask); 3294 qdf_cpumask_clear(&pci_sc->ce_irq_cpu_mask[ce_id]); 3295 qdf_cpumask_copy(&pci_sc->ce_irq_cpu_mask[ce_id], 3296 &updated_mask); 3297 if (ret) 3298 hif_err_rl("Set affinity %*pbl fails for CE IRQ %d", 3299 qdf_cpumask_pr_args( 3300 &pci_sc->ce_irq_cpu_mask[ce_id]), 3301 pci_sc->ce_irq_num[ce_id]); 3302 else 3303 hif_debug_rl("Set affinity %*pbl for CE IRQ: %d", 3304 qdf_cpumask_pr_args( 3305 &pci_sc->ce_irq_cpu_mask[ce_id]), 3306 pci_sc->ce_irq_num[ce_id]); 3307 } 3308 } 3309 #endif /* #ifdef HIF_CPU_PERF_AFFINE_MASK */ 3310 3311 #ifdef HIF_CPU_CLEAR_AFFINITY 3312 void hif_pci_config_irq_clear_cpu_affinity(struct hif_softc *scn, 3313 int intr_ctxt_id, int cpu) 3314 { 3315 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3316 struct hif_exec_context *hif_ext_group; 3317 int i, ret; 3318 3319 if (intr_ctxt_id < hif_state->hif_num_extgroup) { 3320 hif_ext_group = hif_state->hif_ext_group[intr_ctxt_id]; 3321 3322 for (i = 0; i < hif_ext_group->numirq; i++) { 3323 qdf_cpumask_setall(&hif_ext_group->new_cpu_mask[i]); 3324 qdf_cpumask_clear_cpu(cpu, 3325 &hif_ext_group->new_cpu_mask[i]); 3326 ret = hif_affinity_mgr_set_qrg_irq_affinity((struct hif_softc *)hif_ext_group->hif, 3327 hif_ext_group->os_irq[i], 3328 hif_ext_group->grp_id, i, 3329 &hif_ext_group->new_cpu_mask[i]); 3330 if (ret) 3331 hif_err("Set affinity %*pbl fails for IRQ %d ", 3332 qdf_cpumask_pr_args(&hif_ext_group-> 3333 new_cpu_mask[i]), 3334 hif_ext_group->os_irq[i]); 3335 else 3336 hif_debug("Set affinity %*pbl for IRQ: %d", 3337 qdf_cpumask_pr_args(&hif_ext_group-> 3338 new_cpu_mask[i]), 3339 hif_ext_group->os_irq[i]); 3340 } 3341 } 3342 } 3343 #endif 3344 3345 void hif_pci_config_irq_affinity(struct hif_softc *scn) 3346 { 3347 int i; 3348 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3349 struct hif_exec_context *hif_ext_group; 3350 3351 hif_core_ctl_set_boost(true); 3352 /* Set IRQ affinity for WLAN DP interrupts*/ 3353 for (i = 0; i < hif_state->hif_num_extgroup; i++) { 3354 hif_ext_group = hif_state->hif_ext_group[i]; 3355 hif_pci_irq_set_affinity_hint(hif_ext_group, true); 3356 } 3357 /* Set IRQ affinity for CE interrupts*/ 3358 hif_pci_ce_irq_set_affinity_hint(scn); 3359 } 3360 3361 #ifdef QCA_SUPPORT_LEGACY_INTERRUPTS 3362 /** 3363 * hif_grp_configure_legacyirq() - Configure DP interrupts 3364 * @scn: hif_softc pointer 3365 * @hif_ext_group: hif extended group pointer 3366 * 3367 * Configure DP legacy interrupts 3368 * 3369 * Return: int 3370 */ 3371 static int hif_grp_configure_legacyirq(struct hif_softc *scn, 3372 struct hif_exec_context *hif_ext_group) 3373 { 3374 int ret = 0; 3375 int irq = 0; 3376 int j; 3377 int pci_slot; 3378 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 3379 struct pci_dev *pdev = sc->pdev; 3380 qdf_device_t qdf_dev = scn->qdf_dev; 3381 3382 for (j = 0; j < hif_ext_group->numirq; j++) { 3383 ret = pfrm_get_irq(&pdev->dev, 3384 (struct qdf_pfm_hndl *)qdf_dev->cnss_pdev, 3385 legacy_ic_irqname[hif_ext_group->irq[j]], 3386 hif_ext_group->irq[j], &irq); 3387 if (ret) { 3388 dev_err(&pdev->dev, "get irq failed\n"); 3389 return -EFAULT; 3390 } 3391 hif_ext_group->os_irq[j] = irq; 3392 } 3393 3394 hif_ext_group->irq_enable = &hif_exec_grp_irq_enable; 3395 hif_ext_group->irq_disable = &hif_exec_grp_irq_disable; 3396 hif_ext_group->irq_name = &hif_pci_get_irq_name; 3397 hif_ext_group->work_complete = &hif_dummy_grp_done; 3398 3399 pci_slot = hif_get_pci_slot(scn); 3400 for (j = 0; j < hif_ext_group->numirq; j++) { 3401 irq = hif_ext_group->os_irq[j]; 3402 if (scn->irq_unlazy_disable) 3403 qdf_dev_set_irq_status_flags(irq, 3404 QDF_IRQ_DISABLE_UNLAZY); 3405 3406 hif_debug("request_irq = %d for grp %d", 3407 irq, hif_ext_group->grp_id); 3408 3409 qdf_scnprintf(dp_legacy_irqname[pci_slot][hif_ext_group->irq[j]], 3410 DP_IRQ_NAME_LEN, "pci%u_%s", pci_slot, 3411 legacy_ic_irqname[hif_ext_group->irq[j]]); 3412 3413 ret = pfrm_request_irq(scn->qdf_dev->dev, irq, 3414 hif_ext_group_interrupt_handler, 3415 IRQF_SHARED | IRQF_NO_SUSPEND, 3416 dp_legacy_irqname[pci_slot][hif_ext_group->irq[j]], 3417 hif_ext_group); 3418 if (ret) { 3419 hif_err("request_irq failed ret = %d", ret); 3420 return -EFAULT; 3421 } 3422 hif_ext_group->os_irq[j] = irq; 3423 } 3424 hif_ext_group->irq_requested = true; 3425 return 0; 3426 } 3427 #else 3428 /** 3429 * hif_grp_configure_legacyirq() - Configure DP interrupts 3430 * @scn: hif_softc pointer 3431 * @hif_ext_group: hif extended group pointer 3432 * 3433 * Configure DP legacy interrupts 3434 * 3435 * Return: int 3436 */ 3437 static int hif_grp_configure_legacyirq(struct hif_softc *scn, 3438 struct hif_exec_context *hif_ext_group) 3439 { 3440 return 0; 3441 } 3442 #endif 3443 3444 int hif_pci_configure_grp_irq(struct hif_softc *scn, 3445 struct hif_exec_context *hif_ext_group) 3446 { 3447 int ret = 0; 3448 int irq = 0; 3449 int j; 3450 int pci_slot; 3451 unsigned long irq_flags; 3452 3453 if (pld_get_enable_intx(scn->qdf_dev->dev)) 3454 return hif_grp_configure_legacyirq(scn, hif_ext_group); 3455 3456 hif_ext_group->irq_enable = &hif_exec_grp_irq_enable; 3457 hif_ext_group->irq_disable = &hif_exec_grp_irq_disable; 3458 hif_ext_group->irq_name = &hif_pci_get_irq_name; 3459 hif_ext_group->work_complete = &hif_dummy_grp_done; 3460 3461 pci_slot = hif_get_pci_slot(scn); 3462 for (j = 0; j < hif_ext_group->numirq; j++) { 3463 irq = hif_ext_group->irq[j]; 3464 if (scn->irq_unlazy_disable) 3465 qdf_dev_set_irq_status_flags(irq, 3466 QDF_IRQ_DISABLE_UNLAZY); 3467 3468 if (pld_is_one_msi(scn->qdf_dev->dev)) 3469 irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 3470 else 3471 irq_flags = IRQF_SHARED | IRQF_NO_SUSPEND; 3472 hif_debug("request_irq = %d for grp %d irq_flags 0x%lx", 3473 irq, hif_ext_group->grp_id, irq_flags); 3474 3475 qdf_scnprintf(dp_irqname[pci_slot][hif_ext_group->grp_id], 3476 DP_IRQ_NAME_LEN, "pci%u_wlan_grp_dp_%u", 3477 pci_slot, hif_ext_group->grp_id); 3478 ret = pfrm_request_irq( 3479 scn->qdf_dev->dev, irq, 3480 hif_ext_group_interrupt_handler, 3481 irq_flags, 3482 dp_irqname[pci_slot][hif_ext_group->grp_id], 3483 hif_ext_group); 3484 if (ret) { 3485 hif_err("request_irq failed ret = %d", ret); 3486 return -EFAULT; 3487 } 3488 hif_ext_group->os_irq[j] = irq; 3489 hif_affinity_mgr_init_grp_irq(scn, hif_ext_group->grp_id, 3490 j, irq); 3491 } 3492 hif_ext_group->irq_requested = true; 3493 return 0; 3494 } 3495 3496 #ifdef FEATURE_IRQ_AFFINITY 3497 void hif_pci_set_grp_intr_affinity(struct hif_softc *scn, 3498 uint32_t grp_intr_bitmask, bool perf) 3499 { 3500 int i; 3501 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3502 struct hif_exec_context *hif_ext_group; 3503 3504 for (i = 0; i < hif_state->hif_num_extgroup; i++) { 3505 if (!(grp_intr_bitmask & BIT(i))) 3506 continue; 3507 3508 hif_ext_group = hif_state->hif_ext_group[i]; 3509 hif_pci_irq_set_affinity_hint(hif_ext_group, perf); 3510 qdf_atomic_set(&hif_ext_group->force_napi_complete, -1); 3511 } 3512 } 3513 #endif 3514 3515 #if (defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 3516 defined(QCA_WIFI_KIWI)) 3517 uint32_t hif_pci_reg_read32(struct hif_softc *hif_sc, 3518 uint32_t offset) 3519 { 3520 return hal_read32_mb(hif_sc->hal_soc, offset); 3521 } 3522 3523 void hif_pci_reg_write32(struct hif_softc *hif_sc, 3524 uint32_t offset, 3525 uint32_t value) 3526 { 3527 hal_write32_mb(hif_sc->hal_soc, offset, value); 3528 } 3529 #else 3530 /* TODO: Need to implement other chips carefully */ 3531 uint32_t hif_pci_reg_read32(struct hif_softc *hif_sc, 3532 uint32_t offset) 3533 { 3534 return 0; 3535 } 3536 3537 void hif_pci_reg_write32(struct hif_softc *hif_sc, 3538 uint32_t offset, 3539 uint32_t value) 3540 { 3541 } 3542 #endif 3543 3544 /** 3545 * hif_configure_irq() - configure interrupt 3546 * @scn: HIF context 3547 * 3548 * This function configures interrupt(s) 3549 * 3550 * Return: 0 - for success 3551 */ 3552 int hif_configure_irq(struct hif_softc *scn) 3553 { 3554 int ret = 0; 3555 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 3556 3557 hif_info("E"); 3558 3559 if (hif_is_polled_mode_enabled(GET_HIF_OPAQUE_HDL(scn))) { 3560 scn->request_irq_done = false; 3561 return 0; 3562 } 3563 3564 hif_init_reschedule_tasklet_work(sc); 3565 3566 ret = hif_ce_msi_configure_irq(scn); 3567 if (ret == 0) { 3568 goto end; 3569 } 3570 3571 switch (scn->target_info.target_type) { 3572 case TARGET_TYPE_QCA8074: 3573 case TARGET_TYPE_QCA8074V2: 3574 case TARGET_TYPE_QCA6018: 3575 case TARGET_TYPE_QCA5018: 3576 case TARGET_TYPE_QCA5332: 3577 case TARGET_TYPE_QCA9574: 3578 case TARGET_TYPE_QCN9160: 3579 ret = hif_ahb_configure_irq(sc); 3580 break; 3581 case TARGET_TYPE_QCN9224: 3582 ret = hif_ce_configure_legacyirq(scn); 3583 break; 3584 default: 3585 ret = hif_pci_configure_legacy_irq(sc); 3586 break; 3587 } 3588 if (ret < 0) { 3589 hif_err("error = %d", ret); 3590 return ret; 3591 } 3592 end: 3593 scn->request_irq_done = true; 3594 return 0; 3595 } 3596 3597 /** 3598 * hif_trigger_timer_irq() : Triggers interrupt on LF_Timer 0 3599 * @scn: hif control structure 3600 * 3601 * Sets IRQ bit in LF Timer Status Address to awake peregrine/swift 3602 * stuck at a polling loop in pcie_address_config in FW 3603 * 3604 * Return: none 3605 */ 3606 static void hif_trigger_timer_irq(struct hif_softc *scn) 3607 { 3608 int tmp; 3609 /* Trigger IRQ on Peregrine/Swift by setting 3610 * IRQ Bit of LF_TIMER 0 3611 */ 3612 tmp = hif_read32_mb(scn, scn->mem + (RTC_SOC_BASE_ADDRESS + 3613 SOC_LF_TIMER_STATUS0_ADDRESS)); 3614 /* Set Raw IRQ Bit */ 3615 tmp |= 1; 3616 /* SOC_LF_TIMER_STATUS0 */ 3617 hif_write32_mb(scn, scn->mem + (RTC_SOC_BASE_ADDRESS + 3618 SOC_LF_TIMER_STATUS0_ADDRESS), tmp); 3619 } 3620 3621 /** 3622 * hif_target_sync() : ensure the target is ready 3623 * @scn: hif control structure 3624 * 3625 * Informs fw that we plan to use legacy interrupts so that 3626 * it can begin booting. Ensures that the fw finishes booting 3627 * before continuing. Should be called before trying to write 3628 * to the targets other registers for the first time. 3629 * 3630 * Return: none 3631 */ 3632 static void hif_target_sync(struct hif_softc *scn) 3633 { 3634 hif_write32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS | 3635 PCIE_INTR_ENABLE_ADDRESS), 3636 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 3637 /* read to flush pcie write */ 3638 (void)hif_read32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS | 3639 PCIE_INTR_ENABLE_ADDRESS)); 3640 3641 hif_write32_mb(scn, scn->mem + PCIE_LOCAL_BASE_ADDRESS + 3642 PCIE_SOC_WAKE_ADDRESS, 3643 PCIE_SOC_WAKE_V_MASK); 3644 while (!hif_targ_is_awake(scn, scn->mem)) 3645 ; 3646 3647 if (HAS_FW_INDICATOR) { 3648 int wait_limit = 500; 3649 int fw_ind = 0; 3650 int retry_count = 0; 3651 uint32_t target_type = scn->target_info.target_type; 3652 fw_retry: 3653 hif_info("Loop checking FW signal"); 3654 while (1) { 3655 fw_ind = hif_read32_mb(scn, scn->mem + 3656 FW_INDICATOR_ADDRESS); 3657 if (fw_ind & FW_IND_INITIALIZED) 3658 break; 3659 if (wait_limit-- < 0) 3660 break; 3661 hif_write32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS | 3662 PCIE_INTR_ENABLE_ADDRESS), 3663 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 3664 /* read to flush pcie write */ 3665 (void)hif_read32_mb(scn, scn->mem + 3666 (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS)); 3667 3668 qdf_mdelay(10); 3669 } 3670 if (wait_limit < 0) { 3671 if (target_type == TARGET_TYPE_AR9888 && 3672 retry_count++ < 2) { 3673 hif_trigger_timer_irq(scn); 3674 wait_limit = 500; 3675 goto fw_retry; 3676 } 3677 hif_info("FW signal timed out"); 3678 qdf_assert_always(0); 3679 } else { 3680 hif_info("Got FW signal, retries = %x", 500-wait_limit); 3681 } 3682 } 3683 hif_write32_mb(scn, scn->mem + PCIE_LOCAL_BASE_ADDRESS + 3684 PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET); 3685 } 3686 3687 static void hif_pci_get_soc_info_pld(struct hif_pci_softc *sc, 3688 struct device *dev) 3689 { 3690 struct pld_soc_info info; 3691 struct hif_softc *scn = HIF_GET_SOFTC(sc); 3692 3693 pld_get_soc_info(dev, &info); 3694 sc->mem = info.v_addr; 3695 sc->ce_sc.ol_sc.mem = info.v_addr; 3696 sc->ce_sc.ol_sc.mem_pa = info.p_addr; 3697 sc->device_version.family_number = info.device_version.family_number; 3698 sc->device_version.device_number = info.device_version.device_number; 3699 sc->device_version.major_version = info.device_version.major_version; 3700 sc->device_version.minor_version = info.device_version.minor_version; 3701 3702 hif_info("%s: fam num %u dev ver %u maj ver %u min ver %u", __func__, 3703 sc->device_version.family_number, 3704 sc->device_version.device_number, 3705 sc->device_version.major_version, 3706 sc->device_version.minor_version); 3707 3708 /* dev_mem_info[0] is for CMEM */ 3709 scn->cmem_start = info.dev_mem_info[0].start; 3710 scn->cmem_size = info.dev_mem_info[0].size; 3711 scn->target_info.target_version = info.soc_id; 3712 scn->target_info.target_revision = 0; 3713 scn->target_info.soc_version = info.device_version.major_version; 3714 } 3715 3716 static void hif_pci_get_soc_info_nopld(struct hif_pci_softc *sc, 3717 struct device *dev) 3718 {} 3719 3720 static bool hif_is_pld_based_target(struct hif_pci_softc *sc, 3721 int device_id) 3722 { 3723 if (!pld_have_platform_driver_support(sc->dev)) 3724 return false; 3725 3726 switch (device_id) { 3727 case QCA6290_DEVICE_ID: 3728 case QCN9000_DEVICE_ID: 3729 case QCN9224_DEVICE_ID: 3730 case QCA6290_EMULATION_DEVICE_ID: 3731 case QCA6390_DEVICE_ID: 3732 case QCA6490_DEVICE_ID: 3733 case AR6320_DEVICE_ID: 3734 case QCN7605_DEVICE_ID: 3735 case KIWI_DEVICE_ID: 3736 case MANGO_DEVICE_ID: 3737 case PEACH_DEVICE_ID: 3738 return true; 3739 } 3740 return false; 3741 } 3742 3743 static void hif_pci_init_deinit_ops_attach(struct hif_pci_softc *sc, 3744 int device_id) 3745 { 3746 if (hif_is_pld_based_target(sc, device_id)) { 3747 sc->hif_enable_pci = hif_enable_pci_pld; 3748 sc->hif_pci_deinit = hif_pci_deinit_pld; 3749 sc->hif_pci_get_soc_info = hif_pci_get_soc_info_pld; 3750 } else { 3751 sc->hif_enable_pci = hif_enable_pci_nopld; 3752 sc->hif_pci_deinit = hif_pci_deinit_nopld; 3753 sc->hif_pci_get_soc_info = hif_pci_get_soc_info_nopld; 3754 } 3755 } 3756 3757 #ifdef HIF_REG_WINDOW_SUPPORT 3758 static void hif_pci_init_reg_windowing_support(struct hif_pci_softc *sc, 3759 u32 target_type) 3760 { 3761 switch (target_type) { 3762 case TARGET_TYPE_QCN7605: 3763 case TARGET_TYPE_QCA6490: 3764 case TARGET_TYPE_QCA6390: 3765 case TARGET_TYPE_KIWI: 3766 case TARGET_TYPE_MANGO: 3767 case TARGET_TYPE_PEACH: 3768 sc->use_register_windowing = true; 3769 qdf_spinlock_create(&sc->register_access_lock); 3770 sc->register_window = 0; 3771 break; 3772 default: 3773 sc->use_register_windowing = false; 3774 } 3775 } 3776 #else 3777 static void hif_pci_init_reg_windowing_support(struct hif_pci_softc *sc, 3778 u32 target_type) 3779 { 3780 sc->use_register_windowing = false; 3781 } 3782 #endif 3783 3784 /** 3785 * hif_pci_enable_bus(): enable bus 3786 * @ol_sc: soft_sc struct 3787 * @dev: device pointer 3788 * @bdev: bus dev pointer 3789 * @bid: bus id pointer 3790 * @type: enum hif_enable_type such as HIF_ENABLE_TYPE_PROBE 3791 * 3792 * This function enables the bus 3793 * 3794 * Return: QDF_STATUS 3795 */ 3796 QDF_STATUS hif_pci_enable_bus(struct hif_softc *ol_sc, 3797 struct device *dev, void *bdev, 3798 const struct hif_bus_id *bid, 3799 enum hif_enable_type type) 3800 { 3801 int ret = 0; 3802 uint32_t hif_type; 3803 uint32_t target_type = TARGET_TYPE_UNKNOWN; 3804 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(ol_sc); 3805 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(ol_sc); 3806 uint16_t revision_id = 0; 3807 int probe_again = 0; 3808 struct pci_dev *pdev = bdev; 3809 const struct pci_device_id *id = (const struct pci_device_id *)bid; 3810 struct hif_target_info *tgt_info; 3811 3812 if (!ol_sc) { 3813 hif_err("hif_ctx is NULL"); 3814 return QDF_STATUS_E_NOMEM; 3815 } 3816 /* Following print is used by various tools to identify 3817 * WLAN SOC (e.g. crash dump analysis and reporting tool). 3818 */ 3819 hif_info("con_mode = 0x%x, WLAN_SOC_device_id = 0x%x", 3820 hif_get_conparam(ol_sc), id->device); 3821 3822 sc->pdev = pdev; 3823 sc->dev = &pdev->dev; 3824 sc->devid = id->device; 3825 sc->cacheline_sz = dma_get_cache_alignment(); 3826 tgt_info = hif_get_target_info_handle(hif_hdl); 3827 hif_pci_init_deinit_ops_attach(sc, id->device); 3828 sc->hif_pci_get_soc_info(sc, dev); 3829 again: 3830 ret = sc->hif_enable_pci(sc, pdev, id); 3831 if (ret < 0) { 3832 hif_err("hif_enable_pci error = %d", ret); 3833 goto err_enable_pci; 3834 } 3835 hif_info("hif_enable_pci done"); 3836 3837 /* Temporary FIX: disable ASPM on peregrine. 3838 * Will be removed after the OTP is programmed 3839 */ 3840 hif_disable_power_gating(hif_hdl); 3841 3842 device_disable_async_suspend(&pdev->dev); 3843 pfrm_read_config_word(pdev, 0x08, &revision_id); 3844 3845 ret = hif_get_device_type(id->device, revision_id, 3846 &hif_type, &target_type); 3847 if (ret < 0) { 3848 hif_err("Invalid device id/revision_id"); 3849 goto err_tgtstate; 3850 } 3851 hif_info("hif_type = 0x%x, target_type = 0x%x", 3852 hif_type, target_type); 3853 3854 hif_register_tbl_attach(ol_sc, hif_type); 3855 hif_target_register_tbl_attach(ol_sc, target_type); 3856 3857 hif_pci_init_reg_windowing_support(sc, target_type); 3858 3859 tgt_info->target_type = target_type; 3860 3861 /* 3862 * Disable unlzay interrupt registration for QCN9000 3863 */ 3864 if (target_type == TARGET_TYPE_QCN9000 || 3865 target_type == TARGET_TYPE_QCN9224) 3866 ol_sc->irq_unlazy_disable = 1; 3867 3868 if (ce_srng_based(ol_sc)) { 3869 hif_info("Skip tgt_wake up for srng devices"); 3870 } else { 3871 ret = hif_pci_probe_tgt_wakeup(sc); 3872 if (ret < 0) { 3873 hif_err("hif_pci_prob_wakeup error = %d", ret); 3874 if (ret == -EAGAIN) 3875 probe_again++; 3876 goto err_tgtstate; 3877 } 3878 hif_info("hif_pci_probe_tgt_wakeup done"); 3879 } 3880 3881 if (!ol_sc->mem_pa) { 3882 hif_err("BAR0 uninitialized"); 3883 ret = -EIO; 3884 goto err_tgtstate; 3885 } 3886 3887 if (!ce_srng_based(ol_sc)) { 3888 hif_target_sync(ol_sc); 3889 3890 if (hif_pci_default_link_up(tgt_info)) 3891 hif_vote_link_up(hif_hdl); 3892 } 3893 3894 return QDF_STATUS_SUCCESS; 3895 3896 err_tgtstate: 3897 hif_disable_pci(sc); 3898 sc->pci_enabled = false; 3899 hif_err("hif_disable_pci done"); 3900 return QDF_STATUS_E_ABORTED; 3901 3902 err_enable_pci: 3903 if (probe_again && (probe_again <= ATH_PCI_PROBE_RETRY_MAX)) { 3904 int delay_time; 3905 3906 hif_info("pci reprobe"); 3907 /* 10, 40, 90, 100, 100, ... */ 3908 delay_time = max(100, 10 * (probe_again * probe_again)); 3909 qdf_mdelay(delay_time); 3910 goto again; 3911 } 3912 return qdf_status_from_os_return(ret); 3913 } 3914 3915 /** 3916 * hif_pci_irq_enable() - ce_irq_enable 3917 * @scn: hif_softc 3918 * @ce_id: ce_id 3919 * 3920 * Return: void 3921 */ 3922 void hif_pci_irq_enable(struct hif_softc *scn, int ce_id) 3923 { 3924 uint32_t tmp = 1 << ce_id; 3925 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 3926 3927 qdf_spin_lock_irqsave(&sc->irq_lock); 3928 scn->ce_irq_summary &= ~tmp; 3929 if (scn->ce_irq_summary == 0) { 3930 /* Enable Legacy PCI line interrupts */ 3931 if (LEGACY_INTERRUPTS(sc) && 3932 (scn->target_status != TARGET_STATUS_RESET) && 3933 (!qdf_atomic_read(&scn->link_suspended))) { 3934 3935 hif_write32_mb(scn, scn->mem + 3936 (SOC_CORE_BASE_ADDRESS | 3937 PCIE_INTR_ENABLE_ADDRESS), 3938 HOST_GROUP0_MASK); 3939 3940 hif_read32_mb(scn, scn->mem + 3941 (SOC_CORE_BASE_ADDRESS | 3942 PCIE_INTR_ENABLE_ADDRESS)); 3943 } 3944 } 3945 if (scn->hif_init_done == true) 3946 Q_TARGET_ACCESS_END(scn); 3947 qdf_spin_unlock_irqrestore(&sc->irq_lock); 3948 3949 /* check for missed firmware crash */ 3950 hif_fw_interrupt_handler(0, scn); 3951 } 3952 3953 /** 3954 * hif_pci_irq_disable() - ce_irq_disable 3955 * @scn: hif_softc 3956 * @ce_id: ce_id 3957 * 3958 * only applicable to legacy copy engine... 3959 * 3960 * Return: void 3961 */ 3962 void hif_pci_irq_disable(struct hif_softc *scn, int ce_id) 3963 { 3964 /* For Rome only need to wake up target */ 3965 /* target access is maintained until interrupts are re-enabled */ 3966 Q_TARGET_ACCESS_BEGIN(scn); 3967 } 3968 3969 int hif_pci_legacy_map_ce_to_irq(struct hif_softc *scn, int ce_id) 3970 { 3971 struct hif_pci_softc *pci_scn = HIF_GET_PCI_SOFTC(scn); 3972 3973 /* legacy case only has one irq */ 3974 return pci_scn->irq; 3975 } 3976 3977 int hif_pci_addr_in_boundary(struct hif_softc *scn, uint32_t offset) 3978 { 3979 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 3980 struct hif_target_info *tgt_info; 3981 3982 tgt_info = hif_get_target_info_handle(GET_HIF_OPAQUE_HDL(scn)); 3983 3984 if (tgt_info->target_type == TARGET_TYPE_QCA6290 || 3985 tgt_info->target_type == TARGET_TYPE_QCA6390 || 3986 tgt_info->target_type == TARGET_TYPE_QCA6490 || 3987 tgt_info->target_type == TARGET_TYPE_QCN7605 || 3988 tgt_info->target_type == TARGET_TYPE_QCA8074 || 3989 tgt_info->target_type == TARGET_TYPE_KIWI || 3990 tgt_info->target_type == TARGET_TYPE_MANGO || 3991 tgt_info->target_type == TARGET_TYPE_PEACH) { 3992 /* 3993 * Need to consider offset's memtype for QCA6290/QCA8074, 3994 * also mem_len and DRAM_BASE_ADDRESS/DRAM_SIZE need to be 3995 * well initialized/defined. 3996 */ 3997 return 0; 3998 } 3999 4000 if ((offset >= DRAM_BASE_ADDRESS && offset <= DRAM_BASE_ADDRESS + DRAM_SIZE) 4001 || (offset + sizeof(unsigned int) <= sc->mem_len)) { 4002 return 0; 4003 } 4004 4005 hif_info("Refusing to read memory at 0x%x - 0x%x (max 0x%zx)", 4006 offset, (uint32_t)(offset + sizeof(unsigned int)), 4007 sc->mem_len); 4008 4009 return -EINVAL; 4010 } 4011 4012 /** 4013 * hif_pci_needs_bmi() - return true if the soc needs bmi through the driver 4014 * @scn: hif context 4015 * 4016 * Return: true if soc needs driver bmi otherwise false 4017 */ 4018 bool hif_pci_needs_bmi(struct hif_softc *scn) 4019 { 4020 return !ce_srng_based(scn); 4021 } 4022 4023 #ifdef FORCE_WAKE 4024 #if defined(DEVICE_FORCE_WAKE_ENABLE) && !defined(CONFIG_PLD_PCIE_FW_SIM) 4025 4026 /* 4027 * HIF_POLL_UMAC_WAKE poll value to indicate if UMAC is powered up 4028 * Update the below macro with FW defined one. 4029 */ 4030 #define HIF_POLL_UMAC_WAKE 0x2 4031 4032 static inline int hif_soc_wake_request(struct hif_opaque_softc *hif_handle) 4033 { 4034 uint32_t timeout, value; 4035 struct hif_softc *scn = (struct hif_softc *)hif_handle; 4036 struct hif_pci_softc *pci_scn = HIF_GET_PCI_SOFTC(scn); 4037 4038 qdf_spin_lock_bh(&pci_scn->force_wake_lock); 4039 if ((qdf_atomic_inc_return(&scn->active_wake_req_cnt) > 1)) { 4040 qdf_spin_unlock_bh(&pci_scn->force_wake_lock); 4041 return 0; 4042 } 4043 4044 hif_write32_mb(scn, scn->mem + PCIE_REG_WAKE_UMAC_OFFSET, 1); 4045 HIF_STATS_INC(pci_scn, soc_force_wake_register_write_success, 1); 4046 /* 4047 * do not reset the timeout 4048 * total_wake_time = MHI_WAKE_TIME + PCI_WAKE_TIME < 50 ms 4049 */ 4050 timeout = 0; 4051 do { 4052 value = hif_read32_mb( 4053 scn, scn->mem + 4054 PCIE_SOC_PCIE_REG_PCIE_SCRATCH_0_SOC_PCIE_REG); 4055 if (value == HIF_POLL_UMAC_WAKE) 4056 break; 4057 qdf_mdelay(FORCE_WAKE_DELAY_MS); 4058 timeout += FORCE_WAKE_DELAY_MS; 4059 } while (timeout <= FORCE_WAKE_DELAY_TIMEOUT_MS); 4060 4061 if (value != HIF_POLL_UMAC_WAKE) { 4062 hif_err("force wake handshake failed, reg value = 0x%x", 4063 value); 4064 HIF_STATS_INC(pci_scn, soc_force_wake_failure, 1); 4065 qdf_atomic_dec(&scn->active_wake_req_cnt); 4066 qdf_spin_unlock_bh(&pci_scn->force_wake_lock); 4067 return -ETIMEDOUT; 4068 } 4069 4070 HIF_STATS_INC(pci_scn, soc_force_wake_success, 1); 4071 qdf_spin_unlock_bh(&pci_scn->force_wake_lock); 4072 return 0; 4073 } 4074 4075 static inline void hif_soc_wake_release(struct hif_opaque_softc *hif_handle) 4076 { 4077 struct hif_softc *scn = (struct hif_softc *)hif_handle; 4078 struct hif_pci_softc *pci_scn = HIF_GET_PCI_SOFTC(scn); 4079 4080 qdf_spin_lock_bh(&pci_scn->force_wake_lock); 4081 if (!qdf_atomic_dec_and_test(&scn->active_wake_req_cnt)) { 4082 qdf_spin_unlock_bh(&pci_scn->force_wake_lock); 4083 return; 4084 } 4085 4086 /* Release umac force wake */ 4087 hif_write32_mb(scn, scn->mem + PCIE_REG_WAKE_UMAC_OFFSET, 0); 4088 qdf_spin_unlock_bh(&pci_scn->force_wake_lock); 4089 } 4090 4091 /** 4092 * hif_force_wake_request(): Enable the force wake recipe 4093 * @hif_handle: HIF handle 4094 * 4095 * Bring MHI to M0 state and force wake the UMAC by asserting the 4096 * soc wake reg. Poll the scratch reg to check if its set to 4097 * HIF_POLL_UMAC_WAKE. The polled value may return 0x1 in case UMAC 4098 * is powered down. 4099 * 4100 * Return: 0 if handshake is successful or ETIMEDOUT in case of failure 4101 */ 4102 int hif_force_wake_request(struct hif_opaque_softc *hif_handle) 4103 { 4104 uint32_t timeout; 4105 struct hif_softc *scn = (struct hif_softc *)hif_handle; 4106 struct hif_pci_softc *pci_scn = HIF_GET_PCI_SOFTC(scn); 4107 int ret, status = 0; 4108 4109 /* Prevent runtime PM or trigger resume firstly */ 4110 if (hif_rtpm_get(HIF_RTPM_GET_SYNC, HIF_RTPM_ID_FORCE_WAKE)) { 4111 hif_err("runtime pm get failed"); 4112 return -EINVAL; 4113 } 4114 4115 HIF_STATS_INC(pci_scn, mhi_force_wake_request_vote, 1); 4116 if (qdf_in_interrupt()) 4117 timeout = FORCE_WAKE_DELAY_TIMEOUT_MS * 1000; 4118 else 4119 timeout = 0; 4120 4121 ret = pld_force_wake_request_sync(scn->qdf_dev->dev, timeout); 4122 if (ret) { 4123 hif_err("force wake request(timeout %u) send failed: %d", 4124 timeout, ret); 4125 HIF_STATS_INC(pci_scn, mhi_force_wake_failure, 1); 4126 status = -EINVAL; 4127 goto release_rtpm_ref; 4128 } 4129 4130 /* If device's M1 state-change event races here, it can be ignored, 4131 * as the device is expected to immediately move from M2 to M0 4132 * without entering low power state. 4133 */ 4134 if (!pld_is_device_awake(scn->qdf_dev->dev)) 4135 hif_info("state-change event races, ignore"); 4136 4137 HIF_STATS_INC(pci_scn, mhi_force_wake_success, 1); 4138 4139 ret = hif_soc_wake_request(hif_handle); 4140 if (ret) { 4141 hif_err("soc force wake failed: %d", ret); 4142 status = ret; 4143 goto release_mhi_wake; 4144 } 4145 return 0; 4146 4147 release_mhi_wake: 4148 /* Release MHI force wake */ 4149 ret = pld_force_wake_release(scn->qdf_dev->dev); 4150 if (ret) { 4151 hif_err("pld force wake release failure"); 4152 HIF_STATS_INC(pci_scn, mhi_force_wake_release_failure, 1); 4153 status = ret; 4154 } else { 4155 HIF_STATS_INC(pci_scn, mhi_force_wake_release_success, 1); 4156 } 4157 4158 release_rtpm_ref: 4159 /* Release runtime PM force wake */ 4160 ret = hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_FORCE_WAKE); 4161 if (ret) { 4162 hif_err("runtime pm put failure: %d", ret); 4163 return ret; 4164 } 4165 4166 return status; 4167 } 4168 4169 int hif_force_wake_release(struct hif_opaque_softc *hif_handle) 4170 { 4171 int ret, status; 4172 struct hif_softc *scn = (struct hif_softc *)hif_handle; 4173 struct hif_pci_softc *pci_scn = HIF_GET_PCI_SOFTC(scn); 4174 4175 hif_soc_wake_release(hif_handle); 4176 4177 /* Release MHI force wake */ 4178 ret = pld_force_wake_release(scn->qdf_dev->dev); 4179 if (ret) { 4180 hif_err("pld force wake release failure"); 4181 HIF_STATS_INC(pci_scn, mhi_force_wake_release_failure, 1); 4182 goto release_rtpm_ref; 4183 } 4184 HIF_STATS_INC(pci_scn, mhi_force_wake_release_success, 1); 4185 HIF_STATS_INC(pci_scn, soc_force_wake_release_success, 1); 4186 4187 release_rtpm_ref: 4188 /* Release runtime PM force wake */ 4189 status = hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_FORCE_WAKE); 4190 if (status) { 4191 hif_err("runtime pm put failure: %d", status); 4192 return status; 4193 } 4194 return ret; 4195 } 4196 4197 #else /* DEVICE_FORCE_WAKE_ENABLE */ 4198 /** hif_force_wake_request() - Disable the PCIE scratch register 4199 * write/read 4200 * 4201 * Return: 0 4202 */ 4203 int hif_force_wake_request(struct hif_opaque_softc *hif_handle) 4204 { 4205 struct hif_softc *scn = (struct hif_softc *)hif_handle; 4206 struct hif_pci_softc *pci_scn = HIF_GET_PCI_SOFTC(scn); 4207 uint32_t timeout; 4208 int ret; 4209 4210 HIF_STATS_INC(pci_scn, mhi_force_wake_request_vote, 1); 4211 4212 if (qdf_in_interrupt()) 4213 timeout = FORCE_WAKE_DELAY_TIMEOUT_MS * 1000; 4214 else 4215 timeout = 0; 4216 4217 ret = pld_force_wake_request_sync(scn->qdf_dev->dev, timeout); 4218 if (ret) { 4219 hif_err("force wake request(timeout %u) send failed: %d", 4220 timeout, ret); 4221 HIF_STATS_INC(pci_scn, mhi_force_wake_failure, 1); 4222 return -EINVAL; 4223 } 4224 4225 /* If device's M1 state-change event races here, it can be ignored, 4226 * as the device is expected to immediately move from M2 to M0 4227 * without entering low power state. 4228 */ 4229 if (!pld_is_device_awake(scn->qdf_dev->dev)) 4230 hif_info("state-change event races, ignore"); 4231 4232 HIF_STATS_INC(pci_scn, mhi_force_wake_success, 1); 4233 4234 return 0; 4235 } 4236 4237 int hif_force_wake_release(struct hif_opaque_softc *hif_handle) 4238 { 4239 int ret; 4240 struct hif_softc *scn = (struct hif_softc *)hif_handle; 4241 struct hif_pci_softc *pci_scn = HIF_GET_PCI_SOFTC(scn); 4242 4243 ret = pld_force_wake_release(scn->qdf_dev->dev); 4244 if (ret) { 4245 hif_err("force wake release failure"); 4246 HIF_STATS_INC(pci_scn, mhi_force_wake_release_failure, 1); 4247 return ret; 4248 } 4249 4250 HIF_STATS_INC(pci_scn, mhi_force_wake_release_success, 1); 4251 return 0; 4252 } 4253 #endif /* DEVICE_FORCE_WAKE_ENABLE */ 4254 4255 void hif_print_pci_stats(struct hif_pci_softc *pci_handle) 4256 { 4257 hif_debug("mhi_force_wake_request_vote: %d", 4258 pci_handle->stats.mhi_force_wake_request_vote); 4259 hif_debug("mhi_force_wake_failure: %d", 4260 pci_handle->stats.mhi_force_wake_failure); 4261 hif_debug("mhi_force_wake_success: %d", 4262 pci_handle->stats.mhi_force_wake_success); 4263 hif_debug("soc_force_wake_register_write_success: %d", 4264 pci_handle->stats.soc_force_wake_register_write_success); 4265 hif_debug("soc_force_wake_failure: %d", 4266 pci_handle->stats.soc_force_wake_failure); 4267 hif_debug("soc_force_wake_success: %d", 4268 pci_handle->stats.soc_force_wake_success); 4269 hif_debug("mhi_force_wake_release_failure: %d", 4270 pci_handle->stats.mhi_force_wake_release_failure); 4271 hif_debug("mhi_force_wake_release_success: %d", 4272 pci_handle->stats.mhi_force_wake_release_success); 4273 hif_debug("oc_force_wake_release_success: %d", 4274 pci_handle->stats.soc_force_wake_release_success); 4275 } 4276 #endif /* FORCE_WAKE */ 4277 4278 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 4279 int hif_prevent_link_low_power_states(struct hif_opaque_softc *hif) 4280 { 4281 return pld_prevent_l1(HIF_GET_SOFTC(hif)->qdf_dev->dev); 4282 } 4283 4284 void hif_allow_link_low_power_states(struct hif_opaque_softc *hif) 4285 { 4286 pld_allow_l1(HIF_GET_SOFTC(hif)->qdf_dev->dev); 4287 } 4288 #endif 4289 4290 #ifdef IPA_OPT_WIFI_DP 4291 int hif_prevent_l1(struct hif_opaque_softc *hif) 4292 { 4293 struct hif_softc *hif_softc = (struct hif_softc *)hif; 4294 int status; 4295 4296 status = hif_force_wake_request(hif); 4297 if (status) { 4298 hif_err("Force wake request error"); 4299 return status; 4300 } 4301 4302 qdf_atomic_inc(&hif_softc->opt_wifi_dp_rtpm_cnt); 4303 hif_info("opt_dp: pcie link up count %d", 4304 qdf_atomic_read(&hif_softc->opt_wifi_dp_rtpm_cnt)); 4305 return status; 4306 } 4307 4308 void hif_allow_l1(struct hif_opaque_softc *hif) 4309 { 4310 struct hif_softc *hif_softc = (struct hif_softc *)hif; 4311 int status; 4312 4313 if (qdf_atomic_read(&hif_softc->opt_wifi_dp_rtpm_cnt) > 0) { 4314 status = hif_force_wake_release(hif); 4315 if (status) { 4316 hif_err("Force wake release error"); 4317 return; 4318 } 4319 4320 qdf_atomic_dec(&hif_softc->opt_wifi_dp_rtpm_cnt); 4321 hif_info("opt_dp: pcie link down count %d", 4322 qdf_atomic_read(&hif_softc->opt_wifi_dp_rtpm_cnt)); 4323 } 4324 } 4325 #endif 4326