1 /* 2 * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef __HIF_IO32_PCI_H__ 20 #define __HIF_IO32_PCI_H__ 21 22 #ifdef HIF_PCI 23 24 #include "hif_main.h" 25 #include "regtable.h" 26 #include "ce_reg.h" 27 #include "qdf_atomic.h" 28 #include "if_pci.h" 29 /* 30 * For maximum performance and no power management, set this to 1. 31 * For power management at the cost of performance, set this to 0. 32 */ 33 #ifndef CONFIG_ATH_PCIE_MAX_PERF 34 #define CONFIG_ATH_PCIE_MAX_PERF 0 35 #endif 36 37 /* 38 * For keeping the target awake till the driver is 39 * loaded, set this to 1 40 */ 41 #ifndef CONFIG_ATH_PCIE_AWAKE_WHILE_DRIVER_LOAD 42 #define CONFIG_ATH_PCIE_AWAKE_WHILE_DRIVER_LOAD 1 43 #endif 44 45 /* 46 * PCI-E L1 ASPPM sub-states 47 * To enable clock gating in L1 state, set this to 1. 48 * (less power, slightly more wakeup latency) 49 * To disable clock gating in L1 state, set this to 0. (slighly more power) 50 */ 51 #define CONFIG_PCIE_ENABLE_L1_CLOCK_GATE 1 52 53 /* 54 * PCIE_ACCESS_LOG_NUM specifies the number of 55 * read/write records to store 56 */ 57 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 58 #define PCIE_ACCESS_LOG_NUM 500 59 #endif 60 61 /* 64-bit MSI support */ 62 #define CONFIG_PCIE_64BIT_MSI 0 63 64 /* BAR0 ready checking for AR6320v2 */ 65 #define PCIE_BAR0_READY_CHECKING 0 66 67 /* AXI gating when L1, L2 to reduce power consumption */ 68 #define CONFIG_PCIE_ENABLE_AXI_CLK_GATE 0 69 70 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg); 71 #endif /* HIF_PCI */ 72 #endif /* __HIF_IO32_PCI_H__ */ 73