1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __ATH_IPCI_H__ 18 #define __ATH_IPCI_H__ 19 20 #include <linux/version.h> 21 #include <linux/semaphore.h> 22 #include <linux/interrupt.h> 23 24 #define ATH_DBG_DEFAULT 0 25 #define DRAM_SIZE 0x000a8000 26 #include "hif.h" 27 #include "cepci.h" 28 #include "ce_main.h" 29 30 #ifdef FORCE_WAKE 31 /** 32 * struct hif_pci_stats - Account for hif pci based statistics 33 * @mhi_force_wake_request_vote: vote for mhi 34 * @mhi_force_wake_failure: mhi force wake failure 35 * @mhi_force_wake_success: mhi force wake success 36 * @soc_force_wake_register_write_success: write to soc wake 37 * @soc_force_wake_failure: soc force wake failure 38 * @soc_force_wake_success: soc force wake success 39 * @mhi_force_wake_release_success: mhi force wake release success 40 * @soc_force_wake_release_success: soc force wake release 41 */ 42 struct hif_ipci_stats { 43 uint32_t mhi_force_wake_request_vote; 44 uint32_t mhi_force_wake_failure; 45 uint32_t mhi_force_wake_success; 46 uint32_t soc_force_wake_register_write_success; 47 uint32_t soc_force_wake_failure; 48 uint32_t soc_force_wake_success; 49 uint32_t mhi_force_wake_release_failure; 50 uint32_t mhi_force_wake_release_success; 51 uint32_t soc_force_wake_release_success; 52 }; 53 54 /* Register to wake the UMAC from power collapse */ 55 #define PCIE_SOC_PCIE_REG_PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040 56 /* Register used for handshake mechanism to validate UMAC is awake */ 57 #define PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004 58 /* Timeout duration to validate UMAC wake status */ 59 #ifdef HAL_CONFIG_SLUB_DEBUG_ON 60 #define FORCE_WAKE_DELAY_TIMEOUT_MS 500 61 #else 62 #define FORCE_WAKE_DELAY_TIMEOUT_MS 50 63 #endif /* HAL_CONFIG_SLUB_DEBUG_ON */ 64 /* Validate UMAC status every 5ms */ 65 #define FORCE_WAKE_DELAY_MS 5 66 #endif /* FORCE_WAKE */ 67 68 struct hif_ipci_softc { 69 struct HIF_CE_state ce_sc; 70 void __iomem *mem; /* PCI address. */ 71 72 struct device *dev; /* For efficiency, should be first in struct */ 73 struct tasklet_struct intr_tq; /* tasklet */ 74 int ce_msi_irq_num[CE_COUNT_MAX]; 75 bool use_register_windowing; 76 uint32_t register_window; 77 qdf_spinlock_t register_access_lock; 78 qdf_spinlock_t irq_lock; 79 80 void (*hif_ipci_get_soc_info)(struct hif_ipci_softc *sc, 81 struct device *dev); 82 #ifdef FORCE_WAKE 83 struct hif_ipci_stats stats; 84 #endif 85 }; 86 87 int hif_configure_irq(struct hif_softc *sc); 88 89 /* 90 * There may be some pending tx frames during platform suspend. 91 * Suspend operation should be delayed until those tx frames are 92 * transferred from the host to target. This macro specifies how 93 * long suspend thread has to sleep before checking pending tx 94 * frame count. 95 */ 96 #define OL_ATH_TX_DRAIN_WAIT_DELAY 50 /* ms */ 97 98 #ifdef FORCE_WAKE 99 /** 100 * hif_print_ipci_stats() - Display HIF IPCI stats 101 * @ipci_scn - HIF ipci handle 102 * 103 * Return: None 104 */ 105 void hif_print_ipci_stats(struct hif_ipci_softc *ipci_scn); 106 #else 107 static inline 108 void hif_print_ipci_stats(struct hif_ipci_softc *ipci_scn) 109 { 110 } 111 #endif /* FORCE_WAKE */ 112 113 #endif /* __IATH_PCI_H__ */ 114