1 /* 2 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __ATH_IPCI_H__ 18 #define __ATH_IPCI_H__ 19 20 #include <linux/version.h> 21 #include <linux/semaphore.h> 22 #include <linux/interrupt.h> 23 24 #define ATH_DBG_DEFAULT 0 25 #define DRAM_SIZE 0x000a8000 26 #include "hif.h" 27 #include "cepci.h" 28 #include "ce_main.h" 29 #include "hif_runtime_pm.h" 30 31 #ifdef FORCE_WAKE 32 /** 33 * struct hif_pci_stats - Account for hif pci based statistics 34 * @mhi_force_wake_request_vote: vote for mhi 35 * @mhi_force_wake_failure: mhi force wake failure 36 * @mhi_force_wake_success: mhi force wake success 37 * @soc_force_wake_register_write_success: write to soc wake 38 * @soc_force_wake_failure: soc force wake failure 39 * @soc_force_wake_success: soc force wake success 40 * @mhi_force_wake_release_success: mhi force wake release success 41 * @soc_force_wake_release_success: soc force wake release 42 */ 43 struct hif_ipci_stats { 44 uint32_t mhi_force_wake_request_vote; 45 uint32_t mhi_force_wake_failure; 46 uint32_t mhi_force_wake_success; 47 uint32_t soc_force_wake_register_write_success; 48 uint32_t soc_force_wake_failure; 49 uint32_t soc_force_wake_success; 50 uint32_t mhi_force_wake_release_failure; 51 uint32_t mhi_force_wake_release_success; 52 uint32_t soc_force_wake_release_success; 53 }; 54 55 /* Register offset to wake the UMAC from power collapse */ 56 #define PCIE_REG_WAKE_UMAC_OFFSET 0x3004 57 /* Register to wake the UMAC from power collapse */ 58 #define PCIE_SOC_PCIE_REG_PCIE_SCRATCH_0_SOC_PCIE_REG (0x01E04000 + 0x40) 59 60 /* Timeout duration to validate UMAC wake status */ 61 #ifdef HAL_CONFIG_SLUB_DEBUG_ON 62 #define FORCE_WAKE_DELAY_TIMEOUT_MS 500 63 #else 64 #define FORCE_WAKE_DELAY_TIMEOUT_MS 50 65 #endif /* HAL_CONFIG_SLUB_DEBUG_ON */ 66 /* Validate UMAC status every 5ms */ 67 #define FORCE_WAKE_DELAY_MS 5 68 #endif /* FORCE_WAKE */ 69 70 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 71 #ifdef HAL_CONFIG_SLUB_DEBUG_ON 72 #define EP_WAKE_RESET_DELAY_TIMEOUT_US 3000 73 #define EP_WAKE_DELAY_TIMEOUT_US 7000 74 #else 75 #define EP_WAKE_RESET_DELAY_TIMEOUT_US 10000 76 #define EP_WAKE_DELAY_TIMEOUT_US 10000 77 #endif 78 #define EP_WAKE_RESET_DELAY_US 50 79 #define EP_WAKE_DELAY_US 200 80 #endif 81 82 struct hif_ipci_softc { 83 struct HIF_CE_state ce_sc; 84 void __iomem *mem; /* PCI address. */ 85 86 struct device *dev; /* For efficiency, should be first in struct */ 87 struct tasklet_struct intr_tq; /* tasklet */ 88 int ce_msi_irq_num[CE_COUNT_MAX]; 89 bool use_register_windowing; 90 uint32_t register_window; 91 qdf_spinlock_t register_access_lock; 92 qdf_spinlock_t irq_lock; 93 bool grp_irqs_disabled; 94 #ifdef FEATURE_RUNTIME_PM 95 struct hif_runtime_pm_ctx rpm_ctx; 96 #endif 97 98 void (*hif_ipci_get_soc_info)(struct hif_ipci_softc *sc, 99 struct device *dev); 100 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 101 uint32_t ep_awake_reset_fail; 102 uint32_t prevent_l1_fail; 103 uint32_t ep_awake_set_fail; 104 bool prevent_l1; 105 #endif 106 #ifdef FORCE_WAKE 107 struct hif_ipci_stats stats; 108 #endif 109 #ifdef HIF_CPU_PERF_AFFINE_MASK 110 /* Stores the affinity hint mask for each CE IRQ */ 111 qdf_cpu_mask ce_irq_cpu_mask[CE_COUNT_MAX]; 112 #endif 113 }; 114 115 int hif_configure_irq(struct hif_softc *sc); 116 117 /* 118 * There may be some pending tx frames during platform suspend. 119 * Suspend operation should be delayed until those tx frames are 120 * transferred from the host to target. This macro specifies how 121 * long suspend thread has to sleep before checking pending tx 122 * frame count. 123 */ 124 #define OL_ATH_TX_DRAIN_WAIT_DELAY 50 /* ms */ 125 126 #ifdef FORCE_WAKE 127 /** 128 * hif_print_ipci_stats() - Display HIF IPCI stats 129 * @ipci_scn - HIF ipci handle 130 * 131 * Return: None 132 */ 133 void hif_print_ipci_stats(struct hif_ipci_softc *ipci_scn); 134 #else 135 static inline 136 void hif_print_ipci_stats(struct hif_ipci_softc *ipci_scn) 137 { 138 } 139 #endif /* FORCE_WAKE */ 140 141 #endif /* __IATH_PCI_H__ */ 142