1 /* 2 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef __ATH_IPCI_H__ 19 #define __ATH_IPCI_H__ 20 21 #include <linux/version.h> 22 #include <linux/semaphore.h> 23 #include <linux/interrupt.h> 24 25 #define ATH_DBG_DEFAULT 0 26 #define DRAM_SIZE 0x000a8000 27 #include "hif.h" 28 #include "cepci.h" 29 #include "ce_main.h" 30 #include "hif_runtime_pm.h" 31 32 #ifdef FORCE_WAKE 33 /** 34 * struct hif_pci_stats - Account for hif pci based statistics 35 * @mhi_force_wake_request_vote: vote for mhi 36 * @mhi_force_wake_failure: mhi force wake failure 37 * @mhi_force_wake_success: mhi force wake success 38 * @soc_force_wake_register_write_success: write to soc wake 39 * @soc_force_wake_failure: soc force wake failure 40 * @soc_force_wake_success: soc force wake success 41 * @mhi_force_wake_release_success: mhi force wake release success 42 * @soc_force_wake_release_success: soc force wake release 43 */ 44 struct hif_ipci_stats { 45 uint32_t mhi_force_wake_request_vote; 46 uint32_t mhi_force_wake_failure; 47 uint32_t mhi_force_wake_success; 48 uint32_t soc_force_wake_register_write_success; 49 uint32_t soc_force_wake_failure; 50 uint32_t soc_force_wake_success; 51 uint32_t mhi_force_wake_release_failure; 52 uint32_t mhi_force_wake_release_success; 53 uint32_t soc_force_wake_release_success; 54 }; 55 56 /* Register offset to wake the UMAC from power collapse */ 57 #define PCIE_REG_WAKE_UMAC_OFFSET 0x3004 58 /* Register to wake the UMAC from power collapse */ 59 #define PCIE_SOC_PCIE_REG_PCIE_SCRATCH_0_SOC_PCIE_REG (0x01E04000 + 0x40) 60 61 /* Timeout duration to validate UMAC wake status */ 62 #define FORCE_WAKE_DELAY_TIMEOUT_MS 500 63 64 /* Validate UMAC status every 5ms */ 65 #define FORCE_WAKE_DELAY_MS 5 66 #endif /* FORCE_WAKE */ 67 68 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 69 #define EP_VOTE_POLL_TIME_US 50 70 #define EP_VOTE_POLL_TIME_CNT 3 71 #ifdef HAL_CONFIG_SLUB_DEBUG_ON 72 #define EP_WAKE_RESET_DELAY_TIMEOUT_MS 3 73 #else 74 #define EP_WAKE_RESET_DELAY_TIMEOUT_MS 10 75 #endif 76 #define EP_WAKE_DELAY_TIMEOUT_MS 10 77 #define EP_WAKE_RESET_DELAY_US 50 78 #define EP_WAKE_DELAY_US 200 79 #endif 80 81 struct hif_ipci_softc { 82 struct HIF_CE_state ce_sc; 83 void __iomem *mem; /* PCI address. */ 84 85 struct device *dev; /* For efficiency, should be first in struct */ 86 struct tasklet_struct intr_tq; /* tasklet */ 87 int ce_msi_irq_num[CE_COUNT_MAX]; 88 bool use_register_windowing; 89 uint32_t register_window; 90 qdf_spinlock_t register_access_lock; 91 qdf_spinlock_t irq_lock; 92 bool grp_irqs_disabled; 93 94 void (*hif_ipci_get_soc_info)(struct hif_ipci_softc *sc, 95 struct device *dev); 96 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 97 uint32_t ep_awake_reset_fail; 98 uint32_t prevent_l1_fail; 99 uint32_t ep_awake_set_fail; 100 bool prevent_l1; 101 #endif 102 #ifdef FORCE_WAKE 103 struct hif_ipci_stats stats; 104 #endif 105 #ifdef HIF_CPU_PERF_AFFINE_MASK 106 /* Stores the affinity hint mask for each CE IRQ */ 107 qdf_cpu_mask ce_irq_cpu_mask[CE_COUNT_MAX]; 108 #endif 109 }; 110 111 int hif_configure_irq(struct hif_softc *sc); 112 113 /* 114 * There may be some pending tx frames during platform suspend. 115 * Suspend operation should be delayed until those tx frames are 116 * transferred from the host to target. This macro specifies how 117 * long suspend thread has to sleep before checking pending tx 118 * frame count. 119 */ 120 #define OL_ATH_TX_DRAIN_WAIT_DELAY 50 /* ms */ 121 122 #ifdef FORCE_WAKE 123 /** 124 * hif_print_ipci_stats() - Display HIF IPCI stats 125 * @ipci_scn - HIF ipci handle 126 * 127 * Return: None 128 */ 129 void hif_print_ipci_stats(struct hif_ipci_softc *ipci_scn); 130 #else 131 static inline 132 void hif_print_ipci_stats(struct hif_ipci_softc *ipci_scn) 133 { 134 } 135 #endif /* FORCE_WAKE */ 136 137 #endif /* __IATH_PCI_H__ */ 138