1 /* 2 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef __ATH_IPCI_H__ 19 #define __ATH_IPCI_H__ 20 21 #include <linux/version.h> 22 #include <linux/semaphore.h> 23 #include <linux/interrupt.h> 24 25 #define ATH_DBG_DEFAULT 0 26 #define DRAM_SIZE 0x000a8000 27 #include "hif.h" 28 #include "cepci.h" 29 #include "ce_main.h" 30 #include "hif_runtime_pm.h" 31 32 #ifdef FORCE_WAKE 33 /** 34 * struct hif_ipci_stats - Account for hif pci based statistics 35 * @mhi_force_wake_request_vote: vote for mhi 36 * @mhi_force_wake_failure: mhi force wake failure 37 * @mhi_force_wake_success: mhi force wake success 38 * @soc_force_wake_register_write_success: write to soc wake 39 * @soc_force_wake_failure: soc force wake failure 40 * @soc_force_wake_success: soc force wake success 41 * @mhi_force_wake_release_failure: mhi force wake release failure 42 * @mhi_force_wake_release_success: mhi force wake release success 43 * @soc_force_wake_release_success: soc force wake release 44 */ 45 struct hif_ipci_stats { 46 uint32_t mhi_force_wake_request_vote; 47 uint32_t mhi_force_wake_failure; 48 uint32_t mhi_force_wake_success; 49 uint32_t soc_force_wake_register_write_success; 50 uint32_t soc_force_wake_failure; 51 uint32_t soc_force_wake_success; 52 uint32_t mhi_force_wake_release_failure; 53 uint32_t mhi_force_wake_release_success; 54 uint32_t soc_force_wake_release_success; 55 }; 56 57 /* Register offset to wake the UMAC from power collapse */ 58 #define PCIE_REG_WAKE_UMAC_OFFSET 0x3004 59 /* Register to wake the UMAC from power collapse */ 60 #define PCIE_SOC_PCIE_REG_PCIE_SCRATCH_0_SOC_PCIE_REG (0x01E04000 + 0x40) 61 62 /* Timeout duration to validate UMAC wake status */ 63 #define FORCE_WAKE_DELAY_TIMEOUT_MS 1000 64 65 /* Validate UMAC status every 5ms */ 66 #define FORCE_WAKE_DELAY_MS 5 67 #endif /* FORCE_WAKE */ 68 69 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \ 70 defined(FEATURE_HIF_DELAYED_REG_WRITE) 71 #define EP_VOTE_POLL_TIME_US 50 72 #define EP_VOTE_POLL_TIME_CNT 3 73 #ifdef HAL_CONFIG_SLUB_DEBUG_ON 74 #define EP_WAKE_RESET_DELAY_TIMEOUT_MS 3 75 #else 76 #define EP_WAKE_RESET_DELAY_TIMEOUT_MS 10 77 #endif 78 #define EP_WAKE_DELAY_TIMEOUT_MS 10 79 #define EP_WAKE_RESET_DELAY_US 50 80 #define EP_WAKE_DELAY_US 200 81 #endif 82 83 #if defined(QCA_WIFI_WCN6450) 84 #define HIF_IPCI_DEVICE_ID WCN6450_DEVICE_ID 85 #elif defined(QCA_WIFI_QCA6750) 86 #define HIF_IPCI_DEVICE_ID QCA6750_DEVICE_ID 87 #else 88 #define HIF_IPCI_DEVICE_ID 0 89 #endif 90 91 struct hif_ipci_softc { 92 struct HIF_CE_state ce_sc; 93 void __iomem *mem; /* PCI address. */ 94 95 struct device *dev; /* For efficiency, should be first in struct */ 96 struct tasklet_struct intr_tq; /* tasklet */ 97 int ce_msi_irq_num[CE_COUNT_MAX]; 98 bool use_register_windowing; 99 uint32_t register_window; 100 qdf_spinlock_t register_access_lock; 101 qdf_spinlock_t irq_lock; 102 bool grp_irqs_disabled; 103 104 void (*hif_ipci_get_soc_info)(struct hif_ipci_softc *sc, 105 struct device *dev); 106 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \ 107 defined(FEATURE_HIF_DELAYED_REG_WRITE) 108 uint32_t ep_awake_reset_fail; 109 uint32_t prevent_l1_fail; 110 uint32_t ep_awake_set_fail; 111 bool prevent_l1; 112 #endif 113 #ifdef FORCE_WAKE 114 struct hif_ipci_stats stats; 115 #endif 116 #ifdef HIF_CPU_PERF_AFFINE_MASK 117 /* Stores the affinity hint mask for each CE IRQ */ 118 qdf_cpu_mask ce_irq_cpu_mask[CE_COUNT_MAX]; 119 #endif 120 }; 121 122 int hif_configure_irq(struct hif_softc *sc); 123 124 /* 125 * There may be some pending tx frames during platform suspend. 126 * Suspend operation should be delayed until those tx frames are 127 * transferred from the host to target. This macro specifies how 128 * long suspend thread has to sleep before checking pending tx 129 * frame count. 130 */ 131 #define OL_ATH_TX_DRAIN_WAIT_DELAY 50 /* ms */ 132 133 #ifdef FORCE_WAKE 134 /** 135 * hif_print_ipci_stats() - Display HIF IPCI stats 136 * @ipci_scn: HIF ipci handle 137 * 138 * Return: None 139 */ 140 void hif_print_ipci_stats(struct hif_ipci_softc *ipci_scn); 141 #else 142 static inline 143 void hif_print_ipci_stats(struct hif_ipci_softc *ipci_scn) 144 { 145 } 146 #endif /* FORCE_WAKE */ 147 148 #endif /* __IATH_PCI_H__ */ 149