1 /* 2 * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * NB: Inappropriate references to "HTC" are used in this (and other) 21 * HIF implementations. HTC is typically the calling layer, but it 22 * theoretically could be some alternative. 23 */ 24 25 /* 26 * This holds all state needed to process a pending send/recv interrupt. 27 * The information is saved here as soon as the interrupt occurs (thus 28 * allowing the underlying CE to re-use the ring descriptor). The 29 * information here is eventually processed by a completion processing 30 * thread. 31 */ 32 33 #ifndef __HIF_MAIN_H__ 34 #define __HIF_MAIN_H__ 35 36 #include <qdf_atomic.h> /* qdf_atomic_read */ 37 #include "qdf_lock.h" 38 #include "cepci.h" 39 #include "hif.h" 40 #include "multibus.h" 41 #include "hif_unit_test_suspend_i.h" 42 43 #define HIF_MIN_SLEEP_INACTIVITY_TIME_MS 50 44 #define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60 45 46 #define HIF_MAX_BUDGET 0xFFFF 47 48 #define HIF_STATS_INC(_handle, _field, _delta) \ 49 { \ 50 (_handle)->stats._field += _delta; \ 51 } 52 53 /* 54 * This macro implementation is exposed for efficiency only. 55 * The implementation may change and callers should 56 * consider the targid to be a completely opaque handle. 57 */ 58 #define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid))) 59 60 #ifdef QCA_WIFI_3_0 61 #define DISABLE_L1SS_STATES 1 62 #endif 63 64 #define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES 65 66 #ifdef QCA_WIFI_3_0_ADRASTEA 67 #define ADRASTEA_BU 1 68 #else 69 #define ADRASTEA_BU 0 70 #endif 71 72 #ifdef QCA_WIFI_3_0 73 #define HAS_FW_INDICATOR 0 74 #else 75 #define HAS_FW_INDICATOR 1 76 #endif 77 78 79 #define AR9888_DEVICE_ID (0x003c) 80 #define AR6320_DEVICE_ID (0x003e) 81 #define AR6320_FW_1_1 (0x11) 82 #define AR6320_FW_1_3 (0x13) 83 #define AR6320_FW_2_0 (0x20) 84 #define AR6320_FW_3_0 (0x30) 85 #define AR6320_FW_3_2 (0x32) 86 #define QCA6290_EMULATION_DEVICE_ID (0xabcd) 87 #define QCA6290_DEVICE_ID (0x1100) 88 #define QCN9000_DEVICE_ID (0x1104) 89 #define QCA6390_EMULATION_DEVICE_ID (0x0108) 90 #define QCA6390_DEVICE_ID (0x1101) 91 /* TODO: change IDs for HastingsPrime */ 92 #define QCA6490_EMULATION_DEVICE_ID (0x010a) 93 #define QCA6490_DEVICE_ID (0x1103) 94 95 /* TODO: change IDs for Moselle */ 96 #define QCA6750_EMULATION_DEVICE_ID (0x010c) 97 #define QCA6750_DEVICE_ID (0x1105) 98 99 #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021) 100 #define AR9887_DEVICE_ID (0x0050) 101 #define AR900B_DEVICE_ID (0x0040) 102 #define QCA9984_DEVICE_ID (0x0046) 103 #define QCA9888_DEVICE_ID (0x0056) 104 #ifndef IPQ4019_DEVICE_ID 105 #define IPQ4019_DEVICE_ID (0x12ef) 106 #endif 107 #define QCA8074_DEVICE_ID (0xffff) /* Todo: replace this with 108 actual number once available. 109 currently defining this to 0xffff for 110 emulation purpose */ 111 #define QCA8074V2_DEVICE_ID (0xfffe) /* Todo: replace this with actual number */ 112 #define QCA6018_DEVICE_ID (0xfffd) /* Todo: replace this with actual number */ 113 /* Genoa */ 114 #define QCN7605_DEVICE_ID (0x1102) /* Genoa PCIe device ID*/ 115 #define QCN7605_COMPOSITE (0x9901) 116 #define QCN7605_STANDALONE (0x9900) 117 #define QCN7605_STANDALONE_V2 (0x9902) 118 #define QCN7605_COMPOSITE_V2 (0x9903) 119 120 #define RUMIM2M_DEVICE_ID_NODE0 0xabc0 121 #define RUMIM2M_DEVICE_ID_NODE1 0xabc1 122 #define RUMIM2M_DEVICE_ID_NODE2 0xabc2 123 #define RUMIM2M_DEVICE_ID_NODE3 0xabc3 124 #define RUMIM2M_DEVICE_ID_NODE4 0xaa10 125 #define RUMIM2M_DEVICE_ID_NODE5 0xaa11 126 127 #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn) 128 #define HIF_GET_IPCI_SOFTC(scn) ((struct hif_ipci_softc *)scn) 129 #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn) 130 #define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn) 131 #define HIF_GET_USB_SOFTC(scn) ((struct hif_usb_softc *)scn) 132 #define HIF_GET_USB_DEVICE(scn) ((struct HIF_DEVICE_USB *)scn) 133 #define HIF_GET_SOFTC(scn) ((struct hif_softc *)scn) 134 #define GET_HIF_OPAQUE_HDL(scn) ((struct hif_opaque_softc *)scn) 135 136 struct hif_ce_stats { 137 int hif_pipe_no_resrc_count; 138 int ce_ring_delta_fail_count; 139 }; 140 141 /* 142 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 143 * for defined here 144 */ 145 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 146 struct ce_desc_hist { 147 qdf_atomic_t history_index[CE_COUNT_MAX]; 148 uint32_t enable[CE_COUNT_MAX]; 149 bool data_enable[CE_COUNT_MAX]; 150 qdf_mutex_t ce_dbg_datamem_lock[CE_COUNT_MAX]; 151 uint32_t hist_index; 152 uint32_t hist_id; 153 void *hist_ev[CE_COUNT_MAX]; 154 }; 155 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 156 157 /** 158 * struct hif_cfg() - store ini config parameters in hif layer 159 * @ce_status_ring_timer_threshold: ce status ring timer threshold 160 * @ce_status_ring_batch_count_threshold: ce status ring batch count threshold 161 */ 162 struct hif_cfg { 163 uint16_t ce_status_ring_timer_threshold; 164 uint8_t ce_status_ring_batch_count_threshold; 165 }; 166 167 struct hif_softc { 168 struct hif_opaque_softc osc; 169 struct hif_config_info hif_config; 170 struct hif_target_info target_info; 171 void __iomem *mem; 172 enum qdf_bus_type bus_type; 173 struct hif_bus_ops bus_ops; 174 void *ce_id_to_state[CE_COUNT_MAX]; 175 qdf_device_t qdf_dev; 176 bool hif_init_done; 177 bool request_irq_done; 178 bool ext_grp_irq_configured; 179 uint8_t ce_latency_stats; 180 /* Packet statistics */ 181 struct hif_ce_stats pkt_stats; 182 enum hif_target_status target_status; 183 uint64_t event_disable_mask; 184 185 struct targetdef_s *targetdef; 186 struct ce_reg_def *target_ce_def; 187 struct hostdef_s *hostdef; 188 struct host_shadow_regs_s *host_shadow_regs; 189 190 bool recovery; 191 bool notice_send; 192 bool per_ce_irq; 193 uint32_t ce_irq_summary; 194 /* No of copy engines supported */ 195 unsigned int ce_count; 196 atomic_t active_tasklet_cnt; 197 atomic_t active_grp_tasklet_cnt; 198 atomic_t link_suspended; 199 uint32_t *vaddr_rri_on_ddr; 200 qdf_dma_addr_t paddr_rri_on_ddr; 201 int linkstate_vote; 202 bool fastpath_mode_on; 203 atomic_t tasklet_from_intr; 204 int htc_htt_tx_endpoint; 205 qdf_dma_addr_t mem_pa; 206 bool athdiag_procfs_inited; 207 #ifdef FEATURE_NAPI 208 struct qca_napi_data napi_data; 209 #endif /* FEATURE_NAPI */ 210 /* stores ce_service_max_yield_time in ns */ 211 unsigned long long ce_service_max_yield_time; 212 uint8_t ce_service_max_rx_ind_flush; 213 struct hif_driver_state_callbacks callbacks; 214 uint32_t hif_con_param; 215 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 216 uint32_t nss_wifi_ol_mode; 217 #endif 218 void *hal_soc; 219 struct hif_ut_suspend_context ut_suspend_ctx; 220 uint32_t hif_attribute; 221 int wake_irq; 222 int disable_wake_irq; 223 void (*initial_wakeup_cb)(void *); 224 void *initial_wakeup_priv; 225 #ifdef REMOVE_PKT_LOG 226 /* Handle to pktlog device */ 227 void *pktlog_dev; 228 #endif 229 230 /* 231 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 232 * for defined here 233 */ 234 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 235 struct ce_desc_hist hif_ce_desc_hist; 236 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 237 #ifdef IPA_OFFLOAD 238 qdf_shared_mem_t *ipa_ce_ring; 239 #endif 240 struct hif_cfg ini_cfg; 241 }; 242 243 static inline 244 void *hif_get_hal_handle(struct hif_opaque_softc *hif_hdl) 245 { 246 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 247 248 if (!sc) 249 return NULL; 250 251 return sc->hal_soc; 252 } 253 254 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 255 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 256 { 257 return !!(sc->nss_wifi_ol_mode); 258 } 259 #else 260 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 261 { 262 return false; 263 } 264 #endif 265 266 static inline uint8_t hif_is_attribute_set(struct hif_softc *sc, 267 uint32_t hif_attrib) 268 { 269 return sc->hif_attribute == hif_attrib; 270 } 271 272 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 273 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 274 { 275 struct hif_softc *scn = (struct hif_softc *)hif_handle; 276 277 scn->event_disable_mask = HIF_EVENT_HIST_DISABLE_MASK; 278 } 279 #else 280 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 281 { 282 } 283 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 284 285 A_target_id_t hif_get_target_id(struct hif_softc *scn); 286 void hif_dump_pipe_debug_count(struct hif_softc *scn); 287 void hif_display_bus_stats(struct hif_opaque_softc *scn); 288 void hif_clear_bus_stats(struct hif_opaque_softc *scn); 289 bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count); 290 void hif_shutdown_device(struct hif_opaque_softc *hif_ctx); 291 int hif_bus_configure(struct hif_softc *scn); 292 void hif_cancel_deferred_target_sleep(struct hif_softc *scn); 293 int hif_config_ce(struct hif_softc *scn); 294 void hif_unconfig_ce(struct hif_softc *scn); 295 void hif_ce_prepare_config(struct hif_softc *scn); 296 QDF_STATUS hif_ce_open(struct hif_softc *scn); 297 void hif_ce_close(struct hif_softc *scn); 298 int athdiag_procfs_init(void *scn); 299 void athdiag_procfs_remove(void); 300 /* routine to modify the initial buffer count to be allocated on an os 301 * platform basis. Platform owner will need to modify this as needed 302 */ 303 qdf_size_t init_buffer_count(qdf_size_t maxSize); 304 305 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg); 306 int hif_get_device_type(uint32_t device_id, 307 uint32_t revision_id, 308 uint32_t *hif_type, uint32_t *target_type); 309 /*These functions are exposed to HDD*/ 310 void hif_nointrs(struct hif_softc *scn); 311 void hif_bus_close(struct hif_softc *ol_sc); 312 QDF_STATUS hif_bus_open(struct hif_softc *ol_sc, 313 enum qdf_bus_type bus_type); 314 QDF_STATUS hif_enable_bus(struct hif_softc *ol_sc, struct device *dev, 315 void *bdev, const struct hif_bus_id *bid, enum hif_enable_type type); 316 void hif_disable_bus(struct hif_softc *scn); 317 void hif_bus_prevent_linkdown(struct hif_softc *scn, bool flag); 318 int hif_bus_get_context_size(enum qdf_bus_type bus_type); 319 void hif_read_phy_mem_base(struct hif_softc *scn, qdf_dma_addr_t *bar_value); 320 uint32_t hif_get_conparam(struct hif_softc *scn); 321 struct hif_driver_state_callbacks *hif_get_callbacks_handle( 322 struct hif_softc *scn); 323 bool hif_is_driver_unloading(struct hif_softc *scn); 324 bool hif_is_load_or_unload_in_progress(struct hif_softc *scn); 325 bool hif_is_recovery_in_progress(struct hif_softc *scn); 326 bool hif_is_target_ready(struct hif_softc *scn); 327 void hif_wlan_disable(struct hif_softc *scn); 328 int hif_target_sleep_state_adjust(struct hif_softc *scn, 329 bool sleep_ok, 330 bool wait_for_it); 331 /** 332 * hif_get_rx_ctx_id() - Returns NAPI instance ID based on CE ID 333 * @ctx_id: Rx CE context ID 334 * @hif_hdl: HIF Context 335 * 336 * Return: Rx instance ID 337 */ 338 int hif_get_rx_ctx_id(int ctx_id, struct hif_opaque_softc *hif_hdl); 339 void hif_ramdump_handler(struct hif_opaque_softc *scn); 340 #ifdef HIF_USB 341 void hif_usb_get_hw_info(struct hif_softc *scn); 342 void hif_usb_ramdump_handler(struct hif_opaque_softc *scn); 343 #else 344 static inline void hif_usb_get_hw_info(struct hif_softc *scn) {} 345 static inline void hif_usb_ramdump_handler(struct hif_opaque_softc *scn) {} 346 #endif 347 348 /** 349 * hif_wake_interrupt_handler() - interrupt handler for standalone wake irq 350 * @irq: the irq number that fired 351 * @context: the opaque pointer passed to request_irq() 352 * 353 * Return: an irq return type 354 */ 355 irqreturn_t hif_wake_interrupt_handler(int irq, void *context); 356 357 #ifdef HIF_SNOC 358 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc); 359 #else 360 static inline 361 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc) 362 { 363 return true; 364 } 365 #endif 366 367 #ifdef ADRASTEA_RRI_ON_DDR 368 void hif_uninit_rri_on_ddr(struct hif_softc *scn); 369 #else 370 static inline 371 void hif_uninit_rri_on_ddr(struct hif_softc *scn) {} 372 #endif 373 #endif /* __HIF_MAIN_H__ */ 374