1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * NB: Inappropriate references to "HTC" are used in this (and other) 22 * HIF implementations. HTC is typically the calling layer, but it 23 * theoretically could be some alternative. 24 */ 25 26 /* 27 * This holds all state needed to process a pending send/recv interrupt. 28 * The information is saved here as soon as the interrupt occurs (thus 29 * allowing the underlying CE to re-use the ring descriptor). The 30 * information here is eventually processed by a completion processing 31 * thread. 32 */ 33 34 #ifndef __HIF_MAIN_H__ 35 #define __HIF_MAIN_H__ 36 37 #include <qdf_atomic.h> /* qdf_atomic_read */ 38 #include "qdf_lock.h" 39 #include "cepci.h" 40 #include "hif.h" 41 #include "multibus.h" 42 #include "hif_unit_test_suspend_i.h" 43 #ifdef HIF_CE_LOG_INFO 44 #include "qdf_notifier.h" 45 #endif 46 47 #define HIF_MIN_SLEEP_INACTIVITY_TIME_MS 50 48 #define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60 49 50 #define HIF_MAX_BUDGET 0xFFFF 51 52 #define HIF_STATS_INC(_handle, _field, _delta) \ 53 { \ 54 (_handle)->stats._field += _delta; \ 55 } 56 57 /* 58 * This macro implementation is exposed for efficiency only. 59 * The implementation may change and callers should 60 * consider the targid to be a completely opaque handle. 61 */ 62 #define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid))) 63 64 #ifdef QCA_WIFI_3_0 65 #define DISABLE_L1SS_STATES 1 66 #endif 67 68 #define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES 69 70 #ifdef QCA_WIFI_3_0_ADRASTEA 71 #define ADRASTEA_BU 1 72 #else 73 #define ADRASTEA_BU 0 74 #endif 75 76 #ifdef QCA_WIFI_3_0 77 #define HAS_FW_INDICATOR 0 78 #else 79 #define HAS_FW_INDICATOR 1 80 #endif 81 82 83 #define AR9888_DEVICE_ID (0x003c) 84 #define AR6320_DEVICE_ID (0x003e) 85 #define AR6320_FW_1_1 (0x11) 86 #define AR6320_FW_1_3 (0x13) 87 #define AR6320_FW_2_0 (0x20) 88 #define AR6320_FW_3_0 (0x30) 89 #define AR6320_FW_3_2 (0x32) 90 #define QCA6290_EMULATION_DEVICE_ID (0xabcd) 91 #define QCA6290_DEVICE_ID (0x1100) 92 #define QCN9000_DEVICE_ID (0x1104) 93 #define QCN9224_DEVICE_ID (0x1109) 94 #define QCN6122_DEVICE_ID (0xFFFB) 95 #define QCN9160_DEVICE_ID (0xFFF8) 96 #define QCA6390_EMULATION_DEVICE_ID (0x0108) 97 #define QCA6390_DEVICE_ID (0x1101) 98 /* TODO: change IDs for HastingsPrime */ 99 #define QCA6490_EMULATION_DEVICE_ID (0x010a) 100 #define QCA6490_DEVICE_ID (0x1103) 101 #define MANGO_DEVICE_ID (0x110a) 102 103 /* TODO: change IDs for Moselle */ 104 #define QCA6750_EMULATION_DEVICE_ID (0x010c) 105 #define QCA6750_DEVICE_ID (0x1105) 106 107 /* TODO: change IDs for Hamilton */ 108 #define KIWI_DEVICE_ID (0x1107) 109 110 #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021) 111 #define AR9887_DEVICE_ID (0x0050) 112 #define AR900B_DEVICE_ID (0x0040) 113 #define QCA9984_DEVICE_ID (0x0046) 114 #define QCA9888_DEVICE_ID (0x0056) 115 #define QCA8074_DEVICE_ID (0xffff) /* Todo: replace this with 116 actual number once available. 117 currently defining this to 0xffff for 118 emulation purpose */ 119 #define QCA8074V2_DEVICE_ID (0xfffe) /* Todo: replace this with actual number */ 120 #define QCA6018_DEVICE_ID (0xfffd) /* Todo: replace this with actual number */ 121 #define QCA5018_DEVICE_ID (0xfffc) /* Todo: replace this with actual number */ 122 #define QCA9574_DEVICE_ID (0xfffa) 123 #define QCA5332_DEVICE_ID (0xfff9) 124 /* Genoa */ 125 #define QCN7605_DEVICE_ID (0x1102) /* Genoa PCIe device ID*/ 126 #define QCN7605_COMPOSITE (0x9901) 127 #define QCN7605_STANDALONE (0x9900) 128 #define QCN7605_STANDALONE_V2 (0x9902) 129 #define QCN7605_COMPOSITE_V2 (0x9903) 130 131 #define RUMIM2M_DEVICE_ID_NODE0 0xabc0 132 #define RUMIM2M_DEVICE_ID_NODE1 0xabc1 133 #define RUMIM2M_DEVICE_ID_NODE2 0xabc2 134 #define RUMIM2M_DEVICE_ID_NODE3 0xabc3 135 #define RUMIM2M_DEVICE_ID_NODE4 0xaa10 136 #define RUMIM2M_DEVICE_ID_NODE5 0xaa11 137 138 #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn) 139 #define HIF_GET_IPCI_SOFTC(scn) ((struct hif_ipci_softc *)scn) 140 #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn) 141 #define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn) 142 #define HIF_GET_USB_SOFTC(scn) ((struct hif_usb_softc *)scn) 143 #define HIF_GET_USB_DEVICE(scn) ((struct HIF_DEVICE_USB *)scn) 144 #define HIF_GET_SOFTC(scn) ((struct hif_softc *)scn) 145 #define GET_HIF_OPAQUE_HDL(scn) ((struct hif_opaque_softc *)scn) 146 147 #ifdef QCA_WIFI_QCN9224 148 #define NUM_CE_AVAILABLE 16 149 #else 150 #define NUM_CE_AVAILABLE 12 151 #endif 152 /* Add 1 here to store default configuration in index 0 */ 153 #define NUM_CE_CONTEXT (NUM_CE_AVAILABLE + 1) 154 155 #define CE_INTERRUPT_IDX(x) x 156 157 struct ce_int_assignment { 158 uint8_t msi_idx[NUM_CE_AVAILABLE]; 159 }; 160 161 struct hif_ce_stats { 162 int hif_pipe_no_resrc_count; 163 int ce_ring_delta_fail_count; 164 }; 165 166 #ifdef HIF_DETECTION_LATENCY_ENABLE 167 struct hif_latency_detect { 168 qdf_timer_t detect_latency_timer; 169 uint32_t detect_latency_timer_timeout; 170 bool is_timer_started; 171 bool enable_detection; 172 /* threshold when stall happens */ 173 uint32_t detect_latency_threshold; 174 int ce2_tasklet_sched_cpuid; 175 qdf_time_t ce2_tasklet_sched_time; 176 qdf_time_t ce2_tasklet_exec_time; 177 qdf_time_t credit_request_time; 178 qdf_time_t credit_report_time; 179 }; 180 #endif 181 182 /* 183 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 184 * for defined here 185 */ 186 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 187 188 #define HIF_CE_MAX_LATEST_HIST 2 189 190 struct latest_evt_history { 191 uint64_t irq_entry_ts; 192 uint64_t bh_entry_ts; 193 uint64_t bh_resched_ts; 194 uint64_t bh_exit_ts; 195 uint64_t bh_work_ts; 196 int cpu_id; 197 uint32_t ring_hp; 198 uint32_t ring_tp; 199 }; 200 201 struct ce_desc_hist { 202 qdf_atomic_t history_index[CE_COUNT_MAX]; 203 uint8_t ce_id_hist_map[CE_COUNT_MAX]; 204 bool enable[CE_COUNT_MAX]; 205 bool data_enable[CE_COUNT_MAX]; 206 qdf_mutex_t ce_dbg_datamem_lock[CE_COUNT_MAX]; 207 uint32_t hist_index; 208 uint32_t hist_id; 209 void *hist_ev[CE_COUNT_MAX]; 210 struct latest_evt_history latest_evt[HIF_CE_MAX_LATEST_HIST]; 211 }; 212 213 void hif_record_latest_evt(struct ce_desc_hist *ce_hist, 214 uint8_t type, 215 int ce_id, uint64_t time, 216 uint32_t hp, uint32_t tp); 217 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 218 219 /** 220 * struct hif_cfg() - store ini config parameters in hif layer 221 * @ce_status_ring_timer_threshold: ce status ring timer threshold 222 * @ce_status_ring_batch_count_threshold: ce status ring batch count threshold 223 * @disable_wake_irq: disable wake irq 224 */ 225 struct hif_cfg { 226 uint16_t ce_status_ring_timer_threshold; 227 uint8_t ce_status_ring_batch_count_threshold; 228 bool disable_wake_irq; 229 }; 230 231 #ifdef DP_UMAC_HW_RESET_SUPPORT 232 /** 233 * struct hif_umac_reset_ctx - UMAC HW reset context at HIF layer 234 * @intr_tq: Tasklet structure 235 * @cb_handler: Callback handler 236 * @cb_ctx: Argument to be passed to @cb_handler 237 * @os_irq: Interrupt number for this IRQ 238 * @irq_configured: Whether the IRQ has been configured 239 */ 240 struct hif_umac_reset_ctx { 241 struct tasklet_struct intr_tq; 242 int (*cb_handler)(void *cb_ctx); 243 void *cb_ctx; 244 uint32_t os_irq; 245 bool irq_configured; 246 }; 247 #endif 248 249 struct hif_softc { 250 struct hif_opaque_softc osc; 251 struct hif_config_info hif_config; 252 struct hif_target_info target_info; 253 void __iomem *mem; 254 void __iomem *mem_ce; 255 void __iomem *mem_cmem; 256 enum qdf_bus_type bus_type; 257 struct hif_bus_ops bus_ops; 258 void *ce_id_to_state[CE_COUNT_MAX]; 259 qdf_device_t qdf_dev; 260 bool hif_init_done; 261 bool request_irq_done; 262 bool ext_grp_irq_configured; 263 bool free_irq_done; 264 uint8_t ce_latency_stats; 265 /* Packet statistics */ 266 struct hif_ce_stats pkt_stats; 267 enum hif_target_status target_status; 268 uint64_t event_enable_mask; 269 270 struct targetdef_s *targetdef; 271 struct ce_reg_def *target_ce_def; 272 struct hostdef_s *hostdef; 273 struct host_shadow_regs_s *host_shadow_regs; 274 275 bool recovery; 276 bool notice_send; 277 bool per_ce_irq; 278 uint32_t ce_irq_summary; 279 /* No of copy engines supported */ 280 unsigned int ce_count; 281 struct ce_int_assignment *int_assignment; 282 atomic_t active_tasklet_cnt; 283 atomic_t active_grp_tasklet_cnt; 284 atomic_t link_suspended; 285 uint32_t *vaddr_rri_on_ddr; 286 qdf_dma_addr_t paddr_rri_on_ddr; 287 #ifdef CONFIG_BYPASS_QMI 288 uint32_t *vaddr_qmi_bypass; 289 qdf_dma_addr_t paddr_qmi_bypass; 290 #endif 291 int linkstate_vote; 292 bool fastpath_mode_on; 293 atomic_t tasklet_from_intr; 294 int htc_htt_tx_endpoint; 295 qdf_dma_addr_t mem_pa; 296 bool athdiag_procfs_inited; 297 #ifdef FEATURE_NAPI 298 struct qca_napi_data napi_data; 299 #endif /* FEATURE_NAPI */ 300 /* stores ce_service_max_yield_time in ns */ 301 unsigned long long ce_service_max_yield_time; 302 uint8_t ce_service_max_rx_ind_flush; 303 struct hif_driver_state_callbacks callbacks; 304 uint32_t hif_con_param; 305 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 306 uint32_t nss_wifi_ol_mode; 307 #endif 308 void *hal_soc; 309 struct hif_ut_suspend_context ut_suspend_ctx; 310 uint32_t hif_attribute; 311 int wake_irq; 312 hif_pm_wake_irq_type wake_irq_type; 313 void (*initial_wakeup_cb)(void *); 314 void *initial_wakeup_priv; 315 #ifdef REMOVE_PKT_LOG 316 /* Handle to pktlog device */ 317 void *pktlog_dev; 318 #endif 319 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 320 /* Pointer to the srng event history */ 321 struct hif_event_history *evt_hist[HIF_NUM_INT_CONTEXTS]; 322 #endif 323 324 /* 325 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 326 * for defined here 327 */ 328 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 329 struct ce_desc_hist hif_ce_desc_hist; 330 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 331 #ifdef IPA_OFFLOAD 332 qdf_shared_mem_t *ipa_ce_ring; 333 #endif 334 struct hif_cfg ini_cfg; 335 #ifdef HIF_CE_LOG_INFO 336 qdf_notif_block hif_recovery_notifier; 337 #endif 338 #ifdef HIF_CPU_PERF_AFFINE_MASK 339 /* The CPU hotplug event registration handle */ 340 struct qdf_cpuhp_handler *cpuhp_event_handle; 341 #endif 342 uint32_t irq_unlazy_disable; 343 /* Should the unlzay support for interrupt delivery be disabled */ 344 /* Flag to indicate whether bus is suspended */ 345 bool bus_suspended; 346 bool pktlog_init; 347 #ifdef FEATURE_RUNTIME_PM 348 /* Variable to track the link state change in RTPM */ 349 qdf_atomic_t pm_link_state; 350 #endif 351 #ifdef HIF_DETECTION_LATENCY_ENABLE 352 struct hif_latency_detect latency_detect; 353 #endif 354 #ifdef FEATURE_RUNTIME_PM 355 qdf_runtime_lock_t prevent_linkdown_lock; 356 #endif 357 #ifdef SYSTEM_PM_CHECK 358 qdf_atomic_t sys_pm_state; 359 #endif 360 #if defined(HIF_IPCI) && defined(FEATURE_HAL_DELAYED_REG_WRITE) 361 qdf_atomic_t dp_ep_vote_access; 362 qdf_atomic_t ep_vote_access; 363 #endif 364 /* CMEM address target reserved for host usage */ 365 uint64_t cmem_start; 366 /* CMEM size target reserved */ 367 uint64_t cmem_size; 368 #ifdef DP_UMAC_HW_RESET_SUPPORT 369 struct hif_umac_reset_ctx umac_reset_ctx; 370 #endif 371 }; 372 373 static inline 374 void *hif_get_hal_handle(struct hif_opaque_softc *hif_hdl) 375 { 376 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 377 378 if (!sc) 379 return NULL; 380 381 return sc->hal_soc; 382 } 383 384 /** 385 * hif_get_cmem_info() - get CMEM address and size from HIF handle 386 * @hif_hdl: HIF handle pointer 387 * @cmem_start: pointer for CMEM address 388 * @cmem_size: pointer for CMEM size 389 * 390 * Return: None. 391 */ 392 static inline 393 void hif_get_cmem_info(struct hif_opaque_softc *hif_hdl, 394 uint64_t *cmem_start, 395 uint64_t *cmem_size) 396 { 397 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 398 399 *cmem_start = sc->cmem_start; 400 *cmem_size = sc->cmem_size; 401 } 402 403 /** 404 * hif_get_num_active_tasklets() - get the number of active 405 * tasklets pending to be completed. 406 * @scn: HIF context 407 * 408 * Returns: the number of tasklets which are active 409 */ 410 static inline int hif_get_num_active_tasklets(struct hif_softc *scn) 411 { 412 return qdf_atomic_read(&scn->active_tasklet_cnt); 413 } 414 415 /** 416 * Max waiting time during Runtime PM suspend to finish all 417 * the tasks. This is in the multiple of 10ms. 418 */ 419 #define HIF_TASK_DRAIN_WAIT_CNT 25 420 421 /** 422 * hif_try_complete_tasks() - Try to complete all the pending tasks 423 * @scn: HIF context 424 * 425 * Try to complete all the pending datapath tasks, i.e. tasklets, 426 * DP group tasklets and works which are queued, in a given time 427 * slot. 428 * 429 * Returns: QDF_STATUS_SUCCESS if all the tasks were completed 430 * QDF error code, if the time slot exhausted 431 */ 432 QDF_STATUS hif_try_complete_tasks(struct hif_softc *scn); 433 434 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 435 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 436 { 437 return !!(sc->nss_wifi_ol_mode); 438 } 439 #else 440 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 441 { 442 return false; 443 } 444 #endif 445 446 static inline uint8_t hif_is_attribute_set(struct hif_softc *sc, 447 uint32_t hif_attrib) 448 { 449 return sc->hif_attribute == hif_attrib; 450 } 451 452 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 453 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 454 { 455 struct hif_softc *scn = (struct hif_softc *)hif_handle; 456 457 scn->event_enable_mask = HIF_EVENT_HIST_ENABLE_MASK; 458 } 459 #else 460 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 461 { 462 } 463 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 464 465 A_target_id_t hif_get_target_id(struct hif_softc *scn); 466 void hif_dump_pipe_debug_count(struct hif_softc *scn); 467 void hif_display_bus_stats(struct hif_opaque_softc *scn); 468 void hif_clear_bus_stats(struct hif_opaque_softc *scn); 469 bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count); 470 void hif_shutdown_device(struct hif_opaque_softc *hif_ctx); 471 int hif_bus_configure(struct hif_softc *scn); 472 void hif_cancel_deferred_target_sleep(struct hif_softc *scn); 473 int hif_config_ce(struct hif_softc *scn); 474 int hif_config_ce_pktlog(struct hif_opaque_softc *hif_ctx); 475 int hif_config_ce_by_id(struct hif_softc *scn, int pipe_num); 476 void hif_unconfig_ce(struct hif_softc *scn); 477 void hif_ce_prepare_config(struct hif_softc *scn); 478 QDF_STATUS hif_ce_open(struct hif_softc *scn); 479 void hif_ce_close(struct hif_softc *scn); 480 int athdiag_procfs_init(void *scn); 481 void athdiag_procfs_remove(void); 482 /* routine to modify the initial buffer count to be allocated on an os 483 * platform basis. Platform owner will need to modify this as needed 484 */ 485 qdf_size_t init_buffer_count(qdf_size_t maxSize); 486 487 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg); 488 int hif_get_device_type(uint32_t device_id, 489 uint32_t revision_id, 490 uint32_t *hif_type, uint32_t *target_type); 491 /*These functions are exposed to HDD*/ 492 void hif_nointrs(struct hif_softc *scn); 493 void hif_bus_close(struct hif_softc *ol_sc); 494 QDF_STATUS hif_bus_open(struct hif_softc *ol_sc, 495 enum qdf_bus_type bus_type); 496 QDF_STATUS hif_enable_bus(struct hif_softc *ol_sc, struct device *dev, 497 void *bdev, const struct hif_bus_id *bid, enum hif_enable_type type); 498 void hif_disable_bus(struct hif_softc *scn); 499 void hif_bus_prevent_linkdown(struct hif_softc *scn, bool flag); 500 int hif_bus_get_context_size(enum qdf_bus_type bus_type); 501 void hif_read_phy_mem_base(struct hif_softc *scn, qdf_dma_addr_t *bar_value); 502 uint32_t hif_get_conparam(struct hif_softc *scn); 503 struct hif_driver_state_callbacks *hif_get_callbacks_handle( 504 struct hif_softc *scn); 505 bool hif_is_driver_unloading(struct hif_softc *scn); 506 bool hif_is_load_or_unload_in_progress(struct hif_softc *scn); 507 bool hif_is_recovery_in_progress(struct hif_softc *scn); 508 bool hif_is_target_ready(struct hif_softc *scn); 509 510 /** 511 * hif_get_bandwidth_level() - API to get the current bandwidth level 512 * @scn: HIF Context 513 * 514 * Return: PLD bandwidth level 515 */ 516 int hif_get_bandwidth_level(struct hif_opaque_softc *hif_handle); 517 518 void hif_wlan_disable(struct hif_softc *scn); 519 int hif_target_sleep_state_adjust(struct hif_softc *scn, 520 bool sleep_ok, 521 bool wait_for_it); 522 523 #ifdef DP_MEM_PRE_ALLOC 524 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 525 qdf_size_t size, 526 qdf_dma_addr_t *paddr, 527 uint32_t ring_type, 528 uint8_t *is_mem_prealloc); 529 530 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 531 qdf_size_t size, 532 void *vaddr, 533 qdf_dma_addr_t paddr, 534 qdf_dma_context_t memctx, 535 uint8_t is_mem_prealloc); 536 #else 537 static inline 538 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 539 qdf_size_t size, 540 qdf_dma_addr_t *paddr, 541 uint32_t ring_type, 542 uint8_t *is_mem_prealloc) 543 { 544 return qdf_mem_alloc_consistent(scn->qdf_dev, 545 scn->qdf_dev->dev, 546 size, 547 paddr); 548 } 549 550 static inline 551 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 552 qdf_size_t size, 553 void *vaddr, 554 qdf_dma_addr_t paddr, 555 qdf_dma_context_t memctx, 556 uint8_t is_mem_prealloc) 557 { 558 return qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 559 size, vaddr, paddr, memctx); 560 } 561 #endif 562 563 /** 564 * hif_get_rx_ctx_id() - Returns NAPI instance ID based on CE ID 565 * @ctx_id: Rx CE context ID 566 * @hif_hdl: HIF Context 567 * 568 * Return: Rx instance ID 569 */ 570 int hif_get_rx_ctx_id(int ctx_id, struct hif_opaque_softc *hif_hdl); 571 void hif_ramdump_handler(struct hif_opaque_softc *scn); 572 #ifdef HIF_USB 573 void hif_usb_get_hw_info(struct hif_softc *scn); 574 void hif_usb_ramdump_handler(struct hif_opaque_softc *scn); 575 #else 576 static inline void hif_usb_get_hw_info(struct hif_softc *scn) {} 577 static inline void hif_usb_ramdump_handler(struct hif_opaque_softc *scn) {} 578 #endif 579 580 /** 581 * hif_wake_interrupt_handler() - interrupt handler for standalone wake irq 582 * @irq: the irq number that fired 583 * @context: the opaque pointer passed to request_irq() 584 * 585 * Return: an irq return type 586 */ 587 irqreturn_t hif_wake_interrupt_handler(int irq, void *context); 588 589 #ifdef HIF_SNOC 590 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc); 591 #else 592 static inline 593 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc) 594 { 595 return true; 596 } 597 #endif 598 599 #ifdef ADRASTEA_RRI_ON_DDR 600 void hif_uninit_rri_on_ddr(struct hif_softc *scn); 601 #else 602 static inline 603 void hif_uninit_rri_on_ddr(struct hif_softc *scn) {} 604 #endif 605 void hif_cleanup_static_buf_to_target(struct hif_softc *scn); 606 607 #ifdef FEATURE_RUNTIME_PM 608 /** 609 * hif_runtime_prevent_linkdown() - prevent or allow a runtime pm from occurring 610 * @scn: hif context 611 * @is_get: prevent linkdown if true otherwise allow 612 * 613 * this api should only be called as part of bus prevent linkdown 614 */ 615 void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get); 616 #else 617 static inline 618 void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get) 619 { 620 } 621 #endif 622 623 #endif /* __HIF_MAIN_H__ */ 624