1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * NB: Inappropriate references to "HTC" are used in this (and other) 22 * HIF implementations. HTC is typically the calling layer, but it 23 * theoretically could be some alternative. 24 */ 25 26 /* 27 * This holds all state needed to process a pending send/recv interrupt. 28 * The information is saved here as soon as the interrupt occurs (thus 29 * allowing the underlying CE to re-use the ring descriptor). The 30 * information here is eventually processed by a completion processing 31 * thread. 32 */ 33 34 #ifndef __HIF_MAIN_H__ 35 #define __HIF_MAIN_H__ 36 37 #include <qdf_atomic.h> /* qdf_atomic_read */ 38 #include "qdf_lock.h" 39 #include "cepci.h" 40 #include "hif.h" 41 #include "multibus.h" 42 #include "hif_unit_test_suspend_i.h" 43 #ifdef HIF_CE_LOG_INFO 44 #include "qdf_notifier.h" 45 #endif 46 47 #define HIF_MIN_SLEEP_INACTIVITY_TIME_MS 50 48 #define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60 49 50 #define HIF_MAX_BUDGET 0xFFFF 51 52 #define HIF_STATS_INC(_handle, _field, _delta) \ 53 { \ 54 (_handle)->stats._field += _delta; \ 55 } 56 57 /* 58 * This macro implementation is exposed for efficiency only. 59 * The implementation may change and callers should 60 * consider the targid to be a completely opaque handle. 61 */ 62 #define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid))) 63 64 #ifdef QCA_WIFI_3_0 65 #define DISABLE_L1SS_STATES 1 66 #endif 67 68 #define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES 69 70 #ifdef QCA_WIFI_3_0_ADRASTEA 71 #define ADRASTEA_BU 1 72 #else 73 #define ADRASTEA_BU 0 74 #endif 75 76 #ifdef QCA_WIFI_3_0 77 #define HAS_FW_INDICATOR 0 78 #else 79 #define HAS_FW_INDICATOR 1 80 #endif 81 82 83 #define AR9888_DEVICE_ID (0x003c) 84 #define AR6320_DEVICE_ID (0x003e) 85 #define AR6320_FW_1_1 (0x11) 86 #define AR6320_FW_1_3 (0x13) 87 #define AR6320_FW_2_0 (0x20) 88 #define AR6320_FW_3_0 (0x30) 89 #define AR6320_FW_3_2 (0x32) 90 #define QCA6290_EMULATION_DEVICE_ID (0xabcd) 91 #define QCA6290_DEVICE_ID (0x1100) 92 #define QCN9000_DEVICE_ID (0x1104) 93 #define QCN9224_DEVICE_ID (0x1109) 94 #define QCN6122_DEVICE_ID (0xFFFB) 95 #define QCA6390_EMULATION_DEVICE_ID (0x0108) 96 #define QCA6390_DEVICE_ID (0x1101) 97 /* TODO: change IDs for HastingsPrime */ 98 #define QCA6490_EMULATION_DEVICE_ID (0x010a) 99 #define QCA6490_DEVICE_ID (0x1103) 100 101 /* TODO: change IDs for Moselle */ 102 #define QCA6750_EMULATION_DEVICE_ID (0x010c) 103 #define QCA6750_DEVICE_ID (0x1105) 104 105 /* TODO: change IDs for Hamilton */ 106 #define KIWI_DEVICE_ID (0x1107) 107 108 #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021) 109 #define AR9887_DEVICE_ID (0x0050) 110 #define AR900B_DEVICE_ID (0x0040) 111 #define QCA9984_DEVICE_ID (0x0046) 112 #define QCA9888_DEVICE_ID (0x0056) 113 #define QCA8074_DEVICE_ID (0xffff) /* Todo: replace this with 114 actual number once available. 115 currently defining this to 0xffff for 116 emulation purpose */ 117 #define QCA8074V2_DEVICE_ID (0xfffe) /* Todo: replace this with actual number */ 118 #define QCA6018_DEVICE_ID (0xfffd) /* Todo: replace this with actual number */ 119 #define QCA5018_DEVICE_ID (0xfffc) /* Todo: replace this with actual number */ 120 #define QCA9574_DEVICE_ID (0xfffa) 121 /* Genoa */ 122 #define QCN7605_DEVICE_ID (0x1102) /* Genoa PCIe device ID*/ 123 #define QCN7605_COMPOSITE (0x9901) 124 #define QCN7605_STANDALONE (0x9900) 125 #define QCN7605_STANDALONE_V2 (0x9902) 126 #define QCN7605_COMPOSITE_V2 (0x9903) 127 128 #define RUMIM2M_DEVICE_ID_NODE0 0xabc0 129 #define RUMIM2M_DEVICE_ID_NODE1 0xabc1 130 #define RUMIM2M_DEVICE_ID_NODE2 0xabc2 131 #define RUMIM2M_DEVICE_ID_NODE3 0xabc3 132 #define RUMIM2M_DEVICE_ID_NODE4 0xaa10 133 #define RUMIM2M_DEVICE_ID_NODE5 0xaa11 134 135 #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn) 136 #define HIF_GET_IPCI_SOFTC(scn) ((struct hif_ipci_softc *)scn) 137 #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn) 138 #define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn) 139 #define HIF_GET_USB_SOFTC(scn) ((struct hif_usb_softc *)scn) 140 #define HIF_GET_USB_DEVICE(scn) ((struct HIF_DEVICE_USB *)scn) 141 #define HIF_GET_SOFTC(scn) ((struct hif_softc *)scn) 142 #define GET_HIF_OPAQUE_HDL(scn) ((struct hif_opaque_softc *)scn) 143 144 #ifdef QCA_WIFI_QCN9224 145 #define NUM_CE_AVAILABLE 16 146 #else 147 #define NUM_CE_AVAILABLE 12 148 #endif 149 /* Add 1 here to store default configuration in index 0 */ 150 #define NUM_CE_CONTEXT (NUM_CE_AVAILABLE + 1) 151 152 #define CE_INTERRUPT_IDX(x) x 153 154 struct ce_int_assignment { 155 uint8_t msi_idx[NUM_CE_AVAILABLE]; 156 }; 157 158 struct hif_ce_stats { 159 int hif_pipe_no_resrc_count; 160 int ce_ring_delta_fail_count; 161 }; 162 163 #ifdef HIF_DETECTION_LATENCY_ENABLE 164 struct hif_latency_detect { 165 qdf_timer_t detect_latency_timer; 166 uint32_t detect_latency_timer_timeout; 167 bool is_timer_started; 168 bool enable_detection; 169 /* threshold when stall happens */ 170 uint32_t detect_latency_threshold; 171 int ce2_tasklet_sched_cpuid; 172 qdf_time_t ce2_tasklet_sched_time; 173 qdf_time_t ce2_tasklet_exec_time; 174 qdf_time_t credit_request_time; 175 qdf_time_t credit_report_time; 176 }; 177 #endif 178 179 /* 180 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 181 * for defined here 182 */ 183 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 184 struct ce_desc_hist { 185 qdf_atomic_t history_index[CE_COUNT_MAX]; 186 bool enable[CE_COUNT_MAX]; 187 bool data_enable[CE_COUNT_MAX]; 188 qdf_mutex_t ce_dbg_datamem_lock[CE_COUNT_MAX]; 189 uint32_t hist_index; 190 uint32_t hist_id; 191 void *hist_ev[CE_COUNT_MAX]; 192 }; 193 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 194 195 /** 196 * struct hif_cfg() - store ini config parameters in hif layer 197 * @ce_status_ring_timer_threshold: ce status ring timer threshold 198 * @ce_status_ring_batch_count_threshold: ce status ring batch count threshold 199 */ 200 struct hif_cfg { 201 uint16_t ce_status_ring_timer_threshold; 202 uint8_t ce_status_ring_batch_count_threshold; 203 }; 204 205 struct hif_softc { 206 struct hif_opaque_softc osc; 207 struct hif_config_info hif_config; 208 struct hif_target_info target_info; 209 void __iomem *mem; 210 void __iomem *mem_ce; 211 enum qdf_bus_type bus_type; 212 struct hif_bus_ops bus_ops; 213 void *ce_id_to_state[CE_COUNT_MAX]; 214 qdf_device_t qdf_dev; 215 bool hif_init_done; 216 bool request_irq_done; 217 bool ext_grp_irq_configured; 218 bool free_irq_done; 219 uint8_t ce_latency_stats; 220 /* Packet statistics */ 221 struct hif_ce_stats pkt_stats; 222 enum hif_target_status target_status; 223 uint64_t event_enable_mask; 224 225 struct targetdef_s *targetdef; 226 struct ce_reg_def *target_ce_def; 227 struct hostdef_s *hostdef; 228 struct host_shadow_regs_s *host_shadow_regs; 229 230 bool recovery; 231 bool notice_send; 232 bool per_ce_irq; 233 uint32_t ce_irq_summary; 234 /* No of copy engines supported */ 235 unsigned int ce_count; 236 struct ce_int_assignment *int_assignment; 237 atomic_t active_tasklet_cnt; 238 atomic_t active_grp_tasklet_cnt; 239 atomic_t link_suspended; 240 uint32_t *vaddr_rri_on_ddr; 241 qdf_dma_addr_t paddr_rri_on_ddr; 242 #ifdef CONFIG_BYPASS_QMI 243 uint32_t *vaddr_qmi_bypass; 244 qdf_dma_addr_t paddr_qmi_bypass; 245 #endif 246 int linkstate_vote; 247 bool fastpath_mode_on; 248 atomic_t tasklet_from_intr; 249 int htc_htt_tx_endpoint; 250 qdf_dma_addr_t mem_pa; 251 bool athdiag_procfs_inited; 252 #ifdef FEATURE_NAPI 253 struct qca_napi_data napi_data; 254 #endif /* FEATURE_NAPI */ 255 /* stores ce_service_max_yield_time in ns */ 256 unsigned long long ce_service_max_yield_time; 257 uint8_t ce_service_max_rx_ind_flush; 258 struct hif_driver_state_callbacks callbacks; 259 uint32_t hif_con_param; 260 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 261 uint32_t nss_wifi_ol_mode; 262 #endif 263 void *hal_soc; 264 struct hif_ut_suspend_context ut_suspend_ctx; 265 uint32_t hif_attribute; 266 int wake_irq; 267 int disable_wake_irq; 268 hif_pm_wake_irq_type wake_irq_type; 269 void (*initial_wakeup_cb)(void *); 270 void *initial_wakeup_priv; 271 #ifdef REMOVE_PKT_LOG 272 /* Handle to pktlog device */ 273 void *pktlog_dev; 274 #endif 275 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 276 /* Pointer to the srng event history */ 277 struct hif_event_history *evt_hist[HIF_NUM_INT_CONTEXTS]; 278 #endif 279 280 /* 281 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 282 * for defined here 283 */ 284 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 285 struct ce_desc_hist hif_ce_desc_hist; 286 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 287 #ifdef IPA_OFFLOAD 288 qdf_shared_mem_t *ipa_ce_ring; 289 #endif 290 struct hif_cfg ini_cfg; 291 #ifdef HIF_CE_LOG_INFO 292 qdf_notif_block hif_recovery_notifier; 293 #endif 294 #ifdef HIF_CPU_PERF_AFFINE_MASK 295 /* The CPU hotplug event registration handle */ 296 struct qdf_cpuhp_handler *cpuhp_event_handle; 297 #endif 298 uint32_t irq_unlazy_disable; 299 /* Should the unlzay support for interrupt delivery be disabled */ 300 /* Flag to indicate whether bus is suspended */ 301 bool bus_suspended; 302 bool pktlog_init; 303 #ifdef FEATURE_RUNTIME_PM 304 /* Variable to track the link state change in RTPM */ 305 qdf_atomic_t pm_link_state; 306 #endif 307 #ifdef HIF_DETECTION_LATENCY_ENABLE 308 struct hif_latency_detect latency_detect; 309 #endif 310 #ifdef SYSTEM_PM_CHECK 311 qdf_atomic_t sys_pm_state; 312 #endif 313 #if defined(HIF_IPCI) && defined(FEATURE_HAL_DELAYED_REG_WRITE) 314 qdf_atomic_t dp_ep_vote_access; 315 qdf_atomic_t ep_vote_access; 316 #endif 317 /* CMEM address target reserved for host usage */ 318 uint64_t cmem_start; 319 /* CMEM size target reserved */ 320 uint64_t cmem_size; 321 }; 322 323 static inline 324 void *hif_get_hal_handle(struct hif_opaque_softc *hif_hdl) 325 { 326 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 327 328 if (!sc) 329 return NULL; 330 331 return sc->hal_soc; 332 } 333 334 /** 335 * hif_get_cmem_info() - get CMEM address and size from HIF handle 336 * @hif_hdl: HIF handle pointer 337 * @cmem_start: pointer for CMEM address 338 * @cmem_size: pointer for CMEM size 339 * 340 * Return: None. 341 */ 342 static inline 343 void hif_get_cmem_info(struct hif_opaque_softc *hif_hdl, 344 uint64_t *cmem_start, 345 uint64_t *cmem_size) 346 { 347 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 348 349 *cmem_start = sc->cmem_start; 350 *cmem_size = sc->cmem_size; 351 } 352 353 /** 354 * hif_get_num_active_tasklets() - get the number of active 355 * tasklets pending to be completed. 356 * @scn: HIF context 357 * 358 * Returns: the number of tasklets which are active 359 */ 360 static inline int hif_get_num_active_tasklets(struct hif_softc *scn) 361 { 362 return qdf_atomic_read(&scn->active_tasklet_cnt); 363 } 364 365 /** 366 * Max waiting time during Runtime PM suspend to finish all 367 * the tasks. This is in the multiple of 10ms. 368 */ 369 #define HIF_TASK_DRAIN_WAIT_CNT 25 370 371 /** 372 * hif_try_complete_tasks() - Try to complete all the pending tasks 373 * @scn: HIF context 374 * 375 * Try to complete all the pending datapath tasks, i.e. tasklets, 376 * DP group tasklets and works which are queued, in a given time 377 * slot. 378 * 379 * Returns: QDF_STATUS_SUCCESS if all the tasks were completed 380 * QDF error code, if the time slot exhausted 381 */ 382 QDF_STATUS hif_try_complete_tasks(struct hif_softc *scn); 383 384 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 385 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 386 { 387 return !!(sc->nss_wifi_ol_mode); 388 } 389 #else 390 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 391 { 392 return false; 393 } 394 #endif 395 396 static inline uint8_t hif_is_attribute_set(struct hif_softc *sc, 397 uint32_t hif_attrib) 398 { 399 return sc->hif_attribute == hif_attrib; 400 } 401 402 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 403 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 404 { 405 struct hif_softc *scn = (struct hif_softc *)hif_handle; 406 407 scn->event_enable_mask = HIF_EVENT_HIST_ENABLE_MASK; 408 } 409 #else 410 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 411 { 412 } 413 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 414 415 A_target_id_t hif_get_target_id(struct hif_softc *scn); 416 void hif_dump_pipe_debug_count(struct hif_softc *scn); 417 void hif_display_bus_stats(struct hif_opaque_softc *scn); 418 void hif_clear_bus_stats(struct hif_opaque_softc *scn); 419 bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count); 420 void hif_shutdown_device(struct hif_opaque_softc *hif_ctx); 421 int hif_bus_configure(struct hif_softc *scn); 422 void hif_cancel_deferred_target_sleep(struct hif_softc *scn); 423 int hif_config_ce(struct hif_softc *scn); 424 int hif_config_ce_pktlog(struct hif_opaque_softc *hif_ctx); 425 int hif_config_ce_by_id(struct hif_softc *scn, int pipe_num); 426 void hif_unconfig_ce(struct hif_softc *scn); 427 void hif_ce_prepare_config(struct hif_softc *scn); 428 QDF_STATUS hif_ce_open(struct hif_softc *scn); 429 void hif_ce_close(struct hif_softc *scn); 430 int athdiag_procfs_init(void *scn); 431 void athdiag_procfs_remove(void); 432 /* routine to modify the initial buffer count to be allocated on an os 433 * platform basis. Platform owner will need to modify this as needed 434 */ 435 qdf_size_t init_buffer_count(qdf_size_t maxSize); 436 437 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg); 438 int hif_get_device_type(uint32_t device_id, 439 uint32_t revision_id, 440 uint32_t *hif_type, uint32_t *target_type); 441 /*These functions are exposed to HDD*/ 442 void hif_nointrs(struct hif_softc *scn); 443 void hif_bus_close(struct hif_softc *ol_sc); 444 QDF_STATUS hif_bus_open(struct hif_softc *ol_sc, 445 enum qdf_bus_type bus_type); 446 QDF_STATUS hif_enable_bus(struct hif_softc *ol_sc, struct device *dev, 447 void *bdev, const struct hif_bus_id *bid, enum hif_enable_type type); 448 void hif_disable_bus(struct hif_softc *scn); 449 #ifdef FEATURE_RUNTIME_PM 450 struct hif_runtime_pm_ctx *hif_bus_get_rpm_ctx(struct hif_softc *hif_sc); 451 struct device *hif_bus_get_dev(struct hif_softc *hif_sc); 452 #endif 453 void hif_bus_prevent_linkdown(struct hif_softc *scn, bool flag); 454 int hif_bus_get_context_size(enum qdf_bus_type bus_type); 455 void hif_read_phy_mem_base(struct hif_softc *scn, qdf_dma_addr_t *bar_value); 456 uint32_t hif_get_conparam(struct hif_softc *scn); 457 struct hif_driver_state_callbacks *hif_get_callbacks_handle( 458 struct hif_softc *scn); 459 bool hif_is_driver_unloading(struct hif_softc *scn); 460 bool hif_is_load_or_unload_in_progress(struct hif_softc *scn); 461 bool hif_is_recovery_in_progress(struct hif_softc *scn); 462 bool hif_is_target_ready(struct hif_softc *scn); 463 464 /** 465 * hif_get_bandwidth_level() - API to get the current bandwidth level 466 * @scn: HIF Context 467 * 468 * Return: PLD bandwidth level 469 */ 470 int hif_get_bandwidth_level(struct hif_opaque_softc *hif_handle); 471 472 void hif_wlan_disable(struct hif_softc *scn); 473 int hif_target_sleep_state_adjust(struct hif_softc *scn, 474 bool sleep_ok, 475 bool wait_for_it); 476 477 #ifdef DP_MEM_PRE_ALLOC 478 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 479 qdf_size_t size, 480 qdf_dma_addr_t *paddr, 481 uint32_t ring_type, 482 uint8_t *is_mem_prealloc); 483 484 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 485 qdf_size_t size, 486 void *vaddr, 487 qdf_dma_addr_t paddr, 488 qdf_dma_context_t memctx, 489 uint8_t is_mem_prealloc); 490 #else 491 static inline 492 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 493 qdf_size_t size, 494 qdf_dma_addr_t *paddr, 495 uint32_t ring_type, 496 uint8_t *is_mem_prealloc) 497 { 498 return qdf_mem_alloc_consistent(scn->qdf_dev, 499 scn->qdf_dev->dev, 500 size, 501 paddr); 502 } 503 504 static inline 505 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 506 qdf_size_t size, 507 void *vaddr, 508 qdf_dma_addr_t paddr, 509 qdf_dma_context_t memctx, 510 uint8_t is_mem_prealloc) 511 { 512 return qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 513 size, vaddr, paddr, memctx); 514 } 515 #endif 516 517 /** 518 * hif_get_rx_ctx_id() - Returns NAPI instance ID based on CE ID 519 * @ctx_id: Rx CE context ID 520 * @hif_hdl: HIF Context 521 * 522 * Return: Rx instance ID 523 */ 524 int hif_get_rx_ctx_id(int ctx_id, struct hif_opaque_softc *hif_hdl); 525 void hif_ramdump_handler(struct hif_opaque_softc *scn); 526 #ifdef HIF_USB 527 void hif_usb_get_hw_info(struct hif_softc *scn); 528 void hif_usb_ramdump_handler(struct hif_opaque_softc *scn); 529 #else 530 static inline void hif_usb_get_hw_info(struct hif_softc *scn) {} 531 static inline void hif_usb_ramdump_handler(struct hif_opaque_softc *scn) {} 532 #endif 533 534 /** 535 * hif_wake_interrupt_handler() - interrupt handler for standalone wake irq 536 * @irq: the irq number that fired 537 * @context: the opaque pointer passed to request_irq() 538 * 539 * Return: an irq return type 540 */ 541 irqreturn_t hif_wake_interrupt_handler(int irq, void *context); 542 543 #ifdef HIF_SNOC 544 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc); 545 #else 546 static inline 547 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc) 548 { 549 return true; 550 } 551 #endif 552 553 #ifdef ADRASTEA_RRI_ON_DDR 554 void hif_uninit_rri_on_ddr(struct hif_softc *scn); 555 #else 556 static inline 557 void hif_uninit_rri_on_ddr(struct hif_softc *scn) {} 558 #endif 559 void hif_cleanup_static_buf_to_target(struct hif_softc *scn); 560 #endif /* __HIF_MAIN_H__ */ 561