1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * NB: Inappropriate references to "HTC" are used in this (and other) 22 * HIF implementations. HTC is typically the calling layer, but it 23 * theoretically could be some alternative. 24 */ 25 26 /* 27 * This holds all state needed to process a pending send/recv interrupt. 28 * The information is saved here as soon as the interrupt occurs (thus 29 * allowing the underlying CE to re-use the ring descriptor). The 30 * information here is eventually processed by a completion processing 31 * thread. 32 */ 33 34 #ifndef __HIF_MAIN_H__ 35 #define __HIF_MAIN_H__ 36 37 #include <qdf_atomic.h> /* qdf_atomic_read */ 38 #include "qdf_lock.h" 39 #include "cepci.h" 40 #include "hif.h" 41 #include "multibus.h" 42 #include "hif_unit_test_suspend_i.h" 43 #ifdef HIF_CE_LOG_INFO 44 #include "qdf_notifier.h" 45 #endif 46 47 #define HIF_MIN_SLEEP_INACTIVITY_TIME_MS 50 48 #define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60 49 50 #define HIF_MAX_BUDGET 0xFFFF 51 52 #define HIF_STATS_INC(_handle, _field, _delta) \ 53 { \ 54 (_handle)->stats._field += _delta; \ 55 } 56 57 /* 58 * This macro implementation is exposed for efficiency only. 59 * The implementation may change and callers should 60 * consider the targid to be a completely opaque handle. 61 */ 62 #define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid))) 63 64 #ifdef QCA_WIFI_3_0 65 #define DISABLE_L1SS_STATES 1 66 #endif 67 68 #define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES 69 70 #ifdef QCA_WIFI_3_0_ADRASTEA 71 #define ADRASTEA_BU 1 72 #else 73 #define ADRASTEA_BU 0 74 #endif 75 76 #ifdef QCA_WIFI_3_0 77 #define HAS_FW_INDICATOR 0 78 #else 79 #define HAS_FW_INDICATOR 1 80 #endif 81 82 83 #define AR9888_DEVICE_ID (0x003c) 84 #define AR6320_DEVICE_ID (0x003e) 85 #define AR6320_FW_1_1 (0x11) 86 #define AR6320_FW_1_3 (0x13) 87 #define AR6320_FW_2_0 (0x20) 88 #define AR6320_FW_3_0 (0x30) 89 #define AR6320_FW_3_2 (0x32) 90 #define QCA6290_EMULATION_DEVICE_ID (0xabcd) 91 #define QCA6290_DEVICE_ID (0x1100) 92 #define QCN9000_DEVICE_ID (0x1104) 93 #define QCN9224_DEVICE_ID (0x1109) 94 #define QCN6122_DEVICE_ID (0xFFFB) 95 #define QCA6390_EMULATION_DEVICE_ID (0x0108) 96 #define QCA6390_DEVICE_ID (0x1101) 97 /* TODO: change IDs for HastingsPrime */ 98 #define QCA6490_EMULATION_DEVICE_ID (0x010a) 99 #define QCA6490_DEVICE_ID (0x1103) 100 #define MANGO_DEVICE_ID (0x110a) 101 102 /* TODO: change IDs for Moselle */ 103 #define QCA6750_EMULATION_DEVICE_ID (0x010c) 104 #define QCA6750_DEVICE_ID (0x1105) 105 106 /* TODO: change IDs for Hamilton */ 107 #define KIWI_DEVICE_ID (0x1107) 108 109 #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021) 110 #define AR9887_DEVICE_ID (0x0050) 111 #define AR900B_DEVICE_ID (0x0040) 112 #define QCA9984_DEVICE_ID (0x0046) 113 #define QCA9888_DEVICE_ID (0x0056) 114 #define QCA8074_DEVICE_ID (0xffff) /* Todo: replace this with 115 actual number once available. 116 currently defining this to 0xffff for 117 emulation purpose */ 118 #define QCA8074V2_DEVICE_ID (0xfffe) /* Todo: replace this with actual number */ 119 #define QCA6018_DEVICE_ID (0xfffd) /* Todo: replace this with actual number */ 120 #define QCA5018_DEVICE_ID (0xfffc) /* Todo: replace this with actual number */ 121 #define QCA9574_DEVICE_ID (0xfffa) 122 /* Genoa */ 123 #define QCN7605_DEVICE_ID (0x1102) /* Genoa PCIe device ID*/ 124 #define QCN7605_COMPOSITE (0x9901) 125 #define QCN7605_STANDALONE (0x9900) 126 #define QCN7605_STANDALONE_V2 (0x9902) 127 #define QCN7605_COMPOSITE_V2 (0x9903) 128 129 #define RUMIM2M_DEVICE_ID_NODE0 0xabc0 130 #define RUMIM2M_DEVICE_ID_NODE1 0xabc1 131 #define RUMIM2M_DEVICE_ID_NODE2 0xabc2 132 #define RUMIM2M_DEVICE_ID_NODE3 0xabc3 133 #define RUMIM2M_DEVICE_ID_NODE4 0xaa10 134 #define RUMIM2M_DEVICE_ID_NODE5 0xaa11 135 136 #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn) 137 #define HIF_GET_IPCI_SOFTC(scn) ((struct hif_ipci_softc *)scn) 138 #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn) 139 #define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn) 140 #define HIF_GET_USB_SOFTC(scn) ((struct hif_usb_softc *)scn) 141 #define HIF_GET_USB_DEVICE(scn) ((struct HIF_DEVICE_USB *)scn) 142 #define HIF_GET_SOFTC(scn) ((struct hif_softc *)scn) 143 #define GET_HIF_OPAQUE_HDL(scn) ((struct hif_opaque_softc *)scn) 144 145 #ifdef QCA_WIFI_QCN9224 146 #define NUM_CE_AVAILABLE 16 147 #else 148 #define NUM_CE_AVAILABLE 12 149 #endif 150 /* Add 1 here to store default configuration in index 0 */ 151 #define NUM_CE_CONTEXT (NUM_CE_AVAILABLE + 1) 152 153 #define CE_INTERRUPT_IDX(x) x 154 155 struct ce_int_assignment { 156 uint8_t msi_idx[NUM_CE_AVAILABLE]; 157 }; 158 159 struct hif_ce_stats { 160 int hif_pipe_no_resrc_count; 161 int ce_ring_delta_fail_count; 162 }; 163 164 #ifdef HIF_DETECTION_LATENCY_ENABLE 165 struct hif_latency_detect { 166 qdf_timer_t detect_latency_timer; 167 uint32_t detect_latency_timer_timeout; 168 bool is_timer_started; 169 bool enable_detection; 170 /* threshold when stall happens */ 171 uint32_t detect_latency_threshold; 172 int ce2_tasklet_sched_cpuid; 173 qdf_time_t ce2_tasklet_sched_time; 174 qdf_time_t ce2_tasklet_exec_time; 175 qdf_time_t credit_request_time; 176 qdf_time_t credit_report_time; 177 }; 178 #endif 179 180 /* 181 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 182 * for defined here 183 */ 184 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 185 186 #define HIF_CE_MAX_LATEST_HIST 2 187 188 struct latest_evt_history { 189 uint64_t irq_entry_ts; 190 uint64_t bh_entry_ts; 191 uint64_t bh_resched_ts; 192 uint64_t bh_exit_ts; 193 uint64_t bh_work_ts; 194 int cpu_id; 195 uint32_t ring_hp; 196 uint32_t ring_tp; 197 }; 198 199 struct ce_desc_hist { 200 qdf_atomic_t history_index[CE_COUNT_MAX]; 201 uint8_t ce_id_hist_map[CE_COUNT_MAX]; 202 bool enable[CE_COUNT_MAX]; 203 bool data_enable[CE_COUNT_MAX]; 204 qdf_mutex_t ce_dbg_datamem_lock[CE_COUNT_MAX]; 205 uint32_t hist_index; 206 uint32_t hist_id; 207 void *hist_ev[CE_COUNT_MAX]; 208 struct latest_evt_history latest_evt[HIF_CE_MAX_LATEST_HIST]; 209 }; 210 211 void hif_record_latest_evt(struct ce_desc_hist *ce_hist, 212 uint8_t type, 213 int ce_id, uint64_t time, 214 uint32_t hp, uint32_t tp); 215 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 216 217 /** 218 * struct hif_cfg() - store ini config parameters in hif layer 219 * @ce_status_ring_timer_threshold: ce status ring timer threshold 220 * @ce_status_ring_batch_count_threshold: ce status ring batch count threshold 221 */ 222 struct hif_cfg { 223 uint16_t ce_status_ring_timer_threshold; 224 uint8_t ce_status_ring_batch_count_threshold; 225 }; 226 227 #ifdef DP_UMAC_HW_RESET_SUPPORT 228 /** 229 * struct hif_umac_reset_ctx - UMAC HW reset context at HIF layer 230 * @intr_tq: Tasklet structure 231 * @cb_handler: Callback handler 232 * @cb_ctx: Argument to be passed to @cb_handler 233 * @os_irq: Interrupt number for this IRQ 234 * @irq_configured: Whether the IRQ has been configured 235 */ 236 struct hif_umac_reset_ctx { 237 struct tasklet_struct intr_tq; 238 int (*cb_handler)(void *cb_ctx); 239 void *cb_ctx; 240 uint32_t os_irq; 241 bool irq_configured; 242 }; 243 #endif 244 245 struct hif_softc { 246 struct hif_opaque_softc osc; 247 struct hif_config_info hif_config; 248 struct hif_target_info target_info; 249 void __iomem *mem; 250 void __iomem *mem_ce; 251 enum qdf_bus_type bus_type; 252 struct hif_bus_ops bus_ops; 253 void *ce_id_to_state[CE_COUNT_MAX]; 254 qdf_device_t qdf_dev; 255 bool hif_init_done; 256 bool request_irq_done; 257 bool ext_grp_irq_configured; 258 bool free_irq_done; 259 uint8_t ce_latency_stats; 260 /* Packet statistics */ 261 struct hif_ce_stats pkt_stats; 262 enum hif_target_status target_status; 263 uint64_t event_enable_mask; 264 265 struct targetdef_s *targetdef; 266 struct ce_reg_def *target_ce_def; 267 struct hostdef_s *hostdef; 268 struct host_shadow_regs_s *host_shadow_regs; 269 270 bool recovery; 271 bool notice_send; 272 bool per_ce_irq; 273 uint32_t ce_irq_summary; 274 /* No of copy engines supported */ 275 unsigned int ce_count; 276 struct ce_int_assignment *int_assignment; 277 atomic_t active_tasklet_cnt; 278 atomic_t active_grp_tasklet_cnt; 279 atomic_t link_suspended; 280 uint32_t *vaddr_rri_on_ddr; 281 qdf_dma_addr_t paddr_rri_on_ddr; 282 #ifdef CONFIG_BYPASS_QMI 283 uint32_t *vaddr_qmi_bypass; 284 qdf_dma_addr_t paddr_qmi_bypass; 285 #endif 286 int linkstate_vote; 287 bool fastpath_mode_on; 288 atomic_t tasklet_from_intr; 289 int htc_htt_tx_endpoint; 290 qdf_dma_addr_t mem_pa; 291 bool athdiag_procfs_inited; 292 #ifdef FEATURE_NAPI 293 struct qca_napi_data napi_data; 294 #endif /* FEATURE_NAPI */ 295 /* stores ce_service_max_yield_time in ns */ 296 unsigned long long ce_service_max_yield_time; 297 uint8_t ce_service_max_rx_ind_flush; 298 struct hif_driver_state_callbacks callbacks; 299 uint32_t hif_con_param; 300 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 301 uint32_t nss_wifi_ol_mode; 302 #endif 303 void *hal_soc; 304 struct hif_ut_suspend_context ut_suspend_ctx; 305 uint32_t hif_attribute; 306 int wake_irq; 307 int disable_wake_irq; 308 hif_pm_wake_irq_type wake_irq_type; 309 void (*initial_wakeup_cb)(void *); 310 void *initial_wakeup_priv; 311 #ifdef REMOVE_PKT_LOG 312 /* Handle to pktlog device */ 313 void *pktlog_dev; 314 #endif 315 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 316 /* Pointer to the srng event history */ 317 struct hif_event_history *evt_hist[HIF_NUM_INT_CONTEXTS]; 318 #endif 319 320 /* 321 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 322 * for defined here 323 */ 324 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 325 struct ce_desc_hist hif_ce_desc_hist; 326 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 327 #ifdef IPA_OFFLOAD 328 qdf_shared_mem_t *ipa_ce_ring; 329 #endif 330 struct hif_cfg ini_cfg; 331 #ifdef HIF_CE_LOG_INFO 332 qdf_notif_block hif_recovery_notifier; 333 #endif 334 #ifdef HIF_CPU_PERF_AFFINE_MASK 335 /* The CPU hotplug event registration handle */ 336 struct qdf_cpuhp_handler *cpuhp_event_handle; 337 #endif 338 uint32_t irq_unlazy_disable; 339 /* Should the unlzay support for interrupt delivery be disabled */ 340 /* Flag to indicate whether bus is suspended */ 341 bool bus_suspended; 342 bool pktlog_init; 343 #ifdef FEATURE_RUNTIME_PM 344 /* Variable to track the link state change in RTPM */ 345 qdf_atomic_t pm_link_state; 346 #endif 347 #ifdef HIF_DETECTION_LATENCY_ENABLE 348 struct hif_latency_detect latency_detect; 349 #endif 350 #ifdef FEATURE_RUNTIME_PM 351 qdf_runtime_lock_t prevent_linkdown_lock; 352 #endif 353 #ifdef SYSTEM_PM_CHECK 354 qdf_atomic_t sys_pm_state; 355 #endif 356 #if defined(HIF_IPCI) && defined(FEATURE_HAL_DELAYED_REG_WRITE) 357 qdf_atomic_t dp_ep_vote_access; 358 qdf_atomic_t ep_vote_access; 359 #endif 360 /* CMEM address target reserved for host usage */ 361 uint64_t cmem_start; 362 /* CMEM size target reserved */ 363 uint64_t cmem_size; 364 #ifdef DP_UMAC_HW_RESET_SUPPORT 365 struct hif_umac_reset_ctx umac_reset_ctx; 366 #endif 367 }; 368 369 static inline 370 void *hif_get_hal_handle(struct hif_opaque_softc *hif_hdl) 371 { 372 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 373 374 if (!sc) 375 return NULL; 376 377 return sc->hal_soc; 378 } 379 380 /** 381 * hif_get_cmem_info() - get CMEM address and size from HIF handle 382 * @hif_hdl: HIF handle pointer 383 * @cmem_start: pointer for CMEM address 384 * @cmem_size: pointer for CMEM size 385 * 386 * Return: None. 387 */ 388 static inline 389 void hif_get_cmem_info(struct hif_opaque_softc *hif_hdl, 390 uint64_t *cmem_start, 391 uint64_t *cmem_size) 392 { 393 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 394 395 *cmem_start = sc->cmem_start; 396 *cmem_size = sc->cmem_size; 397 } 398 399 /** 400 * hif_get_num_active_tasklets() - get the number of active 401 * tasklets pending to be completed. 402 * @scn: HIF context 403 * 404 * Returns: the number of tasklets which are active 405 */ 406 static inline int hif_get_num_active_tasklets(struct hif_softc *scn) 407 { 408 return qdf_atomic_read(&scn->active_tasklet_cnt); 409 } 410 411 /** 412 * Max waiting time during Runtime PM suspend to finish all 413 * the tasks. This is in the multiple of 10ms. 414 */ 415 #define HIF_TASK_DRAIN_WAIT_CNT 25 416 417 /** 418 * hif_try_complete_tasks() - Try to complete all the pending tasks 419 * @scn: HIF context 420 * 421 * Try to complete all the pending datapath tasks, i.e. tasklets, 422 * DP group tasklets and works which are queued, in a given time 423 * slot. 424 * 425 * Returns: QDF_STATUS_SUCCESS if all the tasks were completed 426 * QDF error code, if the time slot exhausted 427 */ 428 QDF_STATUS hif_try_complete_tasks(struct hif_softc *scn); 429 430 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 431 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 432 { 433 return !!(sc->nss_wifi_ol_mode); 434 } 435 #else 436 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 437 { 438 return false; 439 } 440 #endif 441 442 static inline uint8_t hif_is_attribute_set(struct hif_softc *sc, 443 uint32_t hif_attrib) 444 { 445 return sc->hif_attribute == hif_attrib; 446 } 447 448 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 449 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 450 { 451 struct hif_softc *scn = (struct hif_softc *)hif_handle; 452 453 scn->event_enable_mask = HIF_EVENT_HIST_ENABLE_MASK; 454 } 455 #else 456 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 457 { 458 } 459 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 460 461 A_target_id_t hif_get_target_id(struct hif_softc *scn); 462 void hif_dump_pipe_debug_count(struct hif_softc *scn); 463 void hif_display_bus_stats(struct hif_opaque_softc *scn); 464 void hif_clear_bus_stats(struct hif_opaque_softc *scn); 465 bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count); 466 void hif_shutdown_device(struct hif_opaque_softc *hif_ctx); 467 int hif_bus_configure(struct hif_softc *scn); 468 void hif_cancel_deferred_target_sleep(struct hif_softc *scn); 469 int hif_config_ce(struct hif_softc *scn); 470 int hif_config_ce_pktlog(struct hif_opaque_softc *hif_ctx); 471 int hif_config_ce_by_id(struct hif_softc *scn, int pipe_num); 472 void hif_unconfig_ce(struct hif_softc *scn); 473 void hif_ce_prepare_config(struct hif_softc *scn); 474 QDF_STATUS hif_ce_open(struct hif_softc *scn); 475 void hif_ce_close(struct hif_softc *scn); 476 int athdiag_procfs_init(void *scn); 477 void athdiag_procfs_remove(void); 478 /* routine to modify the initial buffer count to be allocated on an os 479 * platform basis. Platform owner will need to modify this as needed 480 */ 481 qdf_size_t init_buffer_count(qdf_size_t maxSize); 482 483 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg); 484 int hif_get_device_type(uint32_t device_id, 485 uint32_t revision_id, 486 uint32_t *hif_type, uint32_t *target_type); 487 /*These functions are exposed to HDD*/ 488 void hif_nointrs(struct hif_softc *scn); 489 void hif_bus_close(struct hif_softc *ol_sc); 490 QDF_STATUS hif_bus_open(struct hif_softc *ol_sc, 491 enum qdf_bus_type bus_type); 492 QDF_STATUS hif_enable_bus(struct hif_softc *ol_sc, struct device *dev, 493 void *bdev, const struct hif_bus_id *bid, enum hif_enable_type type); 494 void hif_disable_bus(struct hif_softc *scn); 495 void hif_bus_prevent_linkdown(struct hif_softc *scn, bool flag); 496 int hif_bus_get_context_size(enum qdf_bus_type bus_type); 497 void hif_read_phy_mem_base(struct hif_softc *scn, qdf_dma_addr_t *bar_value); 498 uint32_t hif_get_conparam(struct hif_softc *scn); 499 struct hif_driver_state_callbacks *hif_get_callbacks_handle( 500 struct hif_softc *scn); 501 bool hif_is_driver_unloading(struct hif_softc *scn); 502 bool hif_is_load_or_unload_in_progress(struct hif_softc *scn); 503 bool hif_is_recovery_in_progress(struct hif_softc *scn); 504 bool hif_is_target_ready(struct hif_softc *scn); 505 506 /** 507 * hif_get_bandwidth_level() - API to get the current bandwidth level 508 * @scn: HIF Context 509 * 510 * Return: PLD bandwidth level 511 */ 512 int hif_get_bandwidth_level(struct hif_opaque_softc *hif_handle); 513 514 void hif_wlan_disable(struct hif_softc *scn); 515 int hif_target_sleep_state_adjust(struct hif_softc *scn, 516 bool sleep_ok, 517 bool wait_for_it); 518 519 #ifdef DP_MEM_PRE_ALLOC 520 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 521 qdf_size_t size, 522 qdf_dma_addr_t *paddr, 523 uint32_t ring_type, 524 uint8_t *is_mem_prealloc); 525 526 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 527 qdf_size_t size, 528 void *vaddr, 529 qdf_dma_addr_t paddr, 530 qdf_dma_context_t memctx, 531 uint8_t is_mem_prealloc); 532 #else 533 static inline 534 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 535 qdf_size_t size, 536 qdf_dma_addr_t *paddr, 537 uint32_t ring_type, 538 uint8_t *is_mem_prealloc) 539 { 540 return qdf_mem_alloc_consistent(scn->qdf_dev, 541 scn->qdf_dev->dev, 542 size, 543 paddr); 544 } 545 546 static inline 547 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 548 qdf_size_t size, 549 void *vaddr, 550 qdf_dma_addr_t paddr, 551 qdf_dma_context_t memctx, 552 uint8_t is_mem_prealloc) 553 { 554 return qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 555 size, vaddr, paddr, memctx); 556 } 557 #endif 558 559 /** 560 * hif_get_rx_ctx_id() - Returns NAPI instance ID based on CE ID 561 * @ctx_id: Rx CE context ID 562 * @hif_hdl: HIF Context 563 * 564 * Return: Rx instance ID 565 */ 566 int hif_get_rx_ctx_id(int ctx_id, struct hif_opaque_softc *hif_hdl); 567 void hif_ramdump_handler(struct hif_opaque_softc *scn); 568 #ifdef HIF_USB 569 void hif_usb_get_hw_info(struct hif_softc *scn); 570 void hif_usb_ramdump_handler(struct hif_opaque_softc *scn); 571 #else 572 static inline void hif_usb_get_hw_info(struct hif_softc *scn) {} 573 static inline void hif_usb_ramdump_handler(struct hif_opaque_softc *scn) {} 574 #endif 575 576 /** 577 * hif_wake_interrupt_handler() - interrupt handler for standalone wake irq 578 * @irq: the irq number that fired 579 * @context: the opaque pointer passed to request_irq() 580 * 581 * Return: an irq return type 582 */ 583 irqreturn_t hif_wake_interrupt_handler(int irq, void *context); 584 585 #ifdef HIF_SNOC 586 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc); 587 #else 588 static inline 589 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc) 590 { 591 return true; 592 } 593 #endif 594 595 #ifdef ADRASTEA_RRI_ON_DDR 596 void hif_uninit_rri_on_ddr(struct hif_softc *scn); 597 #else 598 static inline 599 void hif_uninit_rri_on_ddr(struct hif_softc *scn) {} 600 #endif 601 void hif_cleanup_static_buf_to_target(struct hif_softc *scn); 602 603 #ifdef FEATURE_RUNTIME_PM 604 /** 605 * hif_runtime_prevent_linkdown() - prevent or allow a runtime pm from occurring 606 * @scn: hif context 607 * @is_get: prevent linkdown if true otherwise allow 608 * 609 * this api should only be called as part of bus prevent linkdown 610 */ 611 void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get); 612 #else 613 static inline 614 void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get) 615 { 616 } 617 #endif 618 619 #endif /* __HIF_MAIN_H__ */ 620