1 /* 2 * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * NB: Inappropriate references to "HTC" are used in this (and other) 21 * HIF implementations. HTC is typically the calling layer, but it 22 * theoretically could be some alternative. 23 */ 24 25 /* 26 * This holds all state needed to process a pending send/recv interrupt. 27 * The information is saved here as soon as the interrupt occurs (thus 28 * allowing the underlying CE to re-use the ring descriptor). The 29 * information here is eventually processed by a completion processing 30 * thread. 31 */ 32 33 #ifndef __HIF_MAIN_H__ 34 #define __HIF_MAIN_H__ 35 36 #include <qdf_atomic.h> /* qdf_atomic_read */ 37 #include "qdf_lock.h" 38 #include "cepci.h" 39 #include "hif.h" 40 #include "multibus.h" 41 #include "hif_unit_test_suspend_i.h" 42 #ifdef HIF_CE_LOG_INFO 43 #include "qdf_notifier.h" 44 #endif 45 46 #define HIF_MIN_SLEEP_INACTIVITY_TIME_MS 50 47 #define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60 48 49 #define HIF_MAX_BUDGET 0xFFFF 50 51 #define HIF_STATS_INC(_handle, _field, _delta) \ 52 { \ 53 (_handle)->stats._field += _delta; \ 54 } 55 56 /* 57 * This macro implementation is exposed for efficiency only. 58 * The implementation may change and callers should 59 * consider the targid to be a completely opaque handle. 60 */ 61 #define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid))) 62 63 #ifdef QCA_WIFI_3_0 64 #define DISABLE_L1SS_STATES 1 65 #endif 66 67 #define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES 68 69 #ifdef QCA_WIFI_3_0_ADRASTEA 70 #define ADRASTEA_BU 1 71 #else 72 #define ADRASTEA_BU 0 73 #endif 74 75 #ifdef QCA_WIFI_3_0 76 #define HAS_FW_INDICATOR 0 77 #else 78 #define HAS_FW_INDICATOR 1 79 #endif 80 81 82 #define AR9888_DEVICE_ID (0x003c) 83 #define AR6320_DEVICE_ID (0x003e) 84 #define AR6320_FW_1_1 (0x11) 85 #define AR6320_FW_1_3 (0x13) 86 #define AR6320_FW_2_0 (0x20) 87 #define AR6320_FW_3_0 (0x30) 88 #define AR6320_FW_3_2 (0x32) 89 #define QCA6290_EMULATION_DEVICE_ID (0xabcd) 90 #define QCA6290_DEVICE_ID (0x1100) 91 #define QCN9000_DEVICE_ID (0x1104) 92 #define QCA6390_EMULATION_DEVICE_ID (0x0108) 93 #define QCA6390_DEVICE_ID (0x1101) 94 /* TODO: change IDs for HastingsPrime */ 95 #define QCA6490_EMULATION_DEVICE_ID (0x010a) 96 #define QCA6490_DEVICE_ID (0x1103) 97 98 /* TODO: change IDs for Moselle */ 99 #define QCA6750_EMULATION_DEVICE_ID (0x010c) 100 #define QCA6750_DEVICE_ID (0x1105) 101 102 #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021) 103 #define AR9887_DEVICE_ID (0x0050) 104 #define AR900B_DEVICE_ID (0x0040) 105 #define QCA9984_DEVICE_ID (0x0046) 106 #define QCA9888_DEVICE_ID (0x0056) 107 #ifndef IPQ4019_DEVICE_ID 108 #define IPQ4019_DEVICE_ID (0x12ef) 109 #endif 110 #define QCA8074_DEVICE_ID (0xffff) /* Todo: replace this with 111 actual number once available. 112 currently defining this to 0xffff for 113 emulation purpose */ 114 #define QCA8074V2_DEVICE_ID (0xfffe) /* Todo: replace this with actual number */ 115 #define QCA6018_DEVICE_ID (0xfffd) /* Todo: replace this with actual number */ 116 #define QCA5018_DEVICE_ID (0xfffc) /* Todo: replace this with actual number */ 117 /* Genoa */ 118 #define QCN7605_DEVICE_ID (0x1102) /* Genoa PCIe device ID*/ 119 #define QCN7605_COMPOSITE (0x9901) 120 #define QCN7605_STANDALONE (0x9900) 121 #define QCN7605_STANDALONE_V2 (0x9902) 122 #define QCN7605_COMPOSITE_V2 (0x9903) 123 124 #define RUMIM2M_DEVICE_ID_NODE0 0xabc0 125 #define RUMIM2M_DEVICE_ID_NODE1 0xabc1 126 #define RUMIM2M_DEVICE_ID_NODE2 0xabc2 127 #define RUMIM2M_DEVICE_ID_NODE3 0xabc3 128 #define RUMIM2M_DEVICE_ID_NODE4 0xaa10 129 #define RUMIM2M_DEVICE_ID_NODE5 0xaa11 130 131 #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn) 132 #define HIF_GET_IPCI_SOFTC(scn) ((struct hif_ipci_softc *)scn) 133 #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn) 134 #define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn) 135 #define HIF_GET_USB_SOFTC(scn) ((struct hif_usb_softc *)scn) 136 #define HIF_GET_USB_DEVICE(scn) ((struct HIF_DEVICE_USB *)scn) 137 #define HIF_GET_SOFTC(scn) ((struct hif_softc *)scn) 138 #define GET_HIF_OPAQUE_HDL(scn) ((struct hif_opaque_softc *)scn) 139 140 struct hif_ce_stats { 141 int hif_pipe_no_resrc_count; 142 int ce_ring_delta_fail_count; 143 }; 144 145 /* 146 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 147 * for defined here 148 */ 149 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 150 struct ce_desc_hist { 151 qdf_atomic_t history_index[CE_COUNT_MAX]; 152 uint32_t enable[CE_COUNT_MAX]; 153 bool data_enable[CE_COUNT_MAX]; 154 qdf_mutex_t ce_dbg_datamem_lock[CE_COUNT_MAX]; 155 uint32_t hist_index; 156 uint32_t hist_id; 157 void *hist_ev[CE_COUNT_MAX]; 158 }; 159 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 160 161 /** 162 * struct hif_cfg() - store ini config parameters in hif layer 163 * @ce_status_ring_timer_threshold: ce status ring timer threshold 164 * @ce_status_ring_batch_count_threshold: ce status ring batch count threshold 165 */ 166 struct hif_cfg { 167 uint16_t ce_status_ring_timer_threshold; 168 uint8_t ce_status_ring_batch_count_threshold; 169 }; 170 171 struct hif_softc { 172 struct hif_opaque_softc osc; 173 struct hif_config_info hif_config; 174 struct hif_target_info target_info; 175 void __iomem *mem; 176 void __iomem *mem_ce; 177 enum qdf_bus_type bus_type; 178 struct hif_bus_ops bus_ops; 179 void *ce_id_to_state[CE_COUNT_MAX]; 180 qdf_device_t qdf_dev; 181 bool hif_init_done; 182 bool request_irq_done; 183 bool ext_grp_irq_configured; 184 uint8_t ce_latency_stats; 185 /* Packet statistics */ 186 struct hif_ce_stats pkt_stats; 187 enum hif_target_status target_status; 188 uint64_t event_disable_mask; 189 190 struct targetdef_s *targetdef; 191 struct ce_reg_def *target_ce_def; 192 struct hostdef_s *hostdef; 193 struct host_shadow_regs_s *host_shadow_regs; 194 195 bool recovery; 196 bool notice_send; 197 bool per_ce_irq; 198 uint32_t ce_irq_summary; 199 /* No of copy engines supported */ 200 unsigned int ce_count; 201 atomic_t active_tasklet_cnt; 202 atomic_t active_grp_tasklet_cnt; 203 atomic_t link_suspended; 204 uint32_t *vaddr_rri_on_ddr; 205 qdf_dma_addr_t paddr_rri_on_ddr; 206 int linkstate_vote; 207 bool fastpath_mode_on; 208 atomic_t tasklet_from_intr; 209 int htc_htt_tx_endpoint; 210 qdf_dma_addr_t mem_pa; 211 bool athdiag_procfs_inited; 212 #ifdef FEATURE_NAPI 213 struct qca_napi_data napi_data; 214 #endif /* FEATURE_NAPI */ 215 /* stores ce_service_max_yield_time in ns */ 216 unsigned long long ce_service_max_yield_time; 217 uint8_t ce_service_max_rx_ind_flush; 218 struct hif_driver_state_callbacks callbacks; 219 uint32_t hif_con_param; 220 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 221 uint32_t nss_wifi_ol_mode; 222 #endif 223 void *hal_soc; 224 struct hif_ut_suspend_context ut_suspend_ctx; 225 uint32_t hif_attribute; 226 int wake_irq; 227 int disable_wake_irq; 228 void (*initial_wakeup_cb)(void *); 229 void *initial_wakeup_priv; 230 #ifdef REMOVE_PKT_LOG 231 /* Handle to pktlog device */ 232 void *pktlog_dev; 233 #endif 234 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 235 /* Pointer to the srng event history */ 236 struct hif_event_history *evt_hist[HIF_NUM_INT_CONTEXTS]; 237 #endif 238 239 /* 240 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 241 * for defined here 242 */ 243 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 244 struct ce_desc_hist hif_ce_desc_hist; 245 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 246 #ifdef IPA_OFFLOAD 247 qdf_shared_mem_t *ipa_ce_ring; 248 #endif 249 struct hif_cfg ini_cfg; 250 #ifdef HIF_CE_LOG_INFO 251 qdf_notif_block hif_recovery_notifier; 252 #endif 253 #ifdef HIF_CPU_PERF_AFFINE_MASK 254 /* The CPU hotplug event registration handle */ 255 struct qdf_cpuhp_handler *cpuhp_event_handle; 256 #endif 257 uint32_t irq_unlazy_disable; 258 /* Should the unlzay support for interrupt delivery be disabled */ 259 }; 260 261 static inline 262 void *hif_get_hal_handle(struct hif_opaque_softc *hif_hdl) 263 { 264 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 265 266 if (!sc) 267 return NULL; 268 269 return sc->hal_soc; 270 } 271 272 /** 273 * Max waiting time during Runtime PM suspend to finish all 274 * the tasks. This is in the multiple of 10ms. 275 */ 276 #define HIF_TASK_DRAIN_WAIT_CNT 25 277 278 /** 279 * hif_try_complete_tasks() - Try to complete all the pending tasks 280 * @scn: HIF context 281 * 282 * Try to complete all the pending datapath tasks, i.e. tasklets, 283 * DP group tasklets and works which are queued, in a given time 284 * slot. 285 * 286 * Returns: QDF_STATUS_SUCCESS if all the tasks were completed 287 * QDF error code, if the time slot exhausted 288 */ 289 QDF_STATUS hif_try_complete_tasks(struct hif_softc *scn); 290 291 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 292 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 293 { 294 return !!(sc->nss_wifi_ol_mode); 295 } 296 #else 297 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 298 { 299 return false; 300 } 301 #endif 302 303 static inline uint8_t hif_is_attribute_set(struct hif_softc *sc, 304 uint32_t hif_attrib) 305 { 306 return sc->hif_attribute == hif_attrib; 307 } 308 309 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 310 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 311 { 312 struct hif_softc *scn = (struct hif_softc *)hif_handle; 313 314 scn->event_disable_mask = HIF_EVENT_HIST_DISABLE_MASK; 315 } 316 #else 317 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 318 { 319 } 320 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 321 322 A_target_id_t hif_get_target_id(struct hif_softc *scn); 323 void hif_dump_pipe_debug_count(struct hif_softc *scn); 324 void hif_display_bus_stats(struct hif_opaque_softc *scn); 325 void hif_clear_bus_stats(struct hif_opaque_softc *scn); 326 bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count); 327 void hif_shutdown_device(struct hif_opaque_softc *hif_ctx); 328 int hif_bus_configure(struct hif_softc *scn); 329 void hif_cancel_deferred_target_sleep(struct hif_softc *scn); 330 int hif_config_ce(struct hif_softc *scn); 331 void hif_unconfig_ce(struct hif_softc *scn); 332 void hif_ce_prepare_config(struct hif_softc *scn); 333 QDF_STATUS hif_ce_open(struct hif_softc *scn); 334 void hif_ce_close(struct hif_softc *scn); 335 int athdiag_procfs_init(void *scn); 336 void athdiag_procfs_remove(void); 337 /* routine to modify the initial buffer count to be allocated on an os 338 * platform basis. Platform owner will need to modify this as needed 339 */ 340 qdf_size_t init_buffer_count(qdf_size_t maxSize); 341 342 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg); 343 int hif_get_device_type(uint32_t device_id, 344 uint32_t revision_id, 345 uint32_t *hif_type, uint32_t *target_type); 346 /*These functions are exposed to HDD*/ 347 void hif_nointrs(struct hif_softc *scn); 348 void hif_bus_close(struct hif_softc *ol_sc); 349 QDF_STATUS hif_bus_open(struct hif_softc *ol_sc, 350 enum qdf_bus_type bus_type); 351 QDF_STATUS hif_enable_bus(struct hif_softc *ol_sc, struct device *dev, 352 void *bdev, const struct hif_bus_id *bid, enum hif_enable_type type); 353 void hif_disable_bus(struct hif_softc *scn); 354 #ifdef FEATURE_RUNTIME_PM 355 struct hif_runtime_pm_ctx *hif_bus_get_rpm_ctx(struct hif_softc *hif_sc); 356 struct device *hif_bus_get_dev(struct hif_softc *hif_sc); 357 #endif 358 void hif_bus_prevent_linkdown(struct hif_softc *scn, bool flag); 359 int hif_bus_get_context_size(enum qdf_bus_type bus_type); 360 void hif_read_phy_mem_base(struct hif_softc *scn, qdf_dma_addr_t *bar_value); 361 uint32_t hif_get_conparam(struct hif_softc *scn); 362 struct hif_driver_state_callbacks *hif_get_callbacks_handle( 363 struct hif_softc *scn); 364 bool hif_is_driver_unloading(struct hif_softc *scn); 365 bool hif_is_load_or_unload_in_progress(struct hif_softc *scn); 366 bool hif_is_recovery_in_progress(struct hif_softc *scn); 367 bool hif_is_target_ready(struct hif_softc *scn); 368 369 /** 370 * hif_get_bandwidth_level() - API to get the current bandwidth level 371 * @scn: HIF Context 372 * 373 * Return: PLD bandwidth level 374 */ 375 int hif_get_bandwidth_level(struct hif_opaque_softc *hif_handle); 376 377 void hif_wlan_disable(struct hif_softc *scn); 378 int hif_target_sleep_state_adjust(struct hif_softc *scn, 379 bool sleep_ok, 380 bool wait_for_it); 381 /** 382 * hif_get_rx_ctx_id() - Returns NAPI instance ID based on CE ID 383 * @ctx_id: Rx CE context ID 384 * @hif_hdl: HIF Context 385 * 386 * Return: Rx instance ID 387 */ 388 int hif_get_rx_ctx_id(int ctx_id, struct hif_opaque_softc *hif_hdl); 389 void hif_ramdump_handler(struct hif_opaque_softc *scn); 390 #ifdef HIF_USB 391 void hif_usb_get_hw_info(struct hif_softc *scn); 392 void hif_usb_ramdump_handler(struct hif_opaque_softc *scn); 393 #else 394 static inline void hif_usb_get_hw_info(struct hif_softc *scn) {} 395 static inline void hif_usb_ramdump_handler(struct hif_opaque_softc *scn) {} 396 #endif 397 398 /** 399 * hif_wake_interrupt_handler() - interrupt handler for standalone wake irq 400 * @irq: the irq number that fired 401 * @context: the opaque pointer passed to request_irq() 402 * 403 * Return: an irq return type 404 */ 405 irqreturn_t hif_wake_interrupt_handler(int irq, void *context); 406 407 #ifdef HIF_SNOC 408 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc); 409 #else 410 static inline 411 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc) 412 { 413 return true; 414 } 415 #endif 416 417 #ifdef ADRASTEA_RRI_ON_DDR 418 void hif_uninit_rri_on_ddr(struct hif_softc *scn); 419 #else 420 static inline 421 void hif_uninit_rri_on_ddr(struct hif_softc *scn) {} 422 #endif 423 #endif /* __HIF_MAIN_H__ */ 424