1 /* 2 * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * NB: Inappropriate references to "HTC" are used in this (and other) 21 * HIF implementations. HTC is typically the calling layer, but it 22 * theoretically could be some alternative. 23 */ 24 25 /* 26 * This holds all state needed to process a pending send/recv interrupt. 27 * The information is saved here as soon as the interrupt occurs (thus 28 * allowing the underlying CE to re-use the ring descriptor). The 29 * information here is eventually processed by a completion processing 30 * thread. 31 */ 32 33 #ifndef __HIF_MAIN_H__ 34 #define __HIF_MAIN_H__ 35 36 #include <qdf_atomic.h> /* qdf_atomic_read */ 37 #include "qdf_lock.h" 38 #include "cepci.h" 39 #include "hif.h" 40 #include "multibus.h" 41 #include "hif_unit_test_suspend_i.h" 42 #ifdef HIF_CE_LOG_INFO 43 #include "qdf_notifier.h" 44 #endif 45 46 #define HIF_MIN_SLEEP_INACTIVITY_TIME_MS 50 47 #define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60 48 49 #define HIF_MAX_BUDGET 0xFFFF 50 51 #define HIF_STATS_INC(_handle, _field, _delta) \ 52 { \ 53 (_handle)->stats._field += _delta; \ 54 } 55 56 /* 57 * This macro implementation is exposed for efficiency only. 58 * The implementation may change and callers should 59 * consider the targid to be a completely opaque handle. 60 */ 61 #define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid))) 62 63 #ifdef QCA_WIFI_3_0 64 #define DISABLE_L1SS_STATES 1 65 #endif 66 67 #define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES 68 69 #ifdef QCA_WIFI_3_0_ADRASTEA 70 #define ADRASTEA_BU 1 71 #else 72 #define ADRASTEA_BU 0 73 #endif 74 75 #ifdef QCA_WIFI_3_0 76 #define HAS_FW_INDICATOR 0 77 #else 78 #define HAS_FW_INDICATOR 1 79 #endif 80 81 82 #define AR9888_DEVICE_ID (0x003c) 83 #define AR6320_DEVICE_ID (0x003e) 84 #define AR6320_FW_1_1 (0x11) 85 #define AR6320_FW_1_3 (0x13) 86 #define AR6320_FW_2_0 (0x20) 87 #define AR6320_FW_3_0 (0x30) 88 #define AR6320_FW_3_2 (0x32) 89 #define QCA6290_EMULATION_DEVICE_ID (0xabcd) 90 #define QCA6290_DEVICE_ID (0x1100) 91 #define QCN9000_DEVICE_ID (0x1104) 92 #define QCN9100_DEVICE_ID (0xFFFB) 93 #define QCA6390_EMULATION_DEVICE_ID (0x0108) 94 #define QCA6390_DEVICE_ID (0x1101) 95 /* TODO: change IDs for HastingsPrime */ 96 #define QCA6490_EMULATION_DEVICE_ID (0x010a) 97 #define QCA6490_DEVICE_ID (0x1103) 98 99 /* TODO: change IDs for Moselle */ 100 #define QCA6750_EMULATION_DEVICE_ID (0x010c) 101 #define QCA6750_DEVICE_ID (0x1105) 102 103 #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021) 104 #define AR9887_DEVICE_ID (0x0050) 105 #define AR900B_DEVICE_ID (0x0040) 106 #define QCA9984_DEVICE_ID (0x0046) 107 #define QCA9888_DEVICE_ID (0x0056) 108 #ifndef IPQ4019_DEVICE_ID 109 #define IPQ4019_DEVICE_ID (0x12ef) 110 #endif 111 #define QCA8074_DEVICE_ID (0xffff) /* Todo: replace this with 112 actual number once available. 113 currently defining this to 0xffff for 114 emulation purpose */ 115 #define QCA8074V2_DEVICE_ID (0xfffe) /* Todo: replace this with actual number */ 116 #define QCA6018_DEVICE_ID (0xfffd) /* Todo: replace this with actual number */ 117 #define QCA5018_DEVICE_ID (0xfffc) /* Todo: replace this with actual number */ 118 /* Genoa */ 119 #define QCN7605_DEVICE_ID (0x1102) /* Genoa PCIe device ID*/ 120 #define QCN7605_COMPOSITE (0x9901) 121 #define QCN7605_STANDALONE (0x9900) 122 #define QCN7605_STANDALONE_V2 (0x9902) 123 #define QCN7605_COMPOSITE_V2 (0x9903) 124 125 #define RUMIM2M_DEVICE_ID_NODE0 0xabc0 126 #define RUMIM2M_DEVICE_ID_NODE1 0xabc1 127 #define RUMIM2M_DEVICE_ID_NODE2 0xabc2 128 #define RUMIM2M_DEVICE_ID_NODE3 0xabc3 129 #define RUMIM2M_DEVICE_ID_NODE4 0xaa10 130 #define RUMIM2M_DEVICE_ID_NODE5 0xaa11 131 132 #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn) 133 #define HIF_GET_IPCI_SOFTC(scn) ((struct hif_ipci_softc *)scn) 134 #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn) 135 #define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn) 136 #define HIF_GET_USB_SOFTC(scn) ((struct hif_usb_softc *)scn) 137 #define HIF_GET_USB_DEVICE(scn) ((struct HIF_DEVICE_USB *)scn) 138 #define HIF_GET_SOFTC(scn) ((struct hif_softc *)scn) 139 #define GET_HIF_OPAQUE_HDL(scn) ((struct hif_opaque_softc *)scn) 140 141 struct hif_ce_stats { 142 int hif_pipe_no_resrc_count; 143 int ce_ring_delta_fail_count; 144 }; 145 146 /* 147 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 148 * for defined here 149 */ 150 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 151 struct ce_desc_hist { 152 qdf_atomic_t history_index[CE_COUNT_MAX]; 153 uint32_t enable[CE_COUNT_MAX]; 154 bool data_enable[CE_COUNT_MAX]; 155 qdf_mutex_t ce_dbg_datamem_lock[CE_COUNT_MAX]; 156 uint32_t hist_index; 157 uint32_t hist_id; 158 void *hist_ev[CE_COUNT_MAX]; 159 }; 160 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 161 162 /** 163 * struct hif_cfg() - store ini config parameters in hif layer 164 * @ce_status_ring_timer_threshold: ce status ring timer threshold 165 * @ce_status_ring_batch_count_threshold: ce status ring batch count threshold 166 */ 167 struct hif_cfg { 168 uint16_t ce_status_ring_timer_threshold; 169 uint8_t ce_status_ring_batch_count_threshold; 170 }; 171 172 struct hif_softc { 173 struct hif_opaque_softc osc; 174 struct hif_config_info hif_config; 175 struct hif_target_info target_info; 176 void __iomem *mem; 177 void __iomem *mem_ce; 178 enum qdf_bus_type bus_type; 179 struct hif_bus_ops bus_ops; 180 void *ce_id_to_state[CE_COUNT_MAX]; 181 qdf_device_t qdf_dev; 182 bool hif_init_done; 183 bool request_irq_done; 184 bool ext_grp_irq_configured; 185 uint8_t ce_latency_stats; 186 /* Packet statistics */ 187 struct hif_ce_stats pkt_stats; 188 enum hif_target_status target_status; 189 uint64_t event_disable_mask; 190 191 struct targetdef_s *targetdef; 192 struct ce_reg_def *target_ce_def; 193 struct hostdef_s *hostdef; 194 struct host_shadow_regs_s *host_shadow_regs; 195 196 bool recovery; 197 bool notice_send; 198 bool per_ce_irq; 199 uint32_t ce_irq_summary; 200 /* No of copy engines supported */ 201 unsigned int ce_count; 202 atomic_t active_tasklet_cnt; 203 atomic_t active_grp_tasklet_cnt; 204 atomic_t link_suspended; 205 uint32_t *vaddr_rri_on_ddr; 206 qdf_dma_addr_t paddr_rri_on_ddr; 207 #ifdef CONFIG_BYPASS_QMI 208 uint32_t *vaddr_qmi_bypass; 209 qdf_dma_addr_t paddr_qmi_bypass; 210 #endif 211 int linkstate_vote; 212 bool fastpath_mode_on; 213 atomic_t tasklet_from_intr; 214 int htc_htt_tx_endpoint; 215 qdf_dma_addr_t mem_pa; 216 bool athdiag_procfs_inited; 217 #ifdef FEATURE_NAPI 218 struct qca_napi_data napi_data; 219 #endif /* FEATURE_NAPI */ 220 /* stores ce_service_max_yield_time in ns */ 221 unsigned long long ce_service_max_yield_time; 222 uint8_t ce_service_max_rx_ind_flush; 223 struct hif_driver_state_callbacks callbacks; 224 uint32_t hif_con_param; 225 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 226 uint32_t nss_wifi_ol_mode; 227 #endif 228 void *hal_soc; 229 struct hif_ut_suspend_context ut_suspend_ctx; 230 uint32_t hif_attribute; 231 int wake_irq; 232 int disable_wake_irq; 233 void (*initial_wakeup_cb)(void *); 234 void *initial_wakeup_priv; 235 #ifdef REMOVE_PKT_LOG 236 /* Handle to pktlog device */ 237 void *pktlog_dev; 238 #endif 239 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 240 /* Pointer to the srng event history */ 241 struct hif_event_history *evt_hist[HIF_NUM_INT_CONTEXTS]; 242 #endif 243 244 /* 245 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 246 * for defined here 247 */ 248 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 249 struct ce_desc_hist hif_ce_desc_hist; 250 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 251 #ifdef IPA_OFFLOAD 252 qdf_shared_mem_t *ipa_ce_ring; 253 #endif 254 struct hif_cfg ini_cfg; 255 #ifdef HIF_CE_LOG_INFO 256 qdf_notif_block hif_recovery_notifier; 257 #endif 258 #ifdef HIF_CPU_PERF_AFFINE_MASK 259 /* The CPU hotplug event registration handle */ 260 struct qdf_cpuhp_handler *cpuhp_event_handle; 261 #endif 262 uint32_t irq_unlazy_disable; 263 /* Should the unlzay support for interrupt delivery be disabled */ 264 /* Flag to indicate whether bus is suspended */ 265 bool bus_suspended; 266 bool pktlog_init; 267 }; 268 269 static inline 270 void *hif_get_hal_handle(struct hif_opaque_softc *hif_hdl) 271 { 272 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 273 274 if (!sc) 275 return NULL; 276 277 return sc->hal_soc; 278 } 279 280 /** 281 * Max waiting time during Runtime PM suspend to finish all 282 * the tasks. This is in the multiple of 10ms. 283 */ 284 #define HIF_TASK_DRAIN_WAIT_CNT 25 285 286 /** 287 * hif_try_complete_tasks() - Try to complete all the pending tasks 288 * @scn: HIF context 289 * 290 * Try to complete all the pending datapath tasks, i.e. tasklets, 291 * DP group tasklets and works which are queued, in a given time 292 * slot. 293 * 294 * Returns: QDF_STATUS_SUCCESS if all the tasks were completed 295 * QDF error code, if the time slot exhausted 296 */ 297 QDF_STATUS hif_try_complete_tasks(struct hif_softc *scn); 298 299 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 300 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 301 { 302 return !!(sc->nss_wifi_ol_mode); 303 } 304 #else 305 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 306 { 307 return false; 308 } 309 #endif 310 311 static inline uint8_t hif_is_attribute_set(struct hif_softc *sc, 312 uint32_t hif_attrib) 313 { 314 return sc->hif_attribute == hif_attrib; 315 } 316 317 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 318 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 319 { 320 struct hif_softc *scn = (struct hif_softc *)hif_handle; 321 322 scn->event_disable_mask = HIF_EVENT_HIST_DISABLE_MASK; 323 } 324 #else 325 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 326 { 327 } 328 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 329 330 A_target_id_t hif_get_target_id(struct hif_softc *scn); 331 void hif_dump_pipe_debug_count(struct hif_softc *scn); 332 void hif_display_bus_stats(struct hif_opaque_softc *scn); 333 void hif_clear_bus_stats(struct hif_opaque_softc *scn); 334 bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count); 335 void hif_shutdown_device(struct hif_opaque_softc *hif_ctx); 336 int hif_bus_configure(struct hif_softc *scn); 337 void hif_cancel_deferred_target_sleep(struct hif_softc *scn); 338 int hif_config_ce(struct hif_softc *scn); 339 int hif_config_ce_pktlog(struct hif_opaque_softc *hif_ctx); 340 int hif_config_ce_by_id(struct hif_softc *scn, int pipe_num); 341 void hif_unconfig_ce(struct hif_softc *scn); 342 void hif_ce_prepare_config(struct hif_softc *scn); 343 QDF_STATUS hif_ce_open(struct hif_softc *scn); 344 void hif_ce_close(struct hif_softc *scn); 345 int athdiag_procfs_init(void *scn); 346 void athdiag_procfs_remove(void); 347 /* routine to modify the initial buffer count to be allocated on an os 348 * platform basis. Platform owner will need to modify this as needed 349 */ 350 qdf_size_t init_buffer_count(qdf_size_t maxSize); 351 352 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg); 353 int hif_get_device_type(uint32_t device_id, 354 uint32_t revision_id, 355 uint32_t *hif_type, uint32_t *target_type); 356 /*These functions are exposed to HDD*/ 357 void hif_nointrs(struct hif_softc *scn); 358 void hif_bus_close(struct hif_softc *ol_sc); 359 QDF_STATUS hif_bus_open(struct hif_softc *ol_sc, 360 enum qdf_bus_type bus_type); 361 QDF_STATUS hif_enable_bus(struct hif_softc *ol_sc, struct device *dev, 362 void *bdev, const struct hif_bus_id *bid, enum hif_enable_type type); 363 void hif_disable_bus(struct hif_softc *scn); 364 #ifdef FEATURE_RUNTIME_PM 365 struct hif_runtime_pm_ctx *hif_bus_get_rpm_ctx(struct hif_softc *hif_sc); 366 struct device *hif_bus_get_dev(struct hif_softc *hif_sc); 367 #endif 368 void hif_bus_prevent_linkdown(struct hif_softc *scn, bool flag); 369 int hif_bus_get_context_size(enum qdf_bus_type bus_type); 370 void hif_read_phy_mem_base(struct hif_softc *scn, qdf_dma_addr_t *bar_value); 371 uint32_t hif_get_conparam(struct hif_softc *scn); 372 struct hif_driver_state_callbacks *hif_get_callbacks_handle( 373 struct hif_softc *scn); 374 bool hif_is_driver_unloading(struct hif_softc *scn); 375 bool hif_is_load_or_unload_in_progress(struct hif_softc *scn); 376 bool hif_is_recovery_in_progress(struct hif_softc *scn); 377 bool hif_is_target_ready(struct hif_softc *scn); 378 379 /** 380 * hif_get_bandwidth_level() - API to get the current bandwidth level 381 * @scn: HIF Context 382 * 383 * Return: PLD bandwidth level 384 */ 385 int hif_get_bandwidth_level(struct hif_opaque_softc *hif_handle); 386 387 void hif_wlan_disable(struct hif_softc *scn); 388 int hif_target_sleep_state_adjust(struct hif_softc *scn, 389 bool sleep_ok, 390 bool wait_for_it); 391 392 #ifdef DP_MEM_PRE_ALLOC 393 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 394 qdf_size_t size, 395 qdf_dma_addr_t *paddr, 396 uint32_t ring_type, 397 uint8_t *is_mem_prealloc); 398 399 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 400 qdf_size_t size, 401 void *vaddr, 402 qdf_dma_addr_t paddr, 403 qdf_dma_context_t memctx, 404 uint8_t is_mem_prealloc); 405 #else 406 static inline 407 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 408 qdf_size_t size, 409 qdf_dma_addr_t *paddr, 410 uint32_t ring_type, 411 uint8_t *is_mem_prealloc) 412 { 413 return qdf_mem_alloc_consistent(scn->qdf_dev, 414 scn->qdf_dev->dev, 415 size, 416 paddr); 417 } 418 419 static inline 420 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 421 qdf_size_t size, 422 void *vaddr, 423 qdf_dma_addr_t paddr, 424 qdf_dma_context_t memctx, 425 uint8_t is_mem_prealloc) 426 { 427 return qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 428 size, vaddr, paddr, memctx); 429 } 430 #endif 431 432 /** 433 * hif_get_rx_ctx_id() - Returns NAPI instance ID based on CE ID 434 * @ctx_id: Rx CE context ID 435 * @hif_hdl: HIF Context 436 * 437 * Return: Rx instance ID 438 */ 439 int hif_get_rx_ctx_id(int ctx_id, struct hif_opaque_softc *hif_hdl); 440 void hif_ramdump_handler(struct hif_opaque_softc *scn); 441 #ifdef HIF_USB 442 void hif_usb_get_hw_info(struct hif_softc *scn); 443 void hif_usb_ramdump_handler(struct hif_opaque_softc *scn); 444 #else 445 static inline void hif_usb_get_hw_info(struct hif_softc *scn) {} 446 static inline void hif_usb_ramdump_handler(struct hif_opaque_softc *scn) {} 447 #endif 448 449 /** 450 * hif_wake_interrupt_handler() - interrupt handler for standalone wake irq 451 * @irq: the irq number that fired 452 * @context: the opaque pointer passed to request_irq() 453 * 454 * Return: an irq return type 455 */ 456 irqreturn_t hif_wake_interrupt_handler(int irq, void *context); 457 458 #ifdef HIF_SNOC 459 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc); 460 #else 461 static inline 462 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc) 463 { 464 return true; 465 } 466 #endif 467 468 #ifdef ADRASTEA_RRI_ON_DDR 469 void hif_uninit_rri_on_ddr(struct hif_softc *scn); 470 #else 471 static inline 472 void hif_uninit_rri_on_ddr(struct hif_softc *scn) {} 473 #endif 474 void hif_cleanup_static_buf_to_target(struct hif_softc *scn); 475 #endif /* __HIF_MAIN_H__ */ 476