1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * NB: Inappropriate references to "HTC" are used in this (and other) 22 * HIF implementations. HTC is typically the calling layer, but it 23 * theoretically could be some alternative. 24 */ 25 26 /* 27 * This holds all state needed to process a pending send/recv interrupt. 28 * The information is saved here as soon as the interrupt occurs (thus 29 * allowing the underlying CE to re-use the ring descriptor). The 30 * information here is eventually processed by a completion processing 31 * thread. 32 */ 33 34 #ifndef __HIF_MAIN_H__ 35 #define __HIF_MAIN_H__ 36 37 #include <qdf_atomic.h> /* qdf_atomic_read */ 38 #include "qdf_lock.h" 39 #include "cepci.h" 40 #include "hif.h" 41 #include "multibus.h" 42 #include "hif_unit_test_suspend_i.h" 43 #ifdef HIF_CE_LOG_INFO 44 #include "qdf_notifier.h" 45 #endif 46 47 #define HIF_MIN_SLEEP_INACTIVITY_TIME_MS 50 48 #define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60 49 50 #define HIF_MAX_BUDGET 0xFFFF 51 52 #define HIF_STATS_INC(_handle, _field, _delta) \ 53 { \ 54 (_handle)->stats._field += _delta; \ 55 } 56 57 /* 58 * This macro implementation is exposed for efficiency only. 59 * The implementation may change and callers should 60 * consider the targid to be a completely opaque handle. 61 */ 62 #define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid))) 63 64 #ifdef QCA_WIFI_3_0 65 #define DISABLE_L1SS_STATES 1 66 #endif 67 68 #define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES 69 70 #ifdef QCA_WIFI_3_0_ADRASTEA 71 #define ADRASTEA_BU 1 72 #else 73 #define ADRASTEA_BU 0 74 #endif 75 76 #ifdef QCA_WIFI_3_0 77 #define HAS_FW_INDICATOR 0 78 #else 79 #define HAS_FW_INDICATOR 1 80 #endif 81 82 83 #define AR9888_DEVICE_ID (0x003c) 84 #define AR6320_DEVICE_ID (0x003e) 85 #define AR6320_FW_1_1 (0x11) 86 #define AR6320_FW_1_3 (0x13) 87 #define AR6320_FW_2_0 (0x20) 88 #define AR6320_FW_3_0 (0x30) 89 #define AR6320_FW_3_2 (0x32) 90 #define QCA6290_EMULATION_DEVICE_ID (0xabcd) 91 #define QCA6290_DEVICE_ID (0x1100) 92 #define QCN9000_DEVICE_ID (0x1104) 93 #define QCN9224_DEVICE_ID (0x1109) 94 #define QCN6122_DEVICE_ID (0xFFFB) 95 #define QCA6390_EMULATION_DEVICE_ID (0x0108) 96 #define QCA6390_DEVICE_ID (0x1101) 97 /* TODO: change IDs for HastingsPrime */ 98 #define QCA6490_EMULATION_DEVICE_ID (0x010a) 99 #define QCA6490_DEVICE_ID (0x1103) 100 #define MANGO_DEVICE_ID (0x110a) 101 102 /* TODO: change IDs for Moselle */ 103 #define QCA6750_EMULATION_DEVICE_ID (0x010c) 104 #define QCA6750_DEVICE_ID (0x1105) 105 106 /* TODO: change IDs for Hamilton */ 107 #define KIWI_DEVICE_ID (0x1107) 108 109 #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021) 110 #define AR9887_DEVICE_ID (0x0050) 111 #define AR900B_DEVICE_ID (0x0040) 112 #define QCA9984_DEVICE_ID (0x0046) 113 #define QCA9888_DEVICE_ID (0x0056) 114 #define QCA8074_DEVICE_ID (0xffff) /* Todo: replace this with 115 actual number once available. 116 currently defining this to 0xffff for 117 emulation purpose */ 118 #define QCA8074V2_DEVICE_ID (0xfffe) /* Todo: replace this with actual number */ 119 #define QCA6018_DEVICE_ID (0xfffd) /* Todo: replace this with actual number */ 120 #define QCA5018_DEVICE_ID (0xfffc) /* Todo: replace this with actual number */ 121 #define QCA9574_DEVICE_ID (0xfffa) 122 /* Genoa */ 123 #define QCN7605_DEVICE_ID (0x1102) /* Genoa PCIe device ID*/ 124 #define QCN7605_COMPOSITE (0x9901) 125 #define QCN7605_STANDALONE (0x9900) 126 #define QCN7605_STANDALONE_V2 (0x9902) 127 #define QCN7605_COMPOSITE_V2 (0x9903) 128 129 #define RUMIM2M_DEVICE_ID_NODE0 0xabc0 130 #define RUMIM2M_DEVICE_ID_NODE1 0xabc1 131 #define RUMIM2M_DEVICE_ID_NODE2 0xabc2 132 #define RUMIM2M_DEVICE_ID_NODE3 0xabc3 133 #define RUMIM2M_DEVICE_ID_NODE4 0xaa10 134 #define RUMIM2M_DEVICE_ID_NODE5 0xaa11 135 136 #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn) 137 #define HIF_GET_IPCI_SOFTC(scn) ((struct hif_ipci_softc *)scn) 138 #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn) 139 #define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn) 140 #define HIF_GET_USB_SOFTC(scn) ((struct hif_usb_softc *)scn) 141 #define HIF_GET_USB_DEVICE(scn) ((struct HIF_DEVICE_USB *)scn) 142 #define HIF_GET_SOFTC(scn) ((struct hif_softc *)scn) 143 #define GET_HIF_OPAQUE_HDL(scn) ((struct hif_opaque_softc *)scn) 144 145 #ifdef QCA_WIFI_QCN9224 146 #define NUM_CE_AVAILABLE 16 147 #else 148 #define NUM_CE_AVAILABLE 12 149 #endif 150 /* Add 1 here to store default configuration in index 0 */ 151 #define NUM_CE_CONTEXT (NUM_CE_AVAILABLE + 1) 152 153 #define CE_INTERRUPT_IDX(x) x 154 155 struct ce_int_assignment { 156 uint8_t msi_idx[NUM_CE_AVAILABLE]; 157 }; 158 159 struct hif_ce_stats { 160 int hif_pipe_no_resrc_count; 161 int ce_ring_delta_fail_count; 162 }; 163 164 #ifdef HIF_DETECTION_LATENCY_ENABLE 165 struct hif_latency_detect { 166 qdf_timer_t detect_latency_timer; 167 uint32_t detect_latency_timer_timeout; 168 bool is_timer_started; 169 bool enable_detection; 170 /* threshold when stall happens */ 171 uint32_t detect_latency_threshold; 172 int ce2_tasklet_sched_cpuid; 173 qdf_time_t ce2_tasklet_sched_time; 174 qdf_time_t ce2_tasklet_exec_time; 175 qdf_time_t credit_request_time; 176 qdf_time_t credit_report_time; 177 }; 178 #endif 179 180 /* 181 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 182 * for defined here 183 */ 184 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 185 struct ce_desc_hist { 186 qdf_atomic_t history_index[CE_COUNT_MAX]; 187 uint8_t ce_id_hist_map[CE_COUNT_MAX]; 188 bool enable[CE_COUNT_MAX]; 189 bool data_enable[CE_COUNT_MAX]; 190 qdf_mutex_t ce_dbg_datamem_lock[CE_COUNT_MAX]; 191 uint32_t hist_index; 192 uint32_t hist_id; 193 void *hist_ev[CE_COUNT_MAX]; 194 }; 195 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 196 197 /** 198 * struct hif_cfg() - store ini config parameters in hif layer 199 * @ce_status_ring_timer_threshold: ce status ring timer threshold 200 * @ce_status_ring_batch_count_threshold: ce status ring batch count threshold 201 */ 202 struct hif_cfg { 203 uint16_t ce_status_ring_timer_threshold; 204 uint8_t ce_status_ring_batch_count_threshold; 205 }; 206 207 #ifdef DP_UMAC_HW_RESET_SUPPORT 208 /** 209 * struct hif_umac_reset_ctx - UMAC HW reset context at HIF layer 210 * @intr_tq: Tasklet structure 211 * @cb_handler: Callback handler 212 * @cb_ctx: Argument to be passed to @cb_handler 213 * @os_irq: Interrupt number for this IRQ 214 * @irq_configured: Whether the IRQ has been configured 215 */ 216 struct hif_umac_reset_ctx { 217 struct tasklet_struct intr_tq; 218 int (*cb_handler)(void *cb_ctx); 219 void *cb_ctx; 220 uint32_t os_irq; 221 bool irq_configured; 222 }; 223 #endif 224 225 struct hif_softc { 226 struct hif_opaque_softc osc; 227 struct hif_config_info hif_config; 228 struct hif_target_info target_info; 229 void __iomem *mem; 230 void __iomem *mem_ce; 231 enum qdf_bus_type bus_type; 232 struct hif_bus_ops bus_ops; 233 void *ce_id_to_state[CE_COUNT_MAX]; 234 qdf_device_t qdf_dev; 235 bool hif_init_done; 236 bool request_irq_done; 237 bool ext_grp_irq_configured; 238 bool free_irq_done; 239 uint8_t ce_latency_stats; 240 /* Packet statistics */ 241 struct hif_ce_stats pkt_stats; 242 enum hif_target_status target_status; 243 uint64_t event_enable_mask; 244 245 struct targetdef_s *targetdef; 246 struct ce_reg_def *target_ce_def; 247 struct hostdef_s *hostdef; 248 struct host_shadow_regs_s *host_shadow_regs; 249 250 bool recovery; 251 bool notice_send; 252 bool per_ce_irq; 253 uint32_t ce_irq_summary; 254 /* No of copy engines supported */ 255 unsigned int ce_count; 256 struct ce_int_assignment *int_assignment; 257 atomic_t active_tasklet_cnt; 258 atomic_t active_grp_tasklet_cnt; 259 atomic_t link_suspended; 260 uint32_t *vaddr_rri_on_ddr; 261 qdf_dma_addr_t paddr_rri_on_ddr; 262 #ifdef CONFIG_BYPASS_QMI 263 uint32_t *vaddr_qmi_bypass; 264 qdf_dma_addr_t paddr_qmi_bypass; 265 #endif 266 int linkstate_vote; 267 bool fastpath_mode_on; 268 atomic_t tasklet_from_intr; 269 int htc_htt_tx_endpoint; 270 qdf_dma_addr_t mem_pa; 271 bool athdiag_procfs_inited; 272 #ifdef FEATURE_NAPI 273 struct qca_napi_data napi_data; 274 #endif /* FEATURE_NAPI */ 275 /* stores ce_service_max_yield_time in ns */ 276 unsigned long long ce_service_max_yield_time; 277 uint8_t ce_service_max_rx_ind_flush; 278 struct hif_driver_state_callbacks callbacks; 279 uint32_t hif_con_param; 280 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 281 uint32_t nss_wifi_ol_mode; 282 #endif 283 void *hal_soc; 284 struct hif_ut_suspend_context ut_suspend_ctx; 285 uint32_t hif_attribute; 286 int wake_irq; 287 int disable_wake_irq; 288 hif_pm_wake_irq_type wake_irq_type; 289 void (*initial_wakeup_cb)(void *); 290 void *initial_wakeup_priv; 291 #ifdef REMOVE_PKT_LOG 292 /* Handle to pktlog device */ 293 void *pktlog_dev; 294 #endif 295 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 296 /* Pointer to the srng event history */ 297 struct hif_event_history *evt_hist[HIF_NUM_INT_CONTEXTS]; 298 #endif 299 300 /* 301 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 302 * for defined here 303 */ 304 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 305 struct ce_desc_hist hif_ce_desc_hist; 306 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 307 #ifdef IPA_OFFLOAD 308 qdf_shared_mem_t *ipa_ce_ring; 309 #endif 310 struct hif_cfg ini_cfg; 311 #ifdef HIF_CE_LOG_INFO 312 qdf_notif_block hif_recovery_notifier; 313 #endif 314 #ifdef HIF_CPU_PERF_AFFINE_MASK 315 /* The CPU hotplug event registration handle */ 316 struct qdf_cpuhp_handler *cpuhp_event_handle; 317 #endif 318 uint32_t irq_unlazy_disable; 319 /* Should the unlzay support for interrupt delivery be disabled */ 320 /* Flag to indicate whether bus is suspended */ 321 bool bus_suspended; 322 bool pktlog_init; 323 #ifdef FEATURE_RUNTIME_PM 324 /* Variable to track the link state change in RTPM */ 325 qdf_atomic_t pm_link_state; 326 #endif 327 #ifdef HIF_DETECTION_LATENCY_ENABLE 328 struct hif_latency_detect latency_detect; 329 #endif 330 #ifdef FEATURE_RUNTIME_PM 331 qdf_runtime_lock_t prevent_linkdown_lock; 332 #endif 333 #ifdef SYSTEM_PM_CHECK 334 qdf_atomic_t sys_pm_state; 335 #endif 336 #if defined(HIF_IPCI) && defined(FEATURE_HAL_DELAYED_REG_WRITE) 337 qdf_atomic_t dp_ep_vote_access; 338 qdf_atomic_t ep_vote_access; 339 #endif 340 /* CMEM address target reserved for host usage */ 341 uint64_t cmem_start; 342 /* CMEM size target reserved */ 343 uint64_t cmem_size; 344 #ifdef DP_UMAC_HW_RESET_SUPPORT 345 struct hif_umac_reset_ctx umac_reset_ctx; 346 #endif 347 }; 348 349 static inline 350 void *hif_get_hal_handle(struct hif_opaque_softc *hif_hdl) 351 { 352 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 353 354 if (!sc) 355 return NULL; 356 357 return sc->hal_soc; 358 } 359 360 /** 361 * hif_get_cmem_info() - get CMEM address and size from HIF handle 362 * @hif_hdl: HIF handle pointer 363 * @cmem_start: pointer for CMEM address 364 * @cmem_size: pointer for CMEM size 365 * 366 * Return: None. 367 */ 368 static inline 369 void hif_get_cmem_info(struct hif_opaque_softc *hif_hdl, 370 uint64_t *cmem_start, 371 uint64_t *cmem_size) 372 { 373 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 374 375 *cmem_start = sc->cmem_start; 376 *cmem_size = sc->cmem_size; 377 } 378 379 /** 380 * hif_get_num_active_tasklets() - get the number of active 381 * tasklets pending to be completed. 382 * @scn: HIF context 383 * 384 * Returns: the number of tasklets which are active 385 */ 386 static inline int hif_get_num_active_tasklets(struct hif_softc *scn) 387 { 388 return qdf_atomic_read(&scn->active_tasklet_cnt); 389 } 390 391 /** 392 * Max waiting time during Runtime PM suspend to finish all 393 * the tasks. This is in the multiple of 10ms. 394 */ 395 #define HIF_TASK_DRAIN_WAIT_CNT 25 396 397 /** 398 * hif_try_complete_tasks() - Try to complete all the pending tasks 399 * @scn: HIF context 400 * 401 * Try to complete all the pending datapath tasks, i.e. tasklets, 402 * DP group tasklets and works which are queued, in a given time 403 * slot. 404 * 405 * Returns: QDF_STATUS_SUCCESS if all the tasks were completed 406 * QDF error code, if the time slot exhausted 407 */ 408 QDF_STATUS hif_try_complete_tasks(struct hif_softc *scn); 409 410 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 411 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 412 { 413 return !!(sc->nss_wifi_ol_mode); 414 } 415 #else 416 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 417 { 418 return false; 419 } 420 #endif 421 422 static inline uint8_t hif_is_attribute_set(struct hif_softc *sc, 423 uint32_t hif_attrib) 424 { 425 return sc->hif_attribute == hif_attrib; 426 } 427 428 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 429 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 430 { 431 struct hif_softc *scn = (struct hif_softc *)hif_handle; 432 433 scn->event_enable_mask = HIF_EVENT_HIST_ENABLE_MASK; 434 } 435 #else 436 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 437 { 438 } 439 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 440 441 A_target_id_t hif_get_target_id(struct hif_softc *scn); 442 void hif_dump_pipe_debug_count(struct hif_softc *scn); 443 void hif_display_bus_stats(struct hif_opaque_softc *scn); 444 void hif_clear_bus_stats(struct hif_opaque_softc *scn); 445 bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count); 446 void hif_shutdown_device(struct hif_opaque_softc *hif_ctx); 447 int hif_bus_configure(struct hif_softc *scn); 448 void hif_cancel_deferred_target_sleep(struct hif_softc *scn); 449 int hif_config_ce(struct hif_softc *scn); 450 int hif_config_ce_pktlog(struct hif_opaque_softc *hif_ctx); 451 int hif_config_ce_by_id(struct hif_softc *scn, int pipe_num); 452 void hif_unconfig_ce(struct hif_softc *scn); 453 void hif_ce_prepare_config(struct hif_softc *scn); 454 QDF_STATUS hif_ce_open(struct hif_softc *scn); 455 void hif_ce_close(struct hif_softc *scn); 456 int athdiag_procfs_init(void *scn); 457 void athdiag_procfs_remove(void); 458 /* routine to modify the initial buffer count to be allocated on an os 459 * platform basis. Platform owner will need to modify this as needed 460 */ 461 qdf_size_t init_buffer_count(qdf_size_t maxSize); 462 463 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg); 464 int hif_get_device_type(uint32_t device_id, 465 uint32_t revision_id, 466 uint32_t *hif_type, uint32_t *target_type); 467 /*These functions are exposed to HDD*/ 468 void hif_nointrs(struct hif_softc *scn); 469 void hif_bus_close(struct hif_softc *ol_sc); 470 QDF_STATUS hif_bus_open(struct hif_softc *ol_sc, 471 enum qdf_bus_type bus_type); 472 QDF_STATUS hif_enable_bus(struct hif_softc *ol_sc, struct device *dev, 473 void *bdev, const struct hif_bus_id *bid, enum hif_enable_type type); 474 void hif_disable_bus(struct hif_softc *scn); 475 void hif_bus_prevent_linkdown(struct hif_softc *scn, bool flag); 476 int hif_bus_get_context_size(enum qdf_bus_type bus_type); 477 void hif_read_phy_mem_base(struct hif_softc *scn, qdf_dma_addr_t *bar_value); 478 uint32_t hif_get_conparam(struct hif_softc *scn); 479 struct hif_driver_state_callbacks *hif_get_callbacks_handle( 480 struct hif_softc *scn); 481 bool hif_is_driver_unloading(struct hif_softc *scn); 482 bool hif_is_load_or_unload_in_progress(struct hif_softc *scn); 483 bool hif_is_recovery_in_progress(struct hif_softc *scn); 484 bool hif_is_target_ready(struct hif_softc *scn); 485 486 /** 487 * hif_get_bandwidth_level() - API to get the current bandwidth level 488 * @scn: HIF Context 489 * 490 * Return: PLD bandwidth level 491 */ 492 int hif_get_bandwidth_level(struct hif_opaque_softc *hif_handle); 493 494 void hif_wlan_disable(struct hif_softc *scn); 495 int hif_target_sleep_state_adjust(struct hif_softc *scn, 496 bool sleep_ok, 497 bool wait_for_it); 498 499 #ifdef DP_MEM_PRE_ALLOC 500 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 501 qdf_size_t size, 502 qdf_dma_addr_t *paddr, 503 uint32_t ring_type, 504 uint8_t *is_mem_prealloc); 505 506 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 507 qdf_size_t size, 508 void *vaddr, 509 qdf_dma_addr_t paddr, 510 qdf_dma_context_t memctx, 511 uint8_t is_mem_prealloc); 512 #else 513 static inline 514 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 515 qdf_size_t size, 516 qdf_dma_addr_t *paddr, 517 uint32_t ring_type, 518 uint8_t *is_mem_prealloc) 519 { 520 return qdf_mem_alloc_consistent(scn->qdf_dev, 521 scn->qdf_dev->dev, 522 size, 523 paddr); 524 } 525 526 static inline 527 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 528 qdf_size_t size, 529 void *vaddr, 530 qdf_dma_addr_t paddr, 531 qdf_dma_context_t memctx, 532 uint8_t is_mem_prealloc) 533 { 534 return qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 535 size, vaddr, paddr, memctx); 536 } 537 #endif 538 539 /** 540 * hif_get_rx_ctx_id() - Returns NAPI instance ID based on CE ID 541 * @ctx_id: Rx CE context ID 542 * @hif_hdl: HIF Context 543 * 544 * Return: Rx instance ID 545 */ 546 int hif_get_rx_ctx_id(int ctx_id, struct hif_opaque_softc *hif_hdl); 547 void hif_ramdump_handler(struct hif_opaque_softc *scn); 548 #ifdef HIF_USB 549 void hif_usb_get_hw_info(struct hif_softc *scn); 550 void hif_usb_ramdump_handler(struct hif_opaque_softc *scn); 551 #else 552 static inline void hif_usb_get_hw_info(struct hif_softc *scn) {} 553 static inline void hif_usb_ramdump_handler(struct hif_opaque_softc *scn) {} 554 #endif 555 556 /** 557 * hif_wake_interrupt_handler() - interrupt handler for standalone wake irq 558 * @irq: the irq number that fired 559 * @context: the opaque pointer passed to request_irq() 560 * 561 * Return: an irq return type 562 */ 563 irqreturn_t hif_wake_interrupt_handler(int irq, void *context); 564 565 #ifdef HIF_SNOC 566 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc); 567 #else 568 static inline 569 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc) 570 { 571 return true; 572 } 573 #endif 574 575 #ifdef ADRASTEA_RRI_ON_DDR 576 void hif_uninit_rri_on_ddr(struct hif_softc *scn); 577 #else 578 static inline 579 void hif_uninit_rri_on_ddr(struct hif_softc *scn) {} 580 #endif 581 void hif_cleanup_static_buf_to_target(struct hif_softc *scn); 582 583 #ifdef FEATURE_RUNTIME_PM 584 /** 585 * hif_runtime_prevent_linkdown() - prevent or allow a runtime pm from occurring 586 * @scn: hif context 587 * @is_get: prevent linkdown if true otherwise allow 588 * 589 * this api should only be called as part of bus prevent linkdown 590 */ 591 void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get); 592 #else 593 static inline 594 void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get) 595 { 596 } 597 #endif 598 599 #endif /* __HIF_MAIN_H__ */ 600