1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * NB: Inappropriate references to "HTC" are used in this (and other) 22 * HIF implementations. HTC is typically the calling layer, but it 23 * theoretically could be some alternative. 24 */ 25 26 /* 27 * This holds all state needed to process a pending send/recv interrupt. 28 * The information is saved here as soon as the interrupt occurs (thus 29 * allowing the underlying CE to re-use the ring descriptor). The 30 * information here is eventually processed by a completion processing 31 * thread. 32 */ 33 34 #ifndef __HIF_MAIN_H__ 35 #define __HIF_MAIN_H__ 36 37 #include <qdf_atomic.h> /* qdf_atomic_read */ 38 #include "qdf_lock.h" 39 #include "cepci.h" 40 #include "hif.h" 41 #include "multibus.h" 42 #include "hif_unit_test_suspend_i.h" 43 #ifdef HIF_CE_LOG_INFO 44 #include "qdf_notifier.h" 45 #endif 46 47 #define HIF_MIN_SLEEP_INACTIVITY_TIME_MS 50 48 #define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60 49 50 #define HIF_MAX_BUDGET 0xFFFF 51 52 #define HIF_STATS_INC(_handle, _field, _delta) \ 53 { \ 54 (_handle)->stats._field += _delta; \ 55 } 56 57 /* 58 * This macro implementation is exposed for efficiency only. 59 * The implementation may change and callers should 60 * consider the targid to be a completely opaque handle. 61 */ 62 #define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid))) 63 64 #ifdef QCA_WIFI_3_0 65 #define DISABLE_L1SS_STATES 1 66 #endif 67 68 #define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES 69 70 #ifdef QCA_WIFI_3_0_ADRASTEA 71 #define ADRASTEA_BU 1 72 #else 73 #define ADRASTEA_BU 0 74 #endif 75 76 #ifdef QCA_WIFI_3_0 77 #define HAS_FW_INDICATOR 0 78 #else 79 #define HAS_FW_INDICATOR 1 80 #endif 81 82 83 #define AR9888_DEVICE_ID (0x003c) 84 #define AR6320_DEVICE_ID (0x003e) 85 #define AR6320_FW_1_1 (0x11) 86 #define AR6320_FW_1_3 (0x13) 87 #define AR6320_FW_2_0 (0x20) 88 #define AR6320_FW_3_0 (0x30) 89 #define AR6320_FW_3_2 (0x32) 90 #define QCA6290_EMULATION_DEVICE_ID (0xabcd) 91 #define QCA6290_DEVICE_ID (0x1100) 92 #define QCN9000_DEVICE_ID (0x1104) 93 #define QCN9224_DEVICE_ID (0x1109) 94 #define QCN6122_DEVICE_ID (0xFFFB) 95 #define QCN9160_DEVICE_ID (0xFFF8) 96 #define QCA6390_EMULATION_DEVICE_ID (0x0108) 97 #define QCA6390_DEVICE_ID (0x1101) 98 /* TODO: change IDs for HastingsPrime */ 99 #define QCA6490_EMULATION_DEVICE_ID (0x010a) 100 #define QCA6490_DEVICE_ID (0x1103) 101 #define MANGO_DEVICE_ID (0x110a) 102 103 /* TODO: change IDs for Moselle */ 104 #define QCA6750_EMULATION_DEVICE_ID (0x010c) 105 #define QCA6750_DEVICE_ID (0x1105) 106 107 /* TODO: change IDs for Hamilton */ 108 #define KIWI_DEVICE_ID (0x1107) 109 110 #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021) 111 #define AR9887_DEVICE_ID (0x0050) 112 #define AR900B_DEVICE_ID (0x0040) 113 #define QCA9984_DEVICE_ID (0x0046) 114 #define QCA9888_DEVICE_ID (0x0056) 115 #define QCA8074_DEVICE_ID (0xffff) /* Todo: replace this with 116 actual number once available. 117 currently defining this to 0xffff for 118 emulation purpose */ 119 #define QCA8074V2_DEVICE_ID (0xfffe) /* Todo: replace this with actual number */ 120 #define QCA6018_DEVICE_ID (0xfffd) /* Todo: replace this with actual number */ 121 #define QCA5018_DEVICE_ID (0xfffc) /* Todo: replace this with actual number */ 122 #define QCA9574_DEVICE_ID (0xfffa) 123 #define QCA5332_DEVICE_ID (0xfff9) 124 /* Genoa */ 125 #define QCN7605_DEVICE_ID (0x1102) /* Genoa PCIe device ID*/ 126 #define QCN7605_COMPOSITE (0x9901) 127 #define QCN7605_STANDALONE (0x9900) 128 #define QCN7605_STANDALONE_V2 (0x9902) 129 #define QCN7605_COMPOSITE_V2 (0x9903) 130 131 #define RUMIM2M_DEVICE_ID_NODE0 0xabc0 132 #define RUMIM2M_DEVICE_ID_NODE1 0xabc1 133 #define RUMIM2M_DEVICE_ID_NODE2 0xabc2 134 #define RUMIM2M_DEVICE_ID_NODE3 0xabc3 135 #define RUMIM2M_DEVICE_ID_NODE4 0xaa10 136 #define RUMIM2M_DEVICE_ID_NODE5 0xaa11 137 138 #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn) 139 #define HIF_GET_IPCI_SOFTC(scn) ((struct hif_ipci_softc *)scn) 140 #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn) 141 #define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn) 142 #define HIF_GET_USB_SOFTC(scn) ((struct hif_usb_softc *)scn) 143 #define HIF_GET_USB_DEVICE(scn) ((struct HIF_DEVICE_USB *)scn) 144 #define HIF_GET_SOFTC(scn) ((struct hif_softc *)scn) 145 #define GET_HIF_OPAQUE_HDL(scn) ((struct hif_opaque_softc *)scn) 146 147 #ifdef QCA_WIFI_QCN9224 148 #define NUM_CE_AVAILABLE 16 149 #else 150 #define NUM_CE_AVAILABLE 12 151 #endif 152 /* Add 1 here to store default configuration in index 0 */ 153 #define NUM_CE_CONTEXT (NUM_CE_AVAILABLE + 1) 154 155 #define CE_INTERRUPT_IDX(x) x 156 157 struct ce_int_assignment { 158 uint8_t msi_idx[NUM_CE_AVAILABLE]; 159 }; 160 161 struct hif_ce_stats { 162 int hif_pipe_no_resrc_count; 163 int ce_ring_delta_fail_count; 164 }; 165 166 #ifdef HIF_DETECTION_LATENCY_ENABLE 167 struct hif_latency_detect { 168 qdf_timer_t detect_latency_timer; 169 uint32_t detect_latency_timer_timeout; 170 bool is_timer_started; 171 bool enable_detection; 172 /* threshold when stall happens */ 173 uint32_t detect_latency_threshold; 174 int ce2_tasklet_sched_cpuid; 175 qdf_time_t ce2_tasklet_sched_time; 176 qdf_time_t ce2_tasklet_exec_time; 177 qdf_time_t credit_request_time; 178 qdf_time_t credit_report_time; 179 }; 180 #endif 181 182 /* 183 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 184 * for defined here 185 */ 186 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 187 188 #define HIF_CE_MAX_LATEST_HIST 2 189 190 struct latest_evt_history { 191 uint64_t irq_entry_ts; 192 uint64_t bh_entry_ts; 193 uint64_t bh_resched_ts; 194 uint64_t bh_exit_ts; 195 uint64_t bh_work_ts; 196 int cpu_id; 197 uint32_t ring_hp; 198 uint32_t ring_tp; 199 }; 200 201 struct ce_desc_hist { 202 qdf_atomic_t history_index[CE_COUNT_MAX]; 203 uint8_t ce_id_hist_map[CE_COUNT_MAX]; 204 bool enable[CE_COUNT_MAX]; 205 bool data_enable[CE_COUNT_MAX]; 206 qdf_mutex_t ce_dbg_datamem_lock[CE_COUNT_MAX]; 207 uint32_t hist_index; 208 uint32_t hist_id; 209 void *hist_ev[CE_COUNT_MAX]; 210 struct latest_evt_history latest_evt[HIF_CE_MAX_LATEST_HIST]; 211 }; 212 213 void hif_record_latest_evt(struct ce_desc_hist *ce_hist, 214 uint8_t type, 215 int ce_id, uint64_t time, 216 uint32_t hp, uint32_t tp); 217 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 218 219 /** 220 * struct hif_cfg() - store ini config parameters in hif layer 221 * @ce_status_ring_timer_threshold: ce status ring timer threshold 222 * @ce_status_ring_batch_count_threshold: ce status ring batch count threshold 223 */ 224 struct hif_cfg { 225 uint16_t ce_status_ring_timer_threshold; 226 uint8_t ce_status_ring_batch_count_threshold; 227 }; 228 229 #ifdef DP_UMAC_HW_RESET_SUPPORT 230 /** 231 * struct hif_umac_reset_ctx - UMAC HW reset context at HIF layer 232 * @intr_tq: Tasklet structure 233 * @cb_handler: Callback handler 234 * @cb_ctx: Argument to be passed to @cb_handler 235 * @os_irq: Interrupt number for this IRQ 236 * @irq_configured: Whether the IRQ has been configured 237 */ 238 struct hif_umac_reset_ctx { 239 struct tasklet_struct intr_tq; 240 int (*cb_handler)(void *cb_ctx); 241 void *cb_ctx; 242 uint32_t os_irq; 243 bool irq_configured; 244 }; 245 #endif 246 247 struct hif_softc { 248 struct hif_opaque_softc osc; 249 struct hif_config_info hif_config; 250 struct hif_target_info target_info; 251 void __iomem *mem; 252 void __iomem *mem_ce; 253 void __iomem *mem_cmem; 254 enum qdf_bus_type bus_type; 255 struct hif_bus_ops bus_ops; 256 void *ce_id_to_state[CE_COUNT_MAX]; 257 qdf_device_t qdf_dev; 258 bool hif_init_done; 259 bool request_irq_done; 260 bool ext_grp_irq_configured; 261 bool free_irq_done; 262 uint8_t ce_latency_stats; 263 /* Packet statistics */ 264 struct hif_ce_stats pkt_stats; 265 enum hif_target_status target_status; 266 uint64_t event_enable_mask; 267 268 struct targetdef_s *targetdef; 269 struct ce_reg_def *target_ce_def; 270 struct hostdef_s *hostdef; 271 struct host_shadow_regs_s *host_shadow_regs; 272 273 bool recovery; 274 bool notice_send; 275 bool per_ce_irq; 276 uint32_t ce_irq_summary; 277 /* No of copy engines supported */ 278 unsigned int ce_count; 279 struct ce_int_assignment *int_assignment; 280 atomic_t active_tasklet_cnt; 281 atomic_t active_grp_tasklet_cnt; 282 atomic_t link_suspended; 283 uint32_t *vaddr_rri_on_ddr; 284 qdf_dma_addr_t paddr_rri_on_ddr; 285 #ifdef CONFIG_BYPASS_QMI 286 uint32_t *vaddr_qmi_bypass; 287 qdf_dma_addr_t paddr_qmi_bypass; 288 #endif 289 int linkstate_vote; 290 bool fastpath_mode_on; 291 atomic_t tasklet_from_intr; 292 int htc_htt_tx_endpoint; 293 qdf_dma_addr_t mem_pa; 294 bool athdiag_procfs_inited; 295 #ifdef FEATURE_NAPI 296 struct qca_napi_data napi_data; 297 #endif /* FEATURE_NAPI */ 298 /* stores ce_service_max_yield_time in ns */ 299 unsigned long long ce_service_max_yield_time; 300 uint8_t ce_service_max_rx_ind_flush; 301 struct hif_driver_state_callbacks callbacks; 302 uint32_t hif_con_param; 303 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 304 uint32_t nss_wifi_ol_mode; 305 #endif 306 void *hal_soc; 307 struct hif_ut_suspend_context ut_suspend_ctx; 308 uint32_t hif_attribute; 309 int wake_irq; 310 int disable_wake_irq; 311 hif_pm_wake_irq_type wake_irq_type; 312 void (*initial_wakeup_cb)(void *); 313 void *initial_wakeup_priv; 314 #ifdef REMOVE_PKT_LOG 315 /* Handle to pktlog device */ 316 void *pktlog_dev; 317 #endif 318 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 319 /* Pointer to the srng event history */ 320 struct hif_event_history *evt_hist[HIF_NUM_INT_CONTEXTS]; 321 #endif 322 323 /* 324 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 325 * for defined here 326 */ 327 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 328 struct ce_desc_hist hif_ce_desc_hist; 329 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 330 #ifdef IPA_OFFLOAD 331 qdf_shared_mem_t *ipa_ce_ring; 332 #endif 333 struct hif_cfg ini_cfg; 334 #ifdef HIF_CE_LOG_INFO 335 qdf_notif_block hif_recovery_notifier; 336 #endif 337 #ifdef HIF_CPU_PERF_AFFINE_MASK 338 /* The CPU hotplug event registration handle */ 339 struct qdf_cpuhp_handler *cpuhp_event_handle; 340 #endif 341 uint32_t irq_unlazy_disable; 342 /* Should the unlzay support for interrupt delivery be disabled */ 343 /* Flag to indicate whether bus is suspended */ 344 bool bus_suspended; 345 bool pktlog_init; 346 #ifdef FEATURE_RUNTIME_PM 347 /* Variable to track the link state change in RTPM */ 348 qdf_atomic_t pm_link_state; 349 #endif 350 #ifdef HIF_DETECTION_LATENCY_ENABLE 351 struct hif_latency_detect latency_detect; 352 #endif 353 #ifdef FEATURE_RUNTIME_PM 354 qdf_runtime_lock_t prevent_linkdown_lock; 355 #endif 356 #ifdef SYSTEM_PM_CHECK 357 qdf_atomic_t sys_pm_state; 358 #endif 359 #if defined(HIF_IPCI) && defined(FEATURE_HAL_DELAYED_REG_WRITE) 360 qdf_atomic_t dp_ep_vote_access; 361 qdf_atomic_t ep_vote_access; 362 #endif 363 /* CMEM address target reserved for host usage */ 364 uint64_t cmem_start; 365 /* CMEM size target reserved */ 366 uint64_t cmem_size; 367 #ifdef DP_UMAC_HW_RESET_SUPPORT 368 struct hif_umac_reset_ctx umac_reset_ctx; 369 #endif 370 }; 371 372 static inline 373 void *hif_get_hal_handle(struct hif_opaque_softc *hif_hdl) 374 { 375 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 376 377 if (!sc) 378 return NULL; 379 380 return sc->hal_soc; 381 } 382 383 /** 384 * hif_get_cmem_info() - get CMEM address and size from HIF handle 385 * @hif_hdl: HIF handle pointer 386 * @cmem_start: pointer for CMEM address 387 * @cmem_size: pointer for CMEM size 388 * 389 * Return: None. 390 */ 391 static inline 392 void hif_get_cmem_info(struct hif_opaque_softc *hif_hdl, 393 uint64_t *cmem_start, 394 uint64_t *cmem_size) 395 { 396 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 397 398 *cmem_start = sc->cmem_start; 399 *cmem_size = sc->cmem_size; 400 } 401 402 /** 403 * hif_get_num_active_tasklets() - get the number of active 404 * tasklets pending to be completed. 405 * @scn: HIF context 406 * 407 * Returns: the number of tasklets which are active 408 */ 409 static inline int hif_get_num_active_tasklets(struct hif_softc *scn) 410 { 411 return qdf_atomic_read(&scn->active_tasklet_cnt); 412 } 413 414 /** 415 * Max waiting time during Runtime PM suspend to finish all 416 * the tasks. This is in the multiple of 10ms. 417 */ 418 #define HIF_TASK_DRAIN_WAIT_CNT 25 419 420 /** 421 * hif_try_complete_tasks() - Try to complete all the pending tasks 422 * @scn: HIF context 423 * 424 * Try to complete all the pending datapath tasks, i.e. tasklets, 425 * DP group tasklets and works which are queued, in a given time 426 * slot. 427 * 428 * Returns: QDF_STATUS_SUCCESS if all the tasks were completed 429 * QDF error code, if the time slot exhausted 430 */ 431 QDF_STATUS hif_try_complete_tasks(struct hif_softc *scn); 432 433 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 434 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 435 { 436 return !!(sc->nss_wifi_ol_mode); 437 } 438 #else 439 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 440 { 441 return false; 442 } 443 #endif 444 445 static inline uint8_t hif_is_attribute_set(struct hif_softc *sc, 446 uint32_t hif_attrib) 447 { 448 return sc->hif_attribute == hif_attrib; 449 } 450 451 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 452 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 453 { 454 struct hif_softc *scn = (struct hif_softc *)hif_handle; 455 456 scn->event_enable_mask = HIF_EVENT_HIST_ENABLE_MASK; 457 } 458 #else 459 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 460 { 461 } 462 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 463 464 A_target_id_t hif_get_target_id(struct hif_softc *scn); 465 void hif_dump_pipe_debug_count(struct hif_softc *scn); 466 void hif_display_bus_stats(struct hif_opaque_softc *scn); 467 void hif_clear_bus_stats(struct hif_opaque_softc *scn); 468 bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count); 469 void hif_shutdown_device(struct hif_opaque_softc *hif_ctx); 470 int hif_bus_configure(struct hif_softc *scn); 471 void hif_cancel_deferred_target_sleep(struct hif_softc *scn); 472 int hif_config_ce(struct hif_softc *scn); 473 int hif_config_ce_pktlog(struct hif_opaque_softc *hif_ctx); 474 int hif_config_ce_by_id(struct hif_softc *scn, int pipe_num); 475 void hif_unconfig_ce(struct hif_softc *scn); 476 void hif_ce_prepare_config(struct hif_softc *scn); 477 QDF_STATUS hif_ce_open(struct hif_softc *scn); 478 void hif_ce_close(struct hif_softc *scn); 479 int athdiag_procfs_init(void *scn); 480 void athdiag_procfs_remove(void); 481 /* routine to modify the initial buffer count to be allocated on an os 482 * platform basis. Platform owner will need to modify this as needed 483 */ 484 qdf_size_t init_buffer_count(qdf_size_t maxSize); 485 486 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg); 487 int hif_get_device_type(uint32_t device_id, 488 uint32_t revision_id, 489 uint32_t *hif_type, uint32_t *target_type); 490 /*These functions are exposed to HDD*/ 491 void hif_nointrs(struct hif_softc *scn); 492 void hif_bus_close(struct hif_softc *ol_sc); 493 QDF_STATUS hif_bus_open(struct hif_softc *ol_sc, 494 enum qdf_bus_type bus_type); 495 QDF_STATUS hif_enable_bus(struct hif_softc *ol_sc, struct device *dev, 496 void *bdev, const struct hif_bus_id *bid, enum hif_enable_type type); 497 void hif_disable_bus(struct hif_softc *scn); 498 void hif_bus_prevent_linkdown(struct hif_softc *scn, bool flag); 499 int hif_bus_get_context_size(enum qdf_bus_type bus_type); 500 void hif_read_phy_mem_base(struct hif_softc *scn, qdf_dma_addr_t *bar_value); 501 uint32_t hif_get_conparam(struct hif_softc *scn); 502 struct hif_driver_state_callbacks *hif_get_callbacks_handle( 503 struct hif_softc *scn); 504 bool hif_is_driver_unloading(struct hif_softc *scn); 505 bool hif_is_load_or_unload_in_progress(struct hif_softc *scn); 506 bool hif_is_recovery_in_progress(struct hif_softc *scn); 507 bool hif_is_target_ready(struct hif_softc *scn); 508 509 /** 510 * hif_get_bandwidth_level() - API to get the current bandwidth level 511 * @scn: HIF Context 512 * 513 * Return: PLD bandwidth level 514 */ 515 int hif_get_bandwidth_level(struct hif_opaque_softc *hif_handle); 516 517 void hif_wlan_disable(struct hif_softc *scn); 518 int hif_target_sleep_state_adjust(struct hif_softc *scn, 519 bool sleep_ok, 520 bool wait_for_it); 521 522 #ifdef DP_MEM_PRE_ALLOC 523 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 524 qdf_size_t size, 525 qdf_dma_addr_t *paddr, 526 uint32_t ring_type, 527 uint8_t *is_mem_prealloc); 528 529 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 530 qdf_size_t size, 531 void *vaddr, 532 qdf_dma_addr_t paddr, 533 qdf_dma_context_t memctx, 534 uint8_t is_mem_prealloc); 535 #else 536 static inline 537 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 538 qdf_size_t size, 539 qdf_dma_addr_t *paddr, 540 uint32_t ring_type, 541 uint8_t *is_mem_prealloc) 542 { 543 return qdf_mem_alloc_consistent(scn->qdf_dev, 544 scn->qdf_dev->dev, 545 size, 546 paddr); 547 } 548 549 static inline 550 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 551 qdf_size_t size, 552 void *vaddr, 553 qdf_dma_addr_t paddr, 554 qdf_dma_context_t memctx, 555 uint8_t is_mem_prealloc) 556 { 557 return qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 558 size, vaddr, paddr, memctx); 559 } 560 #endif 561 562 /** 563 * hif_get_rx_ctx_id() - Returns NAPI instance ID based on CE ID 564 * @ctx_id: Rx CE context ID 565 * @hif_hdl: HIF Context 566 * 567 * Return: Rx instance ID 568 */ 569 int hif_get_rx_ctx_id(int ctx_id, struct hif_opaque_softc *hif_hdl); 570 void hif_ramdump_handler(struct hif_opaque_softc *scn); 571 #ifdef HIF_USB 572 void hif_usb_get_hw_info(struct hif_softc *scn); 573 void hif_usb_ramdump_handler(struct hif_opaque_softc *scn); 574 #else 575 static inline void hif_usb_get_hw_info(struct hif_softc *scn) {} 576 static inline void hif_usb_ramdump_handler(struct hif_opaque_softc *scn) {} 577 #endif 578 579 /** 580 * hif_wake_interrupt_handler() - interrupt handler for standalone wake irq 581 * @irq: the irq number that fired 582 * @context: the opaque pointer passed to request_irq() 583 * 584 * Return: an irq return type 585 */ 586 irqreturn_t hif_wake_interrupt_handler(int irq, void *context); 587 588 #ifdef HIF_SNOC 589 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc); 590 #else 591 static inline 592 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc) 593 { 594 return true; 595 } 596 #endif 597 598 #ifdef ADRASTEA_RRI_ON_DDR 599 void hif_uninit_rri_on_ddr(struct hif_softc *scn); 600 #else 601 static inline 602 void hif_uninit_rri_on_ddr(struct hif_softc *scn) {} 603 #endif 604 void hif_cleanup_static_buf_to_target(struct hif_softc *scn); 605 606 #ifdef FEATURE_RUNTIME_PM 607 /** 608 * hif_runtime_prevent_linkdown() - prevent or allow a runtime pm from occurring 609 * @scn: hif context 610 * @is_get: prevent linkdown if true otherwise allow 611 * 612 * this api should only be called as part of bus prevent linkdown 613 */ 614 void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get); 615 #else 616 static inline 617 void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get) 618 { 619 } 620 #endif 621 622 #endif /* __HIF_MAIN_H__ */ 623