1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * NB: Inappropriate references to "HTC" are used in this (and other) 22 * HIF implementations. HTC is typically the calling layer, but it 23 * theoretically could be some alternative. 24 */ 25 26 /* 27 * This holds all state needed to process a pending send/recv interrupt. 28 * The information is saved here as soon as the interrupt occurs (thus 29 * allowing the underlying CE to re-use the ring descriptor). The 30 * information here is eventually processed by a completion processing 31 * thread. 32 */ 33 34 #ifndef __HIF_MAIN_H__ 35 #define __HIF_MAIN_H__ 36 37 #include <qdf_atomic.h> /* qdf_atomic_read */ 38 #include "qdf_lock.h" 39 #include "cepci.h" 40 #include "hif.h" 41 #include "multibus.h" 42 #include "hif_unit_test_suspend_i.h" 43 #ifdef HIF_CE_LOG_INFO 44 #include "qdf_notifier.h" 45 #endif 46 47 #define HIF_MIN_SLEEP_INACTIVITY_TIME_MS 50 48 #define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60 49 50 #define HIF_MAX_BUDGET 0xFFFF 51 52 #define HIF_STATS_INC(_handle, _field, _delta) \ 53 { \ 54 (_handle)->stats._field += _delta; \ 55 } 56 57 /* 58 * This macro implementation is exposed for efficiency only. 59 * The implementation may change and callers should 60 * consider the targid to be a completely opaque handle. 61 */ 62 #define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid))) 63 64 #ifdef QCA_WIFI_3_0 65 #define DISABLE_L1SS_STATES 1 66 #endif 67 68 #define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES 69 70 #ifdef QCA_WIFI_3_0_ADRASTEA 71 #define ADRASTEA_BU 1 72 #else 73 #define ADRASTEA_BU 0 74 #endif 75 76 #ifdef QCA_WIFI_3_0 77 #define HAS_FW_INDICATOR 0 78 #else 79 #define HAS_FW_INDICATOR 1 80 #endif 81 82 83 #define AR9888_DEVICE_ID (0x003c) 84 #define AR6320_DEVICE_ID (0x003e) 85 #define AR6320_FW_1_1 (0x11) 86 #define AR6320_FW_1_3 (0x13) 87 #define AR6320_FW_2_0 (0x20) 88 #define AR6320_FW_3_0 (0x30) 89 #define AR6320_FW_3_2 (0x32) 90 #define QCA6290_EMULATION_DEVICE_ID (0xabcd) 91 #define QCA6290_DEVICE_ID (0x1100) 92 #define QCN9000_DEVICE_ID (0x1104) 93 #define QCN9224_DEVICE_ID (0x1109) 94 #define QCN6122_DEVICE_ID (0xFFFB) 95 #define QCA6390_EMULATION_DEVICE_ID (0x0108) 96 #define QCA6390_DEVICE_ID (0x1101) 97 /* TODO: change IDs for HastingsPrime */ 98 #define QCA6490_EMULATION_DEVICE_ID (0x010a) 99 #define QCA6490_DEVICE_ID (0x1103) 100 101 /* TODO: change IDs for Moselle */ 102 #define QCA6750_EMULATION_DEVICE_ID (0x010c) 103 #define QCA6750_DEVICE_ID (0x1105) 104 105 /* TODO: change IDs for Hamilton */ 106 #define KIWI_DEVICE_ID (0x1107) 107 108 #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021) 109 #define AR9887_DEVICE_ID (0x0050) 110 #define AR900B_DEVICE_ID (0x0040) 111 #define QCA9984_DEVICE_ID (0x0046) 112 #define QCA9888_DEVICE_ID (0x0056) 113 #ifndef IPQ4019_DEVICE_ID 114 #define IPQ4019_DEVICE_ID (0x12ef) 115 #endif 116 #define QCA8074_DEVICE_ID (0xffff) /* Todo: replace this with 117 actual number once available. 118 currently defining this to 0xffff for 119 emulation purpose */ 120 #define QCA8074V2_DEVICE_ID (0xfffe) /* Todo: replace this with actual number */ 121 #define QCA6018_DEVICE_ID (0xfffd) /* Todo: replace this with actual number */ 122 #define QCA5018_DEVICE_ID (0xfffc) /* Todo: replace this with actual number */ 123 #define QCA9574_DEVICE_ID (0xfffa) 124 /* Genoa */ 125 #define QCN7605_DEVICE_ID (0x1102) /* Genoa PCIe device ID*/ 126 #define QCN7605_COMPOSITE (0x9901) 127 #define QCN7605_STANDALONE (0x9900) 128 #define QCN7605_STANDALONE_V2 (0x9902) 129 #define QCN7605_COMPOSITE_V2 (0x9903) 130 131 #define RUMIM2M_DEVICE_ID_NODE0 0xabc0 132 #define RUMIM2M_DEVICE_ID_NODE1 0xabc1 133 #define RUMIM2M_DEVICE_ID_NODE2 0xabc2 134 #define RUMIM2M_DEVICE_ID_NODE3 0xabc3 135 #define RUMIM2M_DEVICE_ID_NODE4 0xaa10 136 #define RUMIM2M_DEVICE_ID_NODE5 0xaa11 137 138 #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn) 139 #define HIF_GET_IPCI_SOFTC(scn) ((struct hif_ipci_softc *)scn) 140 #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn) 141 #define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn) 142 #define HIF_GET_USB_SOFTC(scn) ((struct hif_usb_softc *)scn) 143 #define HIF_GET_USB_DEVICE(scn) ((struct HIF_DEVICE_USB *)scn) 144 #define HIF_GET_SOFTC(scn) ((struct hif_softc *)scn) 145 #define GET_HIF_OPAQUE_HDL(scn) ((struct hif_opaque_softc *)scn) 146 147 #ifdef QCA_WIFI_QCN9224 148 #define NUM_CE_AVAILABLE 16 149 #else 150 #define NUM_CE_AVAILABLE 12 151 #endif 152 /* Add 1 here to store default configuration in index 0 */ 153 #define NUM_CE_CONTEXT (NUM_CE_AVAILABLE + 1) 154 155 #define CE_INTERRUPT_IDX(x) x 156 157 struct ce_int_assignment { 158 uint8_t msi_idx[NUM_CE_AVAILABLE]; 159 }; 160 161 struct hif_ce_stats { 162 int hif_pipe_no_resrc_count; 163 int ce_ring_delta_fail_count; 164 }; 165 166 #ifdef HIF_DETECTION_LATENCY_ENABLE 167 struct hif_latency_detect { 168 qdf_timer_t detect_latency_timer; 169 uint32_t detect_latency_timer_timeout; 170 bool is_timer_started; 171 bool enable_detection; 172 /* threshold when stall happens */ 173 uint32_t detect_latency_threshold; 174 int ce2_tasklet_sched_cpuid; 175 qdf_time_t ce2_tasklet_sched_time; 176 qdf_time_t ce2_tasklet_exec_time; 177 qdf_time_t credit_request_time; 178 qdf_time_t credit_report_time; 179 }; 180 #endif 181 182 /* 183 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 184 * for defined here 185 */ 186 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 187 struct ce_desc_hist { 188 qdf_atomic_t history_index[CE_COUNT_MAX]; 189 bool enable[CE_COUNT_MAX]; 190 bool data_enable[CE_COUNT_MAX]; 191 qdf_mutex_t ce_dbg_datamem_lock[CE_COUNT_MAX]; 192 uint32_t hist_index; 193 uint32_t hist_id; 194 void *hist_ev[CE_COUNT_MAX]; 195 }; 196 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 197 198 /** 199 * struct hif_cfg() - store ini config parameters in hif layer 200 * @ce_status_ring_timer_threshold: ce status ring timer threshold 201 * @ce_status_ring_batch_count_threshold: ce status ring batch count threshold 202 */ 203 struct hif_cfg { 204 uint16_t ce_status_ring_timer_threshold; 205 uint8_t ce_status_ring_batch_count_threshold; 206 }; 207 208 struct hif_softc { 209 struct hif_opaque_softc osc; 210 struct hif_config_info hif_config; 211 struct hif_target_info target_info; 212 void __iomem *mem; 213 void __iomem *mem_ce; 214 enum qdf_bus_type bus_type; 215 struct hif_bus_ops bus_ops; 216 void *ce_id_to_state[CE_COUNT_MAX]; 217 qdf_device_t qdf_dev; 218 bool hif_init_done; 219 bool request_irq_done; 220 bool ext_grp_irq_configured; 221 bool free_irq_done; 222 uint8_t ce_latency_stats; 223 /* Packet statistics */ 224 struct hif_ce_stats pkt_stats; 225 enum hif_target_status target_status; 226 uint64_t event_enable_mask; 227 228 struct targetdef_s *targetdef; 229 struct ce_reg_def *target_ce_def; 230 struct hostdef_s *hostdef; 231 struct host_shadow_regs_s *host_shadow_regs; 232 233 bool recovery; 234 bool notice_send; 235 bool per_ce_irq; 236 uint32_t ce_irq_summary; 237 /* No of copy engines supported */ 238 unsigned int ce_count; 239 struct ce_int_assignment *int_assignment; 240 atomic_t active_tasklet_cnt; 241 atomic_t active_grp_tasklet_cnt; 242 atomic_t link_suspended; 243 uint32_t *vaddr_rri_on_ddr; 244 qdf_dma_addr_t paddr_rri_on_ddr; 245 #ifdef CONFIG_BYPASS_QMI 246 uint32_t *vaddr_qmi_bypass; 247 qdf_dma_addr_t paddr_qmi_bypass; 248 #endif 249 int linkstate_vote; 250 bool fastpath_mode_on; 251 atomic_t tasklet_from_intr; 252 int htc_htt_tx_endpoint; 253 qdf_dma_addr_t mem_pa; 254 bool athdiag_procfs_inited; 255 #ifdef FEATURE_NAPI 256 struct qca_napi_data napi_data; 257 #endif /* FEATURE_NAPI */ 258 /* stores ce_service_max_yield_time in ns */ 259 unsigned long long ce_service_max_yield_time; 260 uint8_t ce_service_max_rx_ind_flush; 261 struct hif_driver_state_callbacks callbacks; 262 uint32_t hif_con_param; 263 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 264 uint32_t nss_wifi_ol_mode; 265 #endif 266 void *hal_soc; 267 struct hif_ut_suspend_context ut_suspend_ctx; 268 uint32_t hif_attribute; 269 int wake_irq; 270 int disable_wake_irq; 271 hif_pm_wake_irq_type wake_irq_type; 272 void (*initial_wakeup_cb)(void *); 273 void *initial_wakeup_priv; 274 #ifdef REMOVE_PKT_LOG 275 /* Handle to pktlog device */ 276 void *pktlog_dev; 277 #endif 278 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 279 /* Pointer to the srng event history */ 280 struct hif_event_history *evt_hist[HIF_NUM_INT_CONTEXTS]; 281 #endif 282 283 /* 284 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 285 * for defined here 286 */ 287 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 288 struct ce_desc_hist hif_ce_desc_hist; 289 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 290 #ifdef IPA_OFFLOAD 291 qdf_shared_mem_t *ipa_ce_ring; 292 #endif 293 struct hif_cfg ini_cfg; 294 #ifdef HIF_CE_LOG_INFO 295 qdf_notif_block hif_recovery_notifier; 296 #endif 297 #ifdef HIF_CPU_PERF_AFFINE_MASK 298 /* The CPU hotplug event registration handle */ 299 struct qdf_cpuhp_handler *cpuhp_event_handle; 300 #endif 301 uint32_t irq_unlazy_disable; 302 /* Should the unlzay support for interrupt delivery be disabled */ 303 /* Flag to indicate whether bus is suspended */ 304 bool bus_suspended; 305 bool pktlog_init; 306 #ifdef FEATURE_RUNTIME_PM 307 /* Variable to track the link state change in RTPM */ 308 qdf_atomic_t pm_link_state; 309 #endif 310 #ifdef HIF_DETECTION_LATENCY_ENABLE 311 struct hif_latency_detect latency_detect; 312 #endif 313 #ifdef SYSTEM_PM_CHECK 314 qdf_atomic_t sys_pm_state; 315 #endif 316 #if defined(HIF_IPCI) && defined(FEATURE_HAL_DELAYED_REG_WRITE) 317 qdf_atomic_t dp_ep_vote_access; 318 qdf_atomic_t ep_vote_access; 319 #endif 320 /* CMEM address target reserved for host usage */ 321 uint64_t cmem_start; 322 /* CMEM size target reserved */ 323 uint64_t cmem_size; 324 }; 325 326 static inline 327 void *hif_get_hal_handle(struct hif_opaque_softc *hif_hdl) 328 { 329 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 330 331 if (!sc) 332 return NULL; 333 334 return sc->hal_soc; 335 } 336 337 /** 338 * hif_get_cmem_info() - get CMEM address and size from HIF handle 339 * @hif_hdl: HIF handle pointer 340 * @cmem_start: pointer for CMEM address 341 * @cmem_size: pointer for CMEM size 342 * 343 * Return: None. 344 */ 345 static inline 346 void hif_get_cmem_info(struct hif_opaque_softc *hif_hdl, 347 uint64_t *cmem_start, 348 uint64_t *cmem_size) 349 { 350 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 351 352 *cmem_start = sc->cmem_start; 353 *cmem_size = sc->cmem_size; 354 } 355 356 /** 357 * hif_get_num_active_tasklets() - get the number of active 358 * tasklets pending to be completed. 359 * @scn: HIF context 360 * 361 * Returns: the number of tasklets which are active 362 */ 363 static inline int hif_get_num_active_tasklets(struct hif_softc *scn) 364 { 365 return qdf_atomic_read(&scn->active_tasklet_cnt); 366 } 367 368 /** 369 * Max waiting time during Runtime PM suspend to finish all 370 * the tasks. This is in the multiple of 10ms. 371 */ 372 #define HIF_TASK_DRAIN_WAIT_CNT 25 373 374 /** 375 * hif_try_complete_tasks() - Try to complete all the pending tasks 376 * @scn: HIF context 377 * 378 * Try to complete all the pending datapath tasks, i.e. tasklets, 379 * DP group tasklets and works which are queued, in a given time 380 * slot. 381 * 382 * Returns: QDF_STATUS_SUCCESS if all the tasks were completed 383 * QDF error code, if the time slot exhausted 384 */ 385 QDF_STATUS hif_try_complete_tasks(struct hif_softc *scn); 386 387 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 388 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 389 { 390 return !!(sc->nss_wifi_ol_mode); 391 } 392 #else 393 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 394 { 395 return false; 396 } 397 #endif 398 399 static inline uint8_t hif_is_attribute_set(struct hif_softc *sc, 400 uint32_t hif_attrib) 401 { 402 return sc->hif_attribute == hif_attrib; 403 } 404 405 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 406 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 407 { 408 struct hif_softc *scn = (struct hif_softc *)hif_handle; 409 410 scn->event_enable_mask = HIF_EVENT_HIST_ENABLE_MASK; 411 } 412 #else 413 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 414 { 415 } 416 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 417 418 A_target_id_t hif_get_target_id(struct hif_softc *scn); 419 void hif_dump_pipe_debug_count(struct hif_softc *scn); 420 void hif_display_bus_stats(struct hif_opaque_softc *scn); 421 void hif_clear_bus_stats(struct hif_opaque_softc *scn); 422 bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count); 423 void hif_shutdown_device(struct hif_opaque_softc *hif_ctx); 424 int hif_bus_configure(struct hif_softc *scn); 425 void hif_cancel_deferred_target_sleep(struct hif_softc *scn); 426 int hif_config_ce(struct hif_softc *scn); 427 int hif_config_ce_pktlog(struct hif_opaque_softc *hif_ctx); 428 int hif_config_ce_by_id(struct hif_softc *scn, int pipe_num); 429 void hif_unconfig_ce(struct hif_softc *scn); 430 void hif_ce_prepare_config(struct hif_softc *scn); 431 QDF_STATUS hif_ce_open(struct hif_softc *scn); 432 void hif_ce_close(struct hif_softc *scn); 433 int athdiag_procfs_init(void *scn); 434 void athdiag_procfs_remove(void); 435 /* routine to modify the initial buffer count to be allocated on an os 436 * platform basis. Platform owner will need to modify this as needed 437 */ 438 qdf_size_t init_buffer_count(qdf_size_t maxSize); 439 440 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg); 441 int hif_get_device_type(uint32_t device_id, 442 uint32_t revision_id, 443 uint32_t *hif_type, uint32_t *target_type); 444 /*These functions are exposed to HDD*/ 445 void hif_nointrs(struct hif_softc *scn); 446 void hif_bus_close(struct hif_softc *ol_sc); 447 QDF_STATUS hif_bus_open(struct hif_softc *ol_sc, 448 enum qdf_bus_type bus_type); 449 QDF_STATUS hif_enable_bus(struct hif_softc *ol_sc, struct device *dev, 450 void *bdev, const struct hif_bus_id *bid, enum hif_enable_type type); 451 void hif_disable_bus(struct hif_softc *scn); 452 #ifdef FEATURE_RUNTIME_PM 453 struct hif_runtime_pm_ctx *hif_bus_get_rpm_ctx(struct hif_softc *hif_sc); 454 struct device *hif_bus_get_dev(struct hif_softc *hif_sc); 455 #endif 456 void hif_bus_prevent_linkdown(struct hif_softc *scn, bool flag); 457 int hif_bus_get_context_size(enum qdf_bus_type bus_type); 458 void hif_read_phy_mem_base(struct hif_softc *scn, qdf_dma_addr_t *bar_value); 459 uint32_t hif_get_conparam(struct hif_softc *scn); 460 struct hif_driver_state_callbacks *hif_get_callbacks_handle( 461 struct hif_softc *scn); 462 bool hif_is_driver_unloading(struct hif_softc *scn); 463 bool hif_is_load_or_unload_in_progress(struct hif_softc *scn); 464 bool hif_is_recovery_in_progress(struct hif_softc *scn); 465 bool hif_is_target_ready(struct hif_softc *scn); 466 467 /** 468 * hif_get_bandwidth_level() - API to get the current bandwidth level 469 * @scn: HIF Context 470 * 471 * Return: PLD bandwidth level 472 */ 473 int hif_get_bandwidth_level(struct hif_opaque_softc *hif_handle); 474 475 void hif_wlan_disable(struct hif_softc *scn); 476 int hif_target_sleep_state_adjust(struct hif_softc *scn, 477 bool sleep_ok, 478 bool wait_for_it); 479 480 #ifdef DP_MEM_PRE_ALLOC 481 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 482 qdf_size_t size, 483 qdf_dma_addr_t *paddr, 484 uint32_t ring_type, 485 uint8_t *is_mem_prealloc); 486 487 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 488 qdf_size_t size, 489 void *vaddr, 490 qdf_dma_addr_t paddr, 491 qdf_dma_context_t memctx, 492 uint8_t is_mem_prealloc); 493 #else 494 static inline 495 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 496 qdf_size_t size, 497 qdf_dma_addr_t *paddr, 498 uint32_t ring_type, 499 uint8_t *is_mem_prealloc) 500 { 501 return qdf_mem_alloc_consistent(scn->qdf_dev, 502 scn->qdf_dev->dev, 503 size, 504 paddr); 505 } 506 507 static inline 508 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 509 qdf_size_t size, 510 void *vaddr, 511 qdf_dma_addr_t paddr, 512 qdf_dma_context_t memctx, 513 uint8_t is_mem_prealloc) 514 { 515 return qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 516 size, vaddr, paddr, memctx); 517 } 518 #endif 519 520 /** 521 * hif_get_rx_ctx_id() - Returns NAPI instance ID based on CE ID 522 * @ctx_id: Rx CE context ID 523 * @hif_hdl: HIF Context 524 * 525 * Return: Rx instance ID 526 */ 527 int hif_get_rx_ctx_id(int ctx_id, struct hif_opaque_softc *hif_hdl); 528 void hif_ramdump_handler(struct hif_opaque_softc *scn); 529 #ifdef HIF_USB 530 void hif_usb_get_hw_info(struct hif_softc *scn); 531 void hif_usb_ramdump_handler(struct hif_opaque_softc *scn); 532 #else 533 static inline void hif_usb_get_hw_info(struct hif_softc *scn) {} 534 static inline void hif_usb_ramdump_handler(struct hif_opaque_softc *scn) {} 535 #endif 536 537 /** 538 * hif_wake_interrupt_handler() - interrupt handler for standalone wake irq 539 * @irq: the irq number that fired 540 * @context: the opaque pointer passed to request_irq() 541 * 542 * Return: an irq return type 543 */ 544 irqreturn_t hif_wake_interrupt_handler(int irq, void *context); 545 546 #ifdef HIF_SNOC 547 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc); 548 #else 549 static inline 550 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc) 551 { 552 return true; 553 } 554 #endif 555 556 #ifdef ADRASTEA_RRI_ON_DDR 557 void hif_uninit_rri_on_ddr(struct hif_softc *scn); 558 #else 559 static inline 560 void hif_uninit_rri_on_ddr(struct hif_softc *scn) {} 561 #endif 562 void hif_cleanup_static_buf_to_target(struct hif_softc *scn); 563 #endif /* __HIF_MAIN_H__ */ 564