1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * NB: Inappropriate references to "HTC" are used in this (and other) 21 * HIF implementations. HTC is typically the calling layer, but it 22 * theoretically could be some alternative. 23 */ 24 25 /* 26 * This holds all state needed to process a pending send/recv interrupt. 27 * The information is saved here as soon as the interrupt occurs (thus 28 * allowing the underlying CE to re-use the ring descriptor). The 29 * information here is eventually processed by a completion processing 30 * thread. 31 */ 32 33 #ifndef __HIF_MAIN_H__ 34 #define __HIF_MAIN_H__ 35 36 #include <qdf_atomic.h> /* qdf_atomic_read */ 37 #include "qdf_lock.h" 38 #include "cepci.h" 39 #include "hif.h" 40 #include "multibus.h" 41 #include "hif_unit_test_suspend_i.h" 42 #ifdef HIF_CE_LOG_INFO 43 #include "qdf_notifier.h" 44 #endif 45 46 #define HIF_MIN_SLEEP_INACTIVITY_TIME_MS 50 47 #define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60 48 49 #define HIF_MAX_BUDGET 0xFFFF 50 51 #define HIF_STATS_INC(_handle, _field, _delta) \ 52 { \ 53 (_handle)->stats._field += _delta; \ 54 } 55 56 /* 57 * This macro implementation is exposed for efficiency only. 58 * The implementation may change and callers should 59 * consider the targid to be a completely opaque handle. 60 */ 61 #define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid))) 62 63 #ifdef QCA_WIFI_3_0 64 #define DISABLE_L1SS_STATES 1 65 #endif 66 67 #define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES 68 69 #ifdef QCA_WIFI_3_0_ADRASTEA 70 #define ADRASTEA_BU 1 71 #else 72 #define ADRASTEA_BU 0 73 #endif 74 75 #ifdef QCA_WIFI_3_0 76 #define HAS_FW_INDICATOR 0 77 #else 78 #define HAS_FW_INDICATOR 1 79 #endif 80 81 82 #define AR9888_DEVICE_ID (0x003c) 83 #define AR6320_DEVICE_ID (0x003e) 84 #define AR6320_FW_1_1 (0x11) 85 #define AR6320_FW_1_3 (0x13) 86 #define AR6320_FW_2_0 (0x20) 87 #define AR6320_FW_3_0 (0x30) 88 #define AR6320_FW_3_2 (0x32) 89 #define QCA6290_EMULATION_DEVICE_ID (0xabcd) 90 #define QCA6290_DEVICE_ID (0x1100) 91 #define QCN9000_DEVICE_ID (0x1104) 92 #define QCN9224_DEVICE_ID (0x1109) 93 #define QCN6122_DEVICE_ID (0xFFFB) 94 #define QCA6390_EMULATION_DEVICE_ID (0x0108) 95 #define QCA6390_DEVICE_ID (0x1101) 96 /* TODO: change IDs for HastingsPrime */ 97 #define QCA6490_EMULATION_DEVICE_ID (0x010a) 98 #define QCA6490_DEVICE_ID (0x1103) 99 100 /* TODO: change IDs for Moselle */ 101 #define QCA6750_EMULATION_DEVICE_ID (0x010c) 102 #define QCA6750_DEVICE_ID (0x1105) 103 104 /* TODO: change IDs for Hamilton */ 105 #define WCN7850_DEVICE_ID (0x1107) 106 107 #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021) 108 #define AR9887_DEVICE_ID (0x0050) 109 #define AR900B_DEVICE_ID (0x0040) 110 #define QCA9984_DEVICE_ID (0x0046) 111 #define QCA9888_DEVICE_ID (0x0056) 112 #ifndef IPQ4019_DEVICE_ID 113 #define IPQ4019_DEVICE_ID (0x12ef) 114 #endif 115 #define QCA8074_DEVICE_ID (0xffff) /* Todo: replace this with 116 actual number once available. 117 currently defining this to 0xffff for 118 emulation purpose */ 119 #define QCA8074V2_DEVICE_ID (0xfffe) /* Todo: replace this with actual number */ 120 #define QCA6018_DEVICE_ID (0xfffd) /* Todo: replace this with actual number */ 121 #define QCA5018_DEVICE_ID (0xfffc) /* Todo: replace this with actual number */ 122 #define QCA9574_DEVICE_ID (0xfffa) 123 /* Genoa */ 124 #define QCN7605_DEVICE_ID (0x1102) /* Genoa PCIe device ID*/ 125 #define QCN7605_COMPOSITE (0x9901) 126 #define QCN7605_STANDALONE (0x9900) 127 #define QCN7605_STANDALONE_V2 (0x9902) 128 #define QCN7605_COMPOSITE_V2 (0x9903) 129 130 #define RUMIM2M_DEVICE_ID_NODE0 0xabc0 131 #define RUMIM2M_DEVICE_ID_NODE1 0xabc1 132 #define RUMIM2M_DEVICE_ID_NODE2 0xabc2 133 #define RUMIM2M_DEVICE_ID_NODE3 0xabc3 134 #define RUMIM2M_DEVICE_ID_NODE4 0xaa10 135 #define RUMIM2M_DEVICE_ID_NODE5 0xaa11 136 137 #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn) 138 #define HIF_GET_IPCI_SOFTC(scn) ((struct hif_ipci_softc *)scn) 139 #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn) 140 #define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn) 141 #define HIF_GET_USB_SOFTC(scn) ((struct hif_usb_softc *)scn) 142 #define HIF_GET_USB_DEVICE(scn) ((struct HIF_DEVICE_USB *)scn) 143 #define HIF_GET_SOFTC(scn) ((struct hif_softc *)scn) 144 #define GET_HIF_OPAQUE_HDL(scn) ((struct hif_opaque_softc *)scn) 145 146 #ifdef QCA_WIFI_QCN9224 147 #define NUM_CE_AVAILABLE 16 148 #else 149 #define NUM_CE_AVAILABLE 12 150 #endif 151 /* Add 1 here to store default configuration in index 0 */ 152 #define NUM_CE_CONTEXT (NUM_CE_AVAILABLE + 1) 153 154 #define CE_INTERRUPT_IDX(x) x 155 156 struct ce_int_assignment { 157 uint8_t msi_idx[NUM_CE_AVAILABLE]; 158 }; 159 160 struct hif_ce_stats { 161 int hif_pipe_no_resrc_count; 162 int ce_ring_delta_fail_count; 163 }; 164 165 #ifdef HIF_DETECTION_LATENCY_ENABLE 166 struct hif_latency_detect { 167 qdf_timer_t detect_latency_timer; 168 uint32_t detect_latency_timer_timeout; 169 bool is_timer_started; 170 bool enable_detection; 171 /* threshold when stall happens */ 172 uint32_t detect_latency_threshold; 173 int ce2_tasklet_sched_cpuid; 174 qdf_time_t ce2_tasklet_sched_time; 175 qdf_time_t ce2_tasklet_exec_time; 176 qdf_time_t credit_request_time; 177 qdf_time_t credit_report_time; 178 }; 179 #endif 180 181 /* 182 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 183 * for defined here 184 */ 185 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 186 struct ce_desc_hist { 187 qdf_atomic_t history_index[CE_COUNT_MAX]; 188 uint32_t enable[CE_COUNT_MAX]; 189 bool data_enable[CE_COUNT_MAX]; 190 qdf_mutex_t ce_dbg_datamem_lock[CE_COUNT_MAX]; 191 uint32_t hist_index; 192 uint32_t hist_id; 193 void *hist_ev[CE_COUNT_MAX]; 194 }; 195 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 196 197 /** 198 * struct hif_cfg() - store ini config parameters in hif layer 199 * @ce_status_ring_timer_threshold: ce status ring timer threshold 200 * @ce_status_ring_batch_count_threshold: ce status ring batch count threshold 201 */ 202 struct hif_cfg { 203 uint16_t ce_status_ring_timer_threshold; 204 uint8_t ce_status_ring_batch_count_threshold; 205 }; 206 207 struct hif_softc { 208 struct hif_opaque_softc osc; 209 struct hif_config_info hif_config; 210 struct hif_target_info target_info; 211 void __iomem *mem; 212 void __iomem *mem_ce; 213 enum qdf_bus_type bus_type; 214 struct hif_bus_ops bus_ops; 215 void *ce_id_to_state[CE_COUNT_MAX]; 216 qdf_device_t qdf_dev; 217 bool hif_init_done; 218 bool request_irq_done; 219 bool ext_grp_irq_configured; 220 bool free_irq_done; 221 uint8_t ce_latency_stats; 222 /* Packet statistics */ 223 struct hif_ce_stats pkt_stats; 224 enum hif_target_status target_status; 225 uint64_t event_enable_mask; 226 227 struct targetdef_s *targetdef; 228 struct ce_reg_def *target_ce_def; 229 struct hostdef_s *hostdef; 230 struct host_shadow_regs_s *host_shadow_regs; 231 232 bool recovery; 233 bool notice_send; 234 bool per_ce_irq; 235 uint32_t ce_irq_summary; 236 /* No of copy engines supported */ 237 unsigned int ce_count; 238 struct ce_int_assignment *int_assignment; 239 atomic_t active_tasklet_cnt; 240 atomic_t active_grp_tasklet_cnt; 241 atomic_t link_suspended; 242 uint32_t *vaddr_rri_on_ddr; 243 qdf_dma_addr_t paddr_rri_on_ddr; 244 #ifdef CONFIG_BYPASS_QMI 245 uint32_t *vaddr_qmi_bypass; 246 qdf_dma_addr_t paddr_qmi_bypass; 247 #endif 248 int linkstate_vote; 249 bool fastpath_mode_on; 250 atomic_t tasklet_from_intr; 251 int htc_htt_tx_endpoint; 252 qdf_dma_addr_t mem_pa; 253 bool athdiag_procfs_inited; 254 #ifdef FEATURE_NAPI 255 struct qca_napi_data napi_data; 256 #endif /* FEATURE_NAPI */ 257 /* stores ce_service_max_yield_time in ns */ 258 unsigned long long ce_service_max_yield_time; 259 uint8_t ce_service_max_rx_ind_flush; 260 struct hif_driver_state_callbacks callbacks; 261 uint32_t hif_con_param; 262 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 263 uint32_t nss_wifi_ol_mode; 264 #endif 265 void *hal_soc; 266 struct hif_ut_suspend_context ut_suspend_ctx; 267 uint32_t hif_attribute; 268 int wake_irq; 269 int disable_wake_irq; 270 hif_pm_wake_irq_type wake_irq_type; 271 void (*initial_wakeup_cb)(void *); 272 void *initial_wakeup_priv; 273 #ifdef REMOVE_PKT_LOG 274 /* Handle to pktlog device */ 275 void *pktlog_dev; 276 #endif 277 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 278 /* Pointer to the srng event history */ 279 struct hif_event_history *evt_hist[HIF_NUM_INT_CONTEXTS]; 280 #endif 281 282 /* 283 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 284 * for defined here 285 */ 286 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 287 struct ce_desc_hist hif_ce_desc_hist; 288 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 289 #ifdef IPA_OFFLOAD 290 qdf_shared_mem_t *ipa_ce_ring; 291 #endif 292 struct hif_cfg ini_cfg; 293 #ifdef HIF_CE_LOG_INFO 294 qdf_notif_block hif_recovery_notifier; 295 #endif 296 #ifdef HIF_CPU_PERF_AFFINE_MASK 297 /* The CPU hotplug event registration handle */ 298 struct qdf_cpuhp_handler *cpuhp_event_handle; 299 #endif 300 uint32_t irq_unlazy_disable; 301 /* Should the unlzay support for interrupt delivery be disabled */ 302 /* Flag to indicate whether bus is suspended */ 303 bool bus_suspended; 304 bool pktlog_init; 305 #ifdef FEATURE_RUNTIME_PM 306 /* Variable to track the link state change in RTPM */ 307 qdf_atomic_t pm_link_state; 308 #endif 309 #ifdef HIF_DETECTION_LATENCY_ENABLE 310 struct hif_latency_detect latency_detect; 311 #endif 312 #ifdef SYSTEM_PM_CHECK 313 qdf_atomic_t sys_pm_state; 314 #endif 315 #if defined(HIF_IPCI) && defined(FEATURE_HAL_DELAYED_REG_WRITE) 316 qdf_atomic_t dp_ep_vote_access; 317 qdf_atomic_t ep_vote_access; 318 #endif 319 /* CMEM address target reserved for host usage */ 320 uint64_t cmem_start; 321 /* CMEM size target reserved */ 322 uint64_t cmem_size; 323 }; 324 325 static inline 326 void *hif_get_hal_handle(struct hif_opaque_softc *hif_hdl) 327 { 328 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 329 330 if (!sc) 331 return NULL; 332 333 return sc->hal_soc; 334 } 335 336 /** 337 * hif_get_cmem_info() - get CMEM address and size from HIF handle 338 * @hif_hdl: HIF handle pointer 339 * @cmem_start: pointer for CMEM address 340 * @cmem_size: pointer for CMEM size 341 * 342 * Return: None. 343 */ 344 static inline 345 void hif_get_cmem_info(struct hif_opaque_softc *hif_hdl, 346 uint64_t *cmem_start, 347 uint64_t *cmem_size) 348 { 349 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 350 351 *cmem_start = sc->cmem_start; 352 *cmem_size = sc->cmem_size; 353 } 354 355 /** 356 * hif_get_num_active_tasklets() - get the number of active 357 * tasklets pending to be completed. 358 * @scn: HIF context 359 * 360 * Returns: the number of tasklets which are active 361 */ 362 static inline int hif_get_num_active_tasklets(struct hif_softc *scn) 363 { 364 return qdf_atomic_read(&scn->active_tasklet_cnt); 365 } 366 367 /** 368 * Max waiting time during Runtime PM suspend to finish all 369 * the tasks. This is in the multiple of 10ms. 370 */ 371 #define HIF_TASK_DRAIN_WAIT_CNT 25 372 373 /** 374 * hif_try_complete_tasks() - Try to complete all the pending tasks 375 * @scn: HIF context 376 * 377 * Try to complete all the pending datapath tasks, i.e. tasklets, 378 * DP group tasklets and works which are queued, in a given time 379 * slot. 380 * 381 * Returns: QDF_STATUS_SUCCESS if all the tasks were completed 382 * QDF error code, if the time slot exhausted 383 */ 384 QDF_STATUS hif_try_complete_tasks(struct hif_softc *scn); 385 386 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 387 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 388 { 389 return !!(sc->nss_wifi_ol_mode); 390 } 391 #else 392 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 393 { 394 return false; 395 } 396 #endif 397 398 static inline uint8_t hif_is_attribute_set(struct hif_softc *sc, 399 uint32_t hif_attrib) 400 { 401 return sc->hif_attribute == hif_attrib; 402 } 403 404 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 405 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 406 { 407 struct hif_softc *scn = (struct hif_softc *)hif_handle; 408 409 scn->event_enable_mask = HIF_EVENT_HIST_ENABLE_MASK; 410 } 411 #else 412 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 413 { 414 } 415 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 416 417 A_target_id_t hif_get_target_id(struct hif_softc *scn); 418 void hif_dump_pipe_debug_count(struct hif_softc *scn); 419 void hif_display_bus_stats(struct hif_opaque_softc *scn); 420 void hif_clear_bus_stats(struct hif_opaque_softc *scn); 421 bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count); 422 void hif_shutdown_device(struct hif_opaque_softc *hif_ctx); 423 int hif_bus_configure(struct hif_softc *scn); 424 void hif_cancel_deferred_target_sleep(struct hif_softc *scn); 425 int hif_config_ce(struct hif_softc *scn); 426 int hif_config_ce_pktlog(struct hif_opaque_softc *hif_ctx); 427 int hif_config_ce_by_id(struct hif_softc *scn, int pipe_num); 428 void hif_unconfig_ce(struct hif_softc *scn); 429 void hif_ce_prepare_config(struct hif_softc *scn); 430 QDF_STATUS hif_ce_open(struct hif_softc *scn); 431 void hif_ce_close(struct hif_softc *scn); 432 int athdiag_procfs_init(void *scn); 433 void athdiag_procfs_remove(void); 434 /* routine to modify the initial buffer count to be allocated on an os 435 * platform basis. Platform owner will need to modify this as needed 436 */ 437 qdf_size_t init_buffer_count(qdf_size_t maxSize); 438 439 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg); 440 int hif_get_device_type(uint32_t device_id, 441 uint32_t revision_id, 442 uint32_t *hif_type, uint32_t *target_type); 443 /*These functions are exposed to HDD*/ 444 void hif_nointrs(struct hif_softc *scn); 445 void hif_bus_close(struct hif_softc *ol_sc); 446 QDF_STATUS hif_bus_open(struct hif_softc *ol_sc, 447 enum qdf_bus_type bus_type); 448 QDF_STATUS hif_enable_bus(struct hif_softc *ol_sc, struct device *dev, 449 void *bdev, const struct hif_bus_id *bid, enum hif_enable_type type); 450 void hif_disable_bus(struct hif_softc *scn); 451 #ifdef FEATURE_RUNTIME_PM 452 struct hif_runtime_pm_ctx *hif_bus_get_rpm_ctx(struct hif_softc *hif_sc); 453 struct device *hif_bus_get_dev(struct hif_softc *hif_sc); 454 #endif 455 void hif_bus_prevent_linkdown(struct hif_softc *scn, bool flag); 456 int hif_bus_get_context_size(enum qdf_bus_type bus_type); 457 void hif_read_phy_mem_base(struct hif_softc *scn, qdf_dma_addr_t *bar_value); 458 uint32_t hif_get_conparam(struct hif_softc *scn); 459 struct hif_driver_state_callbacks *hif_get_callbacks_handle( 460 struct hif_softc *scn); 461 bool hif_is_driver_unloading(struct hif_softc *scn); 462 bool hif_is_load_or_unload_in_progress(struct hif_softc *scn); 463 bool hif_is_recovery_in_progress(struct hif_softc *scn); 464 bool hif_is_target_ready(struct hif_softc *scn); 465 466 /** 467 * hif_get_bandwidth_level() - API to get the current bandwidth level 468 * @scn: HIF Context 469 * 470 * Return: PLD bandwidth level 471 */ 472 int hif_get_bandwidth_level(struct hif_opaque_softc *hif_handle); 473 474 void hif_wlan_disable(struct hif_softc *scn); 475 int hif_target_sleep_state_adjust(struct hif_softc *scn, 476 bool sleep_ok, 477 bool wait_for_it); 478 479 #ifdef DP_MEM_PRE_ALLOC 480 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 481 qdf_size_t size, 482 qdf_dma_addr_t *paddr, 483 uint32_t ring_type, 484 uint8_t *is_mem_prealloc); 485 486 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 487 qdf_size_t size, 488 void *vaddr, 489 qdf_dma_addr_t paddr, 490 qdf_dma_context_t memctx, 491 uint8_t is_mem_prealloc); 492 #else 493 static inline 494 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 495 qdf_size_t size, 496 qdf_dma_addr_t *paddr, 497 uint32_t ring_type, 498 uint8_t *is_mem_prealloc) 499 { 500 return qdf_mem_alloc_consistent(scn->qdf_dev, 501 scn->qdf_dev->dev, 502 size, 503 paddr); 504 } 505 506 static inline 507 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 508 qdf_size_t size, 509 void *vaddr, 510 qdf_dma_addr_t paddr, 511 qdf_dma_context_t memctx, 512 uint8_t is_mem_prealloc) 513 { 514 return qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 515 size, vaddr, paddr, memctx); 516 } 517 #endif 518 519 /** 520 * hif_get_rx_ctx_id() - Returns NAPI instance ID based on CE ID 521 * @ctx_id: Rx CE context ID 522 * @hif_hdl: HIF Context 523 * 524 * Return: Rx instance ID 525 */ 526 int hif_get_rx_ctx_id(int ctx_id, struct hif_opaque_softc *hif_hdl); 527 void hif_ramdump_handler(struct hif_opaque_softc *scn); 528 #ifdef HIF_USB 529 void hif_usb_get_hw_info(struct hif_softc *scn); 530 void hif_usb_ramdump_handler(struct hif_opaque_softc *scn); 531 #else 532 static inline void hif_usb_get_hw_info(struct hif_softc *scn) {} 533 static inline void hif_usb_ramdump_handler(struct hif_opaque_softc *scn) {} 534 #endif 535 536 /** 537 * hif_wake_interrupt_handler() - interrupt handler for standalone wake irq 538 * @irq: the irq number that fired 539 * @context: the opaque pointer passed to request_irq() 540 * 541 * Return: an irq return type 542 */ 543 irqreturn_t hif_wake_interrupt_handler(int irq, void *context); 544 545 #ifdef HIF_SNOC 546 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc); 547 #else 548 static inline 549 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc) 550 { 551 return true; 552 } 553 #endif 554 555 #ifdef ADRASTEA_RRI_ON_DDR 556 void hif_uninit_rri_on_ddr(struct hif_softc *scn); 557 #else 558 static inline 559 void hif_uninit_rri_on_ddr(struct hif_softc *scn) {} 560 #endif 561 void hif_cleanup_static_buf_to_target(struct hif_softc *scn); 562 #endif /* __HIF_MAIN_H__ */ 563