1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * NB: Inappropriate references to "HTC" are used in this (and other) 22 * HIF implementations. HTC is typically the calling layer, but it 23 * theoretically could be some alternative. 24 */ 25 26 /* 27 * This holds all state needed to process a pending send/recv interrupt. 28 * The information is saved here as soon as the interrupt occurs (thus 29 * allowing the underlying CE to re-use the ring descriptor). The 30 * information here is eventually processed by a completion processing 31 * thread. 32 */ 33 34 #ifndef __HIF_MAIN_H__ 35 #define __HIF_MAIN_H__ 36 37 #include <qdf_atomic.h> /* qdf_atomic_read */ 38 #include "qdf_lock.h" 39 #include "cepci.h" 40 #include "hif.h" 41 #include "multibus.h" 42 #include "hif_unit_test_suspend_i.h" 43 #ifdef HIF_CE_LOG_INFO 44 #include "qdf_notifier.h" 45 #endif 46 47 #define HIF_MIN_SLEEP_INACTIVITY_TIME_MS 50 48 #define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60 49 50 #define HIF_MAX_BUDGET 0xFFFF 51 52 #define HIF_STATS_INC(_handle, _field, _delta) \ 53 { \ 54 (_handle)->stats._field += _delta; \ 55 } 56 57 /* 58 * This macro implementation is exposed for efficiency only. 59 * The implementation may change and callers should 60 * consider the targid to be a completely opaque handle. 61 */ 62 #define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid))) 63 64 #ifdef QCA_WIFI_3_0 65 #define DISABLE_L1SS_STATES 1 66 #endif 67 68 #define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES 69 70 #ifdef QCA_WIFI_3_0_ADRASTEA 71 #define ADRASTEA_BU 1 72 #else 73 #define ADRASTEA_BU 0 74 #endif 75 76 #ifdef QCA_WIFI_3_0 77 #define HAS_FW_INDICATOR 0 78 #else 79 #define HAS_FW_INDICATOR 1 80 #endif 81 82 83 #define AR9888_DEVICE_ID (0x003c) 84 #define AR6320_DEVICE_ID (0x003e) 85 #define AR6320_FW_1_1 (0x11) 86 #define AR6320_FW_1_3 (0x13) 87 #define AR6320_FW_2_0 (0x20) 88 #define AR6320_FW_3_0 (0x30) 89 #define AR6320_FW_3_2 (0x32) 90 #define QCA6290_EMULATION_DEVICE_ID (0xabcd) 91 #define QCA6290_DEVICE_ID (0x1100) 92 #define QCN9000_DEVICE_ID (0x1104) 93 #define QCN9224_DEVICE_ID (0x1109) 94 #define QCN6122_DEVICE_ID (0xFFFB) 95 #define QCA6390_EMULATION_DEVICE_ID (0x0108) 96 #define QCA6390_DEVICE_ID (0x1101) 97 /* TODO: change IDs for HastingsPrime */ 98 #define QCA6490_EMULATION_DEVICE_ID (0x010a) 99 #define QCA6490_DEVICE_ID (0x1103) 100 #define MANGO_DEVICE_ID (0x110a) 101 102 /* TODO: change IDs for Moselle */ 103 #define QCA6750_EMULATION_DEVICE_ID (0x010c) 104 #define QCA6750_DEVICE_ID (0x1105) 105 106 /* TODO: change IDs for Hamilton */ 107 #define KIWI_DEVICE_ID (0x1107) 108 109 #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021) 110 #define AR9887_DEVICE_ID (0x0050) 111 #define AR900B_DEVICE_ID (0x0040) 112 #define QCA9984_DEVICE_ID (0x0046) 113 #define QCA9888_DEVICE_ID (0x0056) 114 #define QCA8074_DEVICE_ID (0xffff) /* Todo: replace this with 115 actual number once available. 116 currently defining this to 0xffff for 117 emulation purpose */ 118 #define QCA8074V2_DEVICE_ID (0xfffe) /* Todo: replace this with actual number */ 119 #define QCA6018_DEVICE_ID (0xfffd) /* Todo: replace this with actual number */ 120 #define QCA5018_DEVICE_ID (0xfffc) /* Todo: replace this with actual number */ 121 #define QCA9574_DEVICE_ID (0xfffa) 122 #define QCA5332_DEVICE_ID (0xfff9) 123 /* Genoa */ 124 #define QCN7605_DEVICE_ID (0x1102) /* Genoa PCIe device ID*/ 125 #define QCN7605_COMPOSITE (0x9901) 126 #define QCN7605_STANDALONE (0x9900) 127 #define QCN7605_STANDALONE_V2 (0x9902) 128 #define QCN7605_COMPOSITE_V2 (0x9903) 129 130 #define RUMIM2M_DEVICE_ID_NODE0 0xabc0 131 #define RUMIM2M_DEVICE_ID_NODE1 0xabc1 132 #define RUMIM2M_DEVICE_ID_NODE2 0xabc2 133 #define RUMIM2M_DEVICE_ID_NODE3 0xabc3 134 #define RUMIM2M_DEVICE_ID_NODE4 0xaa10 135 #define RUMIM2M_DEVICE_ID_NODE5 0xaa11 136 137 #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn) 138 #define HIF_GET_IPCI_SOFTC(scn) ((struct hif_ipci_softc *)scn) 139 #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn) 140 #define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn) 141 #define HIF_GET_USB_SOFTC(scn) ((struct hif_usb_softc *)scn) 142 #define HIF_GET_USB_DEVICE(scn) ((struct HIF_DEVICE_USB *)scn) 143 #define HIF_GET_SOFTC(scn) ((struct hif_softc *)scn) 144 #define GET_HIF_OPAQUE_HDL(scn) ((struct hif_opaque_softc *)scn) 145 146 #ifdef QCA_WIFI_QCN9224 147 #define NUM_CE_AVAILABLE 16 148 #else 149 #define NUM_CE_AVAILABLE 12 150 #endif 151 /* Add 1 here to store default configuration in index 0 */ 152 #define NUM_CE_CONTEXT (NUM_CE_AVAILABLE + 1) 153 154 #define CE_INTERRUPT_IDX(x) x 155 156 struct ce_int_assignment { 157 uint8_t msi_idx[NUM_CE_AVAILABLE]; 158 }; 159 160 struct hif_ce_stats { 161 int hif_pipe_no_resrc_count; 162 int ce_ring_delta_fail_count; 163 }; 164 165 #ifdef HIF_DETECTION_LATENCY_ENABLE 166 struct hif_latency_detect { 167 qdf_timer_t detect_latency_timer; 168 uint32_t detect_latency_timer_timeout; 169 bool is_timer_started; 170 bool enable_detection; 171 /* threshold when stall happens */ 172 uint32_t detect_latency_threshold; 173 int ce2_tasklet_sched_cpuid; 174 qdf_time_t ce2_tasklet_sched_time; 175 qdf_time_t ce2_tasklet_exec_time; 176 qdf_time_t credit_request_time; 177 qdf_time_t credit_report_time; 178 }; 179 #endif 180 181 /* 182 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 183 * for defined here 184 */ 185 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 186 187 #define HIF_CE_MAX_LATEST_HIST 2 188 189 struct latest_evt_history { 190 uint64_t irq_entry_ts; 191 uint64_t bh_entry_ts; 192 uint64_t bh_resched_ts; 193 uint64_t bh_exit_ts; 194 uint64_t bh_work_ts; 195 int cpu_id; 196 uint32_t ring_hp; 197 uint32_t ring_tp; 198 }; 199 200 struct ce_desc_hist { 201 qdf_atomic_t history_index[CE_COUNT_MAX]; 202 uint8_t ce_id_hist_map[CE_COUNT_MAX]; 203 bool enable[CE_COUNT_MAX]; 204 bool data_enable[CE_COUNT_MAX]; 205 qdf_mutex_t ce_dbg_datamem_lock[CE_COUNT_MAX]; 206 uint32_t hist_index; 207 uint32_t hist_id; 208 void *hist_ev[CE_COUNT_MAX]; 209 struct latest_evt_history latest_evt[HIF_CE_MAX_LATEST_HIST]; 210 }; 211 212 void hif_record_latest_evt(struct ce_desc_hist *ce_hist, 213 uint8_t type, 214 int ce_id, uint64_t time, 215 uint32_t hp, uint32_t tp); 216 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 217 218 /** 219 * struct hif_cfg() - store ini config parameters in hif layer 220 * @ce_status_ring_timer_threshold: ce status ring timer threshold 221 * @ce_status_ring_batch_count_threshold: ce status ring batch count threshold 222 */ 223 struct hif_cfg { 224 uint16_t ce_status_ring_timer_threshold; 225 uint8_t ce_status_ring_batch_count_threshold; 226 }; 227 228 #ifdef DP_UMAC_HW_RESET_SUPPORT 229 /** 230 * struct hif_umac_reset_ctx - UMAC HW reset context at HIF layer 231 * @intr_tq: Tasklet structure 232 * @cb_handler: Callback handler 233 * @cb_ctx: Argument to be passed to @cb_handler 234 * @os_irq: Interrupt number for this IRQ 235 * @irq_configured: Whether the IRQ has been configured 236 */ 237 struct hif_umac_reset_ctx { 238 struct tasklet_struct intr_tq; 239 int (*cb_handler)(void *cb_ctx); 240 void *cb_ctx; 241 uint32_t os_irq; 242 bool irq_configured; 243 }; 244 #endif 245 246 struct hif_softc { 247 struct hif_opaque_softc osc; 248 struct hif_config_info hif_config; 249 struct hif_target_info target_info; 250 void __iomem *mem; 251 void __iomem *mem_ce; 252 enum qdf_bus_type bus_type; 253 struct hif_bus_ops bus_ops; 254 void *ce_id_to_state[CE_COUNT_MAX]; 255 qdf_device_t qdf_dev; 256 bool hif_init_done; 257 bool request_irq_done; 258 bool ext_grp_irq_configured; 259 bool free_irq_done; 260 uint8_t ce_latency_stats; 261 /* Packet statistics */ 262 struct hif_ce_stats pkt_stats; 263 enum hif_target_status target_status; 264 uint64_t event_enable_mask; 265 266 struct targetdef_s *targetdef; 267 struct ce_reg_def *target_ce_def; 268 struct hostdef_s *hostdef; 269 struct host_shadow_regs_s *host_shadow_regs; 270 271 bool recovery; 272 bool notice_send; 273 bool per_ce_irq; 274 uint32_t ce_irq_summary; 275 /* No of copy engines supported */ 276 unsigned int ce_count; 277 struct ce_int_assignment *int_assignment; 278 atomic_t active_tasklet_cnt; 279 atomic_t active_grp_tasklet_cnt; 280 atomic_t link_suspended; 281 uint32_t *vaddr_rri_on_ddr; 282 qdf_dma_addr_t paddr_rri_on_ddr; 283 #ifdef CONFIG_BYPASS_QMI 284 uint32_t *vaddr_qmi_bypass; 285 qdf_dma_addr_t paddr_qmi_bypass; 286 #endif 287 int linkstate_vote; 288 bool fastpath_mode_on; 289 atomic_t tasklet_from_intr; 290 int htc_htt_tx_endpoint; 291 qdf_dma_addr_t mem_pa; 292 bool athdiag_procfs_inited; 293 #ifdef FEATURE_NAPI 294 struct qca_napi_data napi_data; 295 #endif /* FEATURE_NAPI */ 296 /* stores ce_service_max_yield_time in ns */ 297 unsigned long long ce_service_max_yield_time; 298 uint8_t ce_service_max_rx_ind_flush; 299 struct hif_driver_state_callbacks callbacks; 300 uint32_t hif_con_param; 301 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 302 uint32_t nss_wifi_ol_mode; 303 #endif 304 void *hal_soc; 305 struct hif_ut_suspend_context ut_suspend_ctx; 306 uint32_t hif_attribute; 307 int wake_irq; 308 int disable_wake_irq; 309 hif_pm_wake_irq_type wake_irq_type; 310 void (*initial_wakeup_cb)(void *); 311 void *initial_wakeup_priv; 312 #ifdef REMOVE_PKT_LOG 313 /* Handle to pktlog device */ 314 void *pktlog_dev; 315 #endif 316 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 317 /* Pointer to the srng event history */ 318 struct hif_event_history *evt_hist[HIF_NUM_INT_CONTEXTS]; 319 #endif 320 321 /* 322 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 323 * for defined here 324 */ 325 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 326 struct ce_desc_hist hif_ce_desc_hist; 327 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 328 #ifdef IPA_OFFLOAD 329 qdf_shared_mem_t *ipa_ce_ring; 330 #endif 331 struct hif_cfg ini_cfg; 332 #ifdef HIF_CE_LOG_INFO 333 qdf_notif_block hif_recovery_notifier; 334 #endif 335 #ifdef HIF_CPU_PERF_AFFINE_MASK 336 /* The CPU hotplug event registration handle */ 337 struct qdf_cpuhp_handler *cpuhp_event_handle; 338 #endif 339 uint32_t irq_unlazy_disable; 340 /* Should the unlzay support for interrupt delivery be disabled */ 341 /* Flag to indicate whether bus is suspended */ 342 bool bus_suspended; 343 bool pktlog_init; 344 #ifdef FEATURE_RUNTIME_PM 345 /* Variable to track the link state change in RTPM */ 346 qdf_atomic_t pm_link_state; 347 #endif 348 #ifdef HIF_DETECTION_LATENCY_ENABLE 349 struct hif_latency_detect latency_detect; 350 #endif 351 #ifdef FEATURE_RUNTIME_PM 352 qdf_runtime_lock_t prevent_linkdown_lock; 353 #endif 354 #ifdef SYSTEM_PM_CHECK 355 qdf_atomic_t sys_pm_state; 356 #endif 357 #if defined(HIF_IPCI) && defined(FEATURE_HAL_DELAYED_REG_WRITE) 358 qdf_atomic_t dp_ep_vote_access; 359 qdf_atomic_t ep_vote_access; 360 #endif 361 /* CMEM address target reserved for host usage */ 362 uint64_t cmem_start; 363 /* CMEM size target reserved */ 364 uint64_t cmem_size; 365 #ifdef DP_UMAC_HW_RESET_SUPPORT 366 struct hif_umac_reset_ctx umac_reset_ctx; 367 #endif 368 }; 369 370 static inline 371 void *hif_get_hal_handle(struct hif_opaque_softc *hif_hdl) 372 { 373 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 374 375 if (!sc) 376 return NULL; 377 378 return sc->hal_soc; 379 } 380 381 /** 382 * hif_get_cmem_info() - get CMEM address and size from HIF handle 383 * @hif_hdl: HIF handle pointer 384 * @cmem_start: pointer for CMEM address 385 * @cmem_size: pointer for CMEM size 386 * 387 * Return: None. 388 */ 389 static inline 390 void hif_get_cmem_info(struct hif_opaque_softc *hif_hdl, 391 uint64_t *cmem_start, 392 uint64_t *cmem_size) 393 { 394 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 395 396 *cmem_start = sc->cmem_start; 397 *cmem_size = sc->cmem_size; 398 } 399 400 /** 401 * hif_get_num_active_tasklets() - get the number of active 402 * tasklets pending to be completed. 403 * @scn: HIF context 404 * 405 * Returns: the number of tasklets which are active 406 */ 407 static inline int hif_get_num_active_tasklets(struct hif_softc *scn) 408 { 409 return qdf_atomic_read(&scn->active_tasklet_cnt); 410 } 411 412 /** 413 * Max waiting time during Runtime PM suspend to finish all 414 * the tasks. This is in the multiple of 10ms. 415 */ 416 #define HIF_TASK_DRAIN_WAIT_CNT 25 417 418 /** 419 * hif_try_complete_tasks() - Try to complete all the pending tasks 420 * @scn: HIF context 421 * 422 * Try to complete all the pending datapath tasks, i.e. tasklets, 423 * DP group tasklets and works which are queued, in a given time 424 * slot. 425 * 426 * Returns: QDF_STATUS_SUCCESS if all the tasks were completed 427 * QDF error code, if the time slot exhausted 428 */ 429 QDF_STATUS hif_try_complete_tasks(struct hif_softc *scn); 430 431 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 432 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 433 { 434 return !!(sc->nss_wifi_ol_mode); 435 } 436 #else 437 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 438 { 439 return false; 440 } 441 #endif 442 443 static inline uint8_t hif_is_attribute_set(struct hif_softc *sc, 444 uint32_t hif_attrib) 445 { 446 return sc->hif_attribute == hif_attrib; 447 } 448 449 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 450 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 451 { 452 struct hif_softc *scn = (struct hif_softc *)hif_handle; 453 454 scn->event_enable_mask = HIF_EVENT_HIST_ENABLE_MASK; 455 } 456 #else 457 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 458 { 459 } 460 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 461 462 A_target_id_t hif_get_target_id(struct hif_softc *scn); 463 void hif_dump_pipe_debug_count(struct hif_softc *scn); 464 void hif_display_bus_stats(struct hif_opaque_softc *scn); 465 void hif_clear_bus_stats(struct hif_opaque_softc *scn); 466 bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count); 467 void hif_shutdown_device(struct hif_opaque_softc *hif_ctx); 468 int hif_bus_configure(struct hif_softc *scn); 469 void hif_cancel_deferred_target_sleep(struct hif_softc *scn); 470 int hif_config_ce(struct hif_softc *scn); 471 int hif_config_ce_pktlog(struct hif_opaque_softc *hif_ctx); 472 int hif_config_ce_by_id(struct hif_softc *scn, int pipe_num); 473 void hif_unconfig_ce(struct hif_softc *scn); 474 void hif_ce_prepare_config(struct hif_softc *scn); 475 QDF_STATUS hif_ce_open(struct hif_softc *scn); 476 void hif_ce_close(struct hif_softc *scn); 477 int athdiag_procfs_init(void *scn); 478 void athdiag_procfs_remove(void); 479 /* routine to modify the initial buffer count to be allocated on an os 480 * platform basis. Platform owner will need to modify this as needed 481 */ 482 qdf_size_t init_buffer_count(qdf_size_t maxSize); 483 484 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg); 485 int hif_get_device_type(uint32_t device_id, 486 uint32_t revision_id, 487 uint32_t *hif_type, uint32_t *target_type); 488 /*These functions are exposed to HDD*/ 489 void hif_nointrs(struct hif_softc *scn); 490 void hif_bus_close(struct hif_softc *ol_sc); 491 QDF_STATUS hif_bus_open(struct hif_softc *ol_sc, 492 enum qdf_bus_type bus_type); 493 QDF_STATUS hif_enable_bus(struct hif_softc *ol_sc, struct device *dev, 494 void *bdev, const struct hif_bus_id *bid, enum hif_enable_type type); 495 void hif_disable_bus(struct hif_softc *scn); 496 void hif_bus_prevent_linkdown(struct hif_softc *scn, bool flag); 497 int hif_bus_get_context_size(enum qdf_bus_type bus_type); 498 void hif_read_phy_mem_base(struct hif_softc *scn, qdf_dma_addr_t *bar_value); 499 uint32_t hif_get_conparam(struct hif_softc *scn); 500 struct hif_driver_state_callbacks *hif_get_callbacks_handle( 501 struct hif_softc *scn); 502 bool hif_is_driver_unloading(struct hif_softc *scn); 503 bool hif_is_load_or_unload_in_progress(struct hif_softc *scn); 504 bool hif_is_recovery_in_progress(struct hif_softc *scn); 505 bool hif_is_target_ready(struct hif_softc *scn); 506 507 /** 508 * hif_get_bandwidth_level() - API to get the current bandwidth level 509 * @scn: HIF Context 510 * 511 * Return: PLD bandwidth level 512 */ 513 int hif_get_bandwidth_level(struct hif_opaque_softc *hif_handle); 514 515 void hif_wlan_disable(struct hif_softc *scn); 516 int hif_target_sleep_state_adjust(struct hif_softc *scn, 517 bool sleep_ok, 518 bool wait_for_it); 519 520 #ifdef DP_MEM_PRE_ALLOC 521 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 522 qdf_size_t size, 523 qdf_dma_addr_t *paddr, 524 uint32_t ring_type, 525 uint8_t *is_mem_prealloc); 526 527 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 528 qdf_size_t size, 529 void *vaddr, 530 qdf_dma_addr_t paddr, 531 qdf_dma_context_t memctx, 532 uint8_t is_mem_prealloc); 533 #else 534 static inline 535 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 536 qdf_size_t size, 537 qdf_dma_addr_t *paddr, 538 uint32_t ring_type, 539 uint8_t *is_mem_prealloc) 540 { 541 return qdf_mem_alloc_consistent(scn->qdf_dev, 542 scn->qdf_dev->dev, 543 size, 544 paddr); 545 } 546 547 static inline 548 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 549 qdf_size_t size, 550 void *vaddr, 551 qdf_dma_addr_t paddr, 552 qdf_dma_context_t memctx, 553 uint8_t is_mem_prealloc) 554 { 555 return qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 556 size, vaddr, paddr, memctx); 557 } 558 #endif 559 560 /** 561 * hif_get_rx_ctx_id() - Returns NAPI instance ID based on CE ID 562 * @ctx_id: Rx CE context ID 563 * @hif_hdl: HIF Context 564 * 565 * Return: Rx instance ID 566 */ 567 int hif_get_rx_ctx_id(int ctx_id, struct hif_opaque_softc *hif_hdl); 568 void hif_ramdump_handler(struct hif_opaque_softc *scn); 569 #ifdef HIF_USB 570 void hif_usb_get_hw_info(struct hif_softc *scn); 571 void hif_usb_ramdump_handler(struct hif_opaque_softc *scn); 572 #else 573 static inline void hif_usb_get_hw_info(struct hif_softc *scn) {} 574 static inline void hif_usb_ramdump_handler(struct hif_opaque_softc *scn) {} 575 #endif 576 577 /** 578 * hif_wake_interrupt_handler() - interrupt handler for standalone wake irq 579 * @irq: the irq number that fired 580 * @context: the opaque pointer passed to request_irq() 581 * 582 * Return: an irq return type 583 */ 584 irqreturn_t hif_wake_interrupt_handler(int irq, void *context); 585 586 #ifdef HIF_SNOC 587 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc); 588 #else 589 static inline 590 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc) 591 { 592 return true; 593 } 594 #endif 595 596 #ifdef ADRASTEA_RRI_ON_DDR 597 void hif_uninit_rri_on_ddr(struct hif_softc *scn); 598 #else 599 static inline 600 void hif_uninit_rri_on_ddr(struct hif_softc *scn) {} 601 #endif 602 void hif_cleanup_static_buf_to_target(struct hif_softc *scn); 603 604 #ifdef FEATURE_RUNTIME_PM 605 /** 606 * hif_runtime_prevent_linkdown() - prevent or allow a runtime pm from occurring 607 * @scn: hif context 608 * @is_get: prevent linkdown if true otherwise allow 609 * 610 * this api should only be called as part of bus prevent linkdown 611 */ 612 void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get); 613 #else 614 static inline 615 void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get) 616 { 617 } 618 #endif 619 620 #endif /* __HIF_MAIN_H__ */ 621