1 /* 2 * Copyright (c) 2015-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef __HIF_IO32_H__ 20 #define __HIF_IO32_H__ 21 22 #include <linux/io.h> 23 #include "hif.h" 24 #include "hif_main.h" 25 26 #if defined(HIF_REG_WINDOW_SUPPORT) && (defined(HIF_PCI) || \ 27 defined(HIF_IPCI)) 28 29 static inline 30 void hif_write32_mb_reg_window(void *sc, 31 void __iomem *addr, uint32_t value); 32 static inline 33 uint32_t hif_read32_mb_reg_window(void *sc, 34 void __iomem *addr); 35 #define hif_read32_mb(scn, addr) \ 36 hif_read32_mb_reg_window((void *)scn, \ 37 (void __iomem *)addr) 38 #define hif_write32_mb(scn, addr, value) \ 39 hif_write32_mb_reg_window((void *)scn, \ 40 (void __iomem *)addr, value) 41 42 #else 43 #define hif_read32_mb(scn, addr) ioread32((void __iomem *)addr) 44 #define hif_write32_mb(scn, addr, value) \ 45 iowrite32((u32)(value), (void __iomem *)(addr)) 46 #endif 47 48 #define Q_TARGET_ACCESS_BEGIN(scn) \ 49 hif_target_sleep_state_adjust(scn, false, true) 50 #define Q_TARGET_ACCESS_END(scn) \ 51 hif_target_sleep_state_adjust(scn, true, false) 52 #define TARGET_REGISTER_ACCESS_ALLOWED(scn)\ 53 hif_is_target_register_access_allowed(scn) 54 55 /* 56 * A_TARGET_ACCESS_LIKELY will not wait for the target to wake up before 57 * continuing execution. Because A_TARGET_ACCESS_LIKELY does not guarantee 58 * that the target is awake before continuing, Q_TARGET_ACCESS macros must 59 * protect the actual target access. Since Q_TARGET_ACCESS protect the actual 60 * target access, A_TARGET_ACCESS_LIKELY hints are optional. 61 * 62 * To ignore "LIKELY" hints, set CONFIG_TARGET_ACCESS_LIKELY to 0 63 * (slightly worse performance, less power) 64 * 65 * To use "LIKELY" hints, set CONFIG_TARGET_ACCESS_LIKELY to 1 66 * (slightly better performance, more power) 67 * 68 * note: if a bus doesn't use hif_target_sleep_state_adjust, this will have 69 * no impact. 70 */ 71 #define CONFIG_TARGET_ACCESS_LIKELY 0 72 #if CONFIG_TARGET_ACCESS_LIKELY 73 #define A_TARGET_ACCESS_LIKELY(scn) \ 74 hif_target_sleep_state_adjust(scn, false, false) 75 #define A_TARGET_ACCESS_UNLIKELY(scn) \ 76 hif_target_sleep_state_adjust(scn, true, false) 77 #else /* CONFIG_ATH_PCIE_ACCESS_LIKELY */ 78 #define A_TARGET_ACCESS_LIKELY(scn) \ 79 do { \ 80 unsigned long unused = (unsigned long)(scn); \ 81 unused = unused; \ 82 } while (0) 83 84 #define A_TARGET_ACCESS_UNLIKELY(scn) \ 85 do { \ 86 unsigned long unused = (unsigned long)(scn); \ 87 unused = unused; \ 88 } while (0) 89 #endif /* CONFIG_ATH_PCIE_ACCESS_LIKELY */ 90 91 92 #ifdef HIF_PCI 93 #include "hif_io32_pci.h" 94 #endif 95 #ifdef HIF_SNOC 96 #include "hif_io32_snoc.h" 97 #endif 98 #ifdef HIF_IPCI 99 #include "hif_io32_ipci.h" 100 #endif 101 102 #if defined(HIF_REG_WINDOW_SUPPORT) && (defined(HIF_PCI) || \ 103 defined(HIF_IPCI)) 104 105 #include "qdf_lock.h" 106 #include "qdf_util.h" 107 108 /* Device memory is 32MB but bar size is only 1MB. 109 * Register remapping logic is used to access 32MB device memory. 110 * 0-512KB : Fixed address, 512KB-1MB : remapped address. 111 * Use PCIE_REMAP_1M_BAR_CTRL register to set window. 112 * Offset: 0x310C 113 * Bits : Field Name 114 * 31 FUNCTION_ENABLE_V 115 * 5:0 ADDR_24_19_V 116 */ 117 118 #define MAX_UNWINDOWED_ADDRESS 0x80000 /* 512KB */ 119 #define WINDOW_ENABLE_BIT 0x80000000 /* 31st bit to enable window */ 120 #define WINDOW_REG_ADDRESS 0x310C /* PCIE_REMAP_1M_BAR_CTRL Reg offset */ 121 #define WINDOW_SHIFT 19 122 #define WINDOW_VALUE_MASK 0x3F 123 #define WINDOW_START MAX_UNWINDOWED_ADDRESS 124 #define WINDOW_RANGE_MASK 0x7FFFF 125 126 static inline void hif_select_window(struct hif_pci_softc *sc, uint32_t offset) 127 { 128 uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK; 129 130 if (window != sc->register_window) { 131 qdf_iowrite32(sc->mem + WINDOW_REG_ADDRESS, 132 WINDOW_ENABLE_BIT | window); 133 sc->register_window = window; 134 } 135 } 136 137 /** 138 * note1: WINDOW_RANGE_MASK = (1 << WINDOW_SHIFT) -1 139 * note2: 1 << WINDOW_SHIFT = MAX_UNWINDOWED_ADDRESS 140 * note3: WINDOW_VALUE_MASK = big enough that trying to write past that window 141 * would be a bug 142 */ 143 static inline void hif_write32_mb_reg_window(void *scn, 144 void __iomem *addr, uint32_t value) 145 { 146 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 147 uint32_t offset = addr - sc->mem; 148 149 if (!sc->use_register_windowing || 150 offset < MAX_UNWINDOWED_ADDRESS) { 151 qdf_iowrite32(addr, value); 152 } else { 153 qdf_spin_lock_irqsave(&sc->register_access_lock); 154 hif_select_window(sc, offset); 155 qdf_iowrite32(sc->mem + WINDOW_START + 156 (offset & WINDOW_RANGE_MASK), value); 157 qdf_spin_unlock_irqrestore(&sc->register_access_lock); 158 } 159 } 160 161 static inline uint32_t hif_read32_mb_reg_window(void *scn, void __iomem *addr) 162 { 163 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 164 uint32_t ret; 165 uint32_t offset = addr - sc->mem; 166 167 if (!sc->use_register_windowing || 168 offset < MAX_UNWINDOWED_ADDRESS) { 169 return qdf_ioread32(addr); 170 } 171 172 qdf_spin_lock_irqsave(&sc->register_access_lock); 173 hif_select_window(sc, offset); 174 ret = qdf_ioread32(sc->mem + WINDOW_START + 175 (offset & WINDOW_RANGE_MASK)); 176 qdf_spin_unlock_irqrestore(&sc->register_access_lock); 177 178 return ret; 179 } 180 #endif 181 182 #ifdef CONFIG_IO_MEM_ACCESS_DEBUG 183 uint32_t hif_target_read_checked(struct hif_softc *scn, 184 uint32_t offset); 185 void hif_target_write_checked(struct hif_softc *scn, uint32_t offset, 186 uint32_t value); 187 188 #define A_TARGET_READ(scn, offset) \ 189 hif_target_read_checked(scn, (offset)) 190 #define A_TARGET_WRITE(scn, offset, value) \ 191 hif_target_write_checked(scn, (offset), (value)) 192 #else /* CONFIG_ATH_PCIE_ACCESS_DEBUG */ 193 #define A_TARGET_READ(scn, offset) \ 194 hif_read32_mb(scn, scn->mem + (offset)) 195 #define A_TARGET_WRITE(scn, offset, value) \ 196 hif_write32_mb(scn, (scn->mem) + (offset), value) 197 #endif 198 199 void hif_irq_enable(struct hif_softc *scn, int irq_id); 200 void hif_irq_disable(struct hif_softc *scn, int irq_id); 201 202 #endif /* __HIF_IO32_H__ */ 203