1 /* 2 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef __HIF_IO32_H__ 20 #define __HIF_IO32_H__ 21 22 #include <linux/io.h> 23 #include "hif.h" 24 #include "hif_main.h" 25 26 #if defined(HIF_REG_WINDOW_SUPPORT) && defined(HIF_PCI) 27 28 static inline 29 void hif_write32_mb_reg_window(void *sc, 30 void __iomem *addr, uint32_t value); 31 32 static inline uint32_t hif_read32_mb_reg_window(void *sc, 33 void __iomem *addr); 34 35 #define hif_read32_mb(scn, addr) \ 36 hif_read32_mb_reg_window((void *)scn, \ 37 (void __iomem *)addr) 38 #define hif_write32_mb(scn, addr, value) \ 39 hif_write32_mb_reg_window((void *)scn, \ 40 (void __iomem *)addr, value) 41 42 #else 43 44 #define hif_read32_mb(scn, addr) ioread32((void __iomem *)addr) 45 #define hif_write32_mb(scn, addr, value) \ 46 iowrite32((u32)(value), (void __iomem *)(addr)) 47 48 #endif 49 50 #define Q_TARGET_ACCESS_BEGIN(scn) \ 51 hif_target_sleep_state_adjust(scn, false, true) 52 #define Q_TARGET_ACCESS_END(scn) \ 53 hif_target_sleep_state_adjust(scn, true, false) 54 #define TARGET_REGISTER_ACCESS_ALLOWED(scn)\ 55 hif_is_target_register_access_allowed(scn) 56 57 /* 58 * A_TARGET_ACCESS_LIKELY will not wait for the target to wake up before 59 * continuing execution. Because A_TARGET_ACCESS_LIKELY does not guarantee 60 * that the target is awake before continuing, Q_TARGET_ACCESS macros must 61 * protect the actual target access. Since Q_TARGET_ACCESS protect the actual 62 * target access, A_TARGET_ACCESS_LIKELY hints are optional. 63 * 64 * To ignore "LIKELY" hints, set CONFIG_TARGET_ACCESS_LIKELY to 0 65 * (slightly worse performance, less power) 66 * 67 * To use "LIKELY" hints, set CONFIG_TARGET_ACCESS_LIKELY to 1 68 * (slightly better performance, more power) 69 * 70 * note: if a bus doesn't use hif_target_sleep_state_adjust, this will have 71 * no impact. 72 */ 73 #define CONFIG_TARGET_ACCESS_LIKELY 0 74 #if CONFIG_TARGET_ACCESS_LIKELY 75 #define A_TARGET_ACCESS_LIKELY(scn) \ 76 hif_target_sleep_state_adjust(scn, false, false) 77 #define A_TARGET_ACCESS_UNLIKELY(scn) \ 78 hif_target_sleep_state_adjust(scn, true, false) 79 #else /* CONFIG_ATH_PCIE_ACCESS_LIKELY */ 80 #define A_TARGET_ACCESS_LIKELY(scn) \ 81 do { \ 82 unsigned long unused = (unsigned long)(scn); \ 83 unused = unused; \ 84 } while (0) 85 86 #define A_TARGET_ACCESS_UNLIKELY(scn) \ 87 do { \ 88 unsigned long unused = (unsigned long)(scn); \ 89 unused = unused; \ 90 } while (0) 91 #endif /* CONFIG_ATH_PCIE_ACCESS_LIKELY */ 92 93 94 #ifdef HIF_PCI 95 #include "hif_io32_pci.h" 96 #endif 97 #ifdef HIF_SNOC 98 #include "hif_io32_snoc.h" 99 #endif /* HIF_PCI */ 100 101 #if defined(HIF_REG_WINDOW_SUPPORT) && defined(HIF_PCI) 102 #include "qdf_lock.h" 103 #include "qdf_util.h" 104 105 /* Device memory is 32MB but bar size is only 1MB. 106 * Register remapping logic is used to access 32MB device memory. 107 * 0-512KB : Fixed address, 512KB-1MB : remapped address. 108 * Use PCIE_REMAP_1M_BAR_CTRL register to set window. 109 * Offset: 0x310C 110 * Bits : Field Name 111 * 31 FUNCTION_ENABLE_V 112 * 5:0 ADDR_24_19_V 113 */ 114 115 #define MAX_UNWINDOWED_ADDRESS 0x80000 /* 512KB */ 116 #define WINDOW_ENABLE_BIT 0x80000000 /* 31st bit to enable window */ 117 #define WINDOW_REG_ADDRESS 0x310C /* PCIE_REMAP_1M_BAR_CTRL Reg offset */ 118 #define WINDOW_SHIFT 19 119 #define WINDOW_VALUE_MASK 0x3F 120 #define WINDOW_START MAX_UNWINDOWED_ADDRESS 121 #define WINDOW_RANGE_MASK 0x7FFFF 122 123 static inline void hif_select_window(struct hif_pci_softc *sc, uint32_t offset) 124 { 125 uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK; 126 127 if (window != sc->register_window) { 128 qdf_iowrite32(sc->mem + WINDOW_REG_ADDRESS, 129 WINDOW_ENABLE_BIT | window); 130 sc->register_window = window; 131 } 132 } 133 134 /** 135 * note1: WINDOW_RANGE_MASK = (1 << WINDOW_SHIFT) -1 136 * note2: 1 << WINDOW_SHIFT = MAX_UNWINDOWED_ADDRESS 137 * note3: WINDOW_VALUE_MASK = big enough that trying to write past that window 138 * would be a bug 139 */ 140 static inline void hif_write32_mb_reg_window(void *scn, 141 void __iomem *addr, uint32_t value) 142 { 143 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 144 uint32_t offset = addr - sc->mem; 145 146 if (!sc->use_register_windowing || 147 offset < MAX_UNWINDOWED_ADDRESS) { 148 qdf_iowrite32(addr, value); 149 } else { 150 qdf_spin_lock_irqsave(&sc->register_access_lock); 151 hif_select_window(sc, offset); 152 qdf_iowrite32(sc->mem + WINDOW_START + 153 (offset & WINDOW_RANGE_MASK), value); 154 qdf_spin_unlock_irqrestore(&sc->register_access_lock); 155 } 156 } 157 158 static inline uint32_t hif_read32_mb_reg_window(void *scn, void __iomem *addr) 159 { 160 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 161 uint32_t ret; 162 uint32_t offset = addr - sc->mem; 163 164 if (!sc->use_register_windowing || 165 offset < MAX_UNWINDOWED_ADDRESS) { 166 return qdf_ioread32(addr); 167 } 168 169 qdf_spin_lock_irqsave(&sc->register_access_lock); 170 hif_select_window(sc, offset); 171 ret = qdf_ioread32(sc->mem + WINDOW_START + 172 (offset & WINDOW_RANGE_MASK)); 173 qdf_spin_unlock_irqrestore(&sc->register_access_lock); 174 175 return ret; 176 } 177 #endif 178 179 #ifdef CONFIG_IO_MEM_ACCESS_DEBUG 180 uint32_t hif_target_read_checked(struct hif_softc *scn, 181 uint32_t offset); 182 void hif_target_write_checked(struct hif_softc *scn, uint32_t offset, 183 uint32_t value); 184 185 #define A_TARGET_READ(scn, offset) \ 186 hif_target_read_checked(scn, (offset)) 187 #define A_TARGET_WRITE(scn, offset, value) \ 188 hif_target_write_checked(scn, (offset), (value)) 189 #else /* CONFIG_ATH_PCIE_ACCESS_DEBUG */ 190 #define A_TARGET_READ(scn, offset) \ 191 hif_read32_mb(scn, scn->mem + (offset)) 192 #define A_TARGET_WRITE(scn, offset, value) \ 193 hif_write32_mb(scn, (scn->mem) + (offset), value) 194 #endif 195 196 void hif_irq_enable(struct hif_softc *scn, int irq_id); 197 void hif_irq_disable(struct hif_softc *scn, int irq_id); 198 199 #endif /* __HIF_IO32_H__ */ 200