1 /* 2 * Copyright (c) 2015-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef __HIF_IO32_H__ 20 #define __HIF_IO32_H__ 21 22 #include <linux/io.h> 23 #include "hif.h" 24 #include "hif_main.h" 25 26 #if defined(HIF_REG_WINDOW_SUPPORT) && defined(HIF_PCI) 27 28 static inline 29 void hif_write32_mb_reg_window(void *sc, 30 void __iomem *addr, uint32_t value); 31 static inline 32 uint32_t hif_read32_mb_reg_window(void *sc, 33 void __iomem *addr); 34 #define hif_read32_mb(scn, addr) \ 35 hif_read32_mb_reg_window((void *)scn, \ 36 (void __iomem *)addr) 37 #define hif_write32_mb(scn, addr, value) \ 38 hif_write32_mb_reg_window((void *)scn, \ 39 (void __iomem *)addr, value) 40 41 #else 42 #define hif_read32_mb(scn, addr) ioread32((void __iomem *)addr) 43 #define hif_write32_mb(scn, addr, value) \ 44 iowrite32((u32)(value), (void __iomem *)(addr)) 45 #endif 46 47 #define Q_TARGET_ACCESS_BEGIN(scn) \ 48 hif_target_sleep_state_adjust(scn, false, true) 49 #define Q_TARGET_ACCESS_END(scn) \ 50 hif_target_sleep_state_adjust(scn, true, false) 51 #define TARGET_REGISTER_ACCESS_ALLOWED(scn)\ 52 hif_is_target_register_access_allowed(scn) 53 54 /* 55 * A_TARGET_ACCESS_LIKELY will not wait for the target to wake up before 56 * continuing execution. Because A_TARGET_ACCESS_LIKELY does not guarantee 57 * that the target is awake before continuing, Q_TARGET_ACCESS macros must 58 * protect the actual target access. Since Q_TARGET_ACCESS protect the actual 59 * target access, A_TARGET_ACCESS_LIKELY hints are optional. 60 * 61 * To ignore "LIKELY" hints, set CONFIG_TARGET_ACCESS_LIKELY to 0 62 * (slightly worse performance, less power) 63 * 64 * To use "LIKELY" hints, set CONFIG_TARGET_ACCESS_LIKELY to 1 65 * (slightly better performance, more power) 66 * 67 * note: if a bus doesn't use hif_target_sleep_state_adjust, this will have 68 * no impact. 69 */ 70 #define CONFIG_TARGET_ACCESS_LIKELY 0 71 #if CONFIG_TARGET_ACCESS_LIKELY 72 #define A_TARGET_ACCESS_LIKELY(scn) \ 73 hif_target_sleep_state_adjust(scn, false, false) 74 #define A_TARGET_ACCESS_UNLIKELY(scn) \ 75 hif_target_sleep_state_adjust(scn, true, false) 76 #else /* CONFIG_ATH_PCIE_ACCESS_LIKELY */ 77 #define A_TARGET_ACCESS_LIKELY(scn) \ 78 do { \ 79 unsigned long unused = (unsigned long)(scn); \ 80 unused = unused; \ 81 } while (0) 82 83 #define A_TARGET_ACCESS_UNLIKELY(scn) \ 84 do { \ 85 unsigned long unused = (unsigned long)(scn); \ 86 unused = unused; \ 87 } while (0) 88 #endif /* CONFIG_ATH_PCIE_ACCESS_LIKELY */ 89 90 91 #ifdef HIF_PCI 92 #include "hif_io32_pci.h" 93 #endif 94 #ifdef HIF_SNOC 95 #include "hif_io32_snoc.h" 96 #endif /* HIF_PCI */ 97 98 #if defined(HIF_REG_WINDOW_SUPPORT) && defined(HIF_PCI) 99 #include "qdf_lock.h" 100 #include "qdf_util.h" 101 102 /* Device memory is 32MB but bar size is only 1MB. 103 * Register remapping logic is used to access 32MB device memory. 104 * 0-512KB : Fixed address, 512KB-1MB : remapped address. 105 * Use PCIE_REMAP_1M_BAR_CTRL register to set window. 106 * Offset: 0x310C 107 * Bits : Field Name 108 * 31 FUNCTION_ENABLE_V 109 * 5:0 ADDR_24_19_V 110 */ 111 112 #define MAX_UNWINDOWED_ADDRESS 0x80000 /* 512KB */ 113 #define WINDOW_ENABLE_BIT 0x80000000 /* 31st bit to enable window */ 114 #define WINDOW_REG_ADDRESS 0x310C /* PCIE_REMAP_1M_BAR_CTRL Reg offset */ 115 #define WINDOW_SHIFT 19 116 #define WINDOW_VALUE_MASK 0x3F 117 #define WINDOW_START MAX_UNWINDOWED_ADDRESS 118 #define WINDOW_RANGE_MASK 0x7FFFF 119 120 static inline void hif_select_window(struct hif_pci_softc *sc, uint32_t offset) 121 { 122 uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK; 123 124 if (window != sc->register_window) { 125 qdf_iowrite32(sc->mem + WINDOW_REG_ADDRESS, 126 WINDOW_ENABLE_BIT | window); 127 sc->register_window = window; 128 } 129 } 130 131 /** 132 * note1: WINDOW_RANGE_MASK = (1 << WINDOW_SHIFT) -1 133 * note2: 1 << WINDOW_SHIFT = MAX_UNWINDOWED_ADDRESS 134 * note3: WINDOW_VALUE_MASK = big enough that trying to write past that window 135 * would be a bug 136 */ 137 static inline void hif_write32_mb_reg_window(void *scn, 138 void __iomem *addr, uint32_t value) 139 { 140 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 141 uint32_t offset = addr - sc->mem; 142 143 if (!sc->use_register_windowing || 144 offset < MAX_UNWINDOWED_ADDRESS) { 145 qdf_iowrite32(addr, value); 146 } else { 147 qdf_spin_lock_irqsave(&sc->register_access_lock); 148 hif_select_window(sc, offset); 149 qdf_iowrite32(sc->mem + WINDOW_START + 150 (offset & WINDOW_RANGE_MASK), value); 151 qdf_spin_unlock_irqrestore(&sc->register_access_lock); 152 } 153 } 154 155 static inline uint32_t hif_read32_mb_reg_window(void *scn, void __iomem *addr) 156 { 157 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 158 uint32_t ret; 159 uint32_t offset = addr - sc->mem; 160 161 if (!sc->use_register_windowing || 162 offset < MAX_UNWINDOWED_ADDRESS) { 163 return qdf_ioread32(addr); 164 } 165 166 qdf_spin_lock_irqsave(&sc->register_access_lock); 167 hif_select_window(sc, offset); 168 ret = qdf_ioread32(sc->mem + WINDOW_START + 169 (offset & WINDOW_RANGE_MASK)); 170 qdf_spin_unlock_irqrestore(&sc->register_access_lock); 171 172 return ret; 173 } 174 #endif 175 176 #ifdef CONFIG_IO_MEM_ACCESS_DEBUG 177 uint32_t hif_target_read_checked(struct hif_softc *scn, 178 uint32_t offset); 179 void hif_target_write_checked(struct hif_softc *scn, uint32_t offset, 180 uint32_t value); 181 182 #define A_TARGET_READ(scn, offset) \ 183 hif_target_read_checked(scn, (offset)) 184 #define A_TARGET_WRITE(scn, offset, value) \ 185 hif_target_write_checked(scn, (offset), (value)) 186 #else /* CONFIG_ATH_PCIE_ACCESS_DEBUG */ 187 #define A_TARGET_READ(scn, offset) \ 188 hif_read32_mb(scn, scn->mem + (offset)) 189 #define A_TARGET_WRITE(scn, offset, value) \ 190 hif_write32_mb(scn, (scn->mem) + (offset), value) 191 #endif 192 193 void hif_irq_enable(struct hif_softc *scn, int irq_id); 194 void hif_irq_disable(struct hif_softc *scn, int irq_id); 195 196 #endif /* __HIF_IO32_H__ */ 197