1 /* 2 * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <hif_exec.h> 21 #include <ce_main.h> 22 #include "qdf_module.h" 23 #include "qdf_net_if.h" 24 #include <pld_common.h> 25 26 /* mapping NAPI budget 0 to internal budget 0 27 * NAPI budget 1 to internal budget [1,scaler -1] 28 * NAPI budget 2 to internal budget [scaler, 2 * scaler - 1], etc 29 */ 30 #define NAPI_BUDGET_TO_INTERNAL_BUDGET(n, s) \ 31 (((n) << (s)) - 1) 32 #define INTERNAL_BUDGET_TO_NAPI_BUDGET(n, s) \ 33 (((n) + 1) >> (s)) 34 35 static struct hif_exec_context *hif_exec_tasklet_create(void); 36 37 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 38 struct hif_event_history hif_event_desc_history[HIF_NUM_INT_CONTEXTS]; 39 40 static inline 41 int hif_get_next_record_index(qdf_atomic_t *table_index, 42 int array_size) 43 { 44 int record_index = qdf_atomic_inc_return(table_index); 45 46 return record_index & (array_size - 1); 47 } 48 49 /** 50 * hif_hist_is_prev_record() - Check if index is the immediate 51 * previous record wrt curr_index 52 * @curr_index: curr index in the event history 53 * @index: index to be checked 54 * @hist_size: history size 55 * 56 * Return: true if index is immediately behind curr_index else false 57 */ 58 static inline 59 bool hif_hist_is_prev_record(int32_t curr_index, int32_t index, 60 uint32_t hist_size) 61 { 62 return (((index + 1) & (hist_size - 1)) == curr_index) ? 63 true : false; 64 } 65 66 /** 67 * hif_hist_skip_event_record() - Check if current event needs to be 68 * recorded or not 69 * @hist_ev: HIF event history 70 * @event: DP event entry 71 * 72 * Return: true if current event needs to be skipped else false 73 */ 74 static bool 75 hif_hist_skip_event_record(struct hif_event_history *hist_ev, 76 struct hif_event_record *event) 77 { 78 struct hif_event_record *rec; 79 struct hif_event_record *last_irq_rec; 80 int32_t index; 81 82 index = qdf_atomic_read(&hist_ev->index); 83 if (index < 0) 84 return false; 85 86 index &= (HIF_EVENT_HIST_MAX - 1); 87 rec = &hist_ev->event[index]; 88 89 switch (event->type) { 90 case HIF_EVENT_IRQ_TRIGGER: 91 /* 92 * The prev record check is to prevent skipping the IRQ event 93 * record in case where BH got re-scheduled due to force_break 94 * but there are no entries to be reaped in the rings. 95 */ 96 if (rec->type == HIF_EVENT_BH_SCHED && 97 hif_hist_is_prev_record(index, 98 hist_ev->misc.last_irq_index, 99 HIF_EVENT_HIST_MAX)) { 100 last_irq_rec = 101 &hist_ev->event[hist_ev->misc.last_irq_index]; 102 last_irq_rec->timestamp = hif_get_log_timestamp(); 103 last_irq_rec->cpu_id = qdf_get_cpu(); 104 last_irq_rec->hp++; 105 last_irq_rec->tp = last_irq_rec->timestamp - 106 hist_ev->misc.last_irq_ts; 107 return true; 108 } 109 break; 110 case HIF_EVENT_BH_SCHED: 111 if (rec->type == HIF_EVENT_BH_SCHED) { 112 rec->timestamp = hif_get_log_timestamp(); 113 rec->cpu_id = qdf_get_cpu(); 114 return true; 115 } 116 break; 117 case HIF_EVENT_SRNG_ACCESS_START: 118 if (event->hp == event->tp) 119 return true; 120 break; 121 case HIF_EVENT_SRNG_ACCESS_END: 122 if (rec->type != HIF_EVENT_SRNG_ACCESS_START) 123 return true; 124 break; 125 case HIF_EVENT_BH_COMPLETE: 126 case HIF_EVENT_BH_FORCE_BREAK: 127 if (rec->type != HIF_EVENT_SRNG_ACCESS_END) 128 return true; 129 break; 130 default: 131 break; 132 } 133 134 return false; 135 } 136 137 void hif_hist_record_event(struct hif_opaque_softc *hif_ctx, 138 struct hif_event_record *event, uint8_t intr_grp_id) 139 { 140 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 141 struct hif_event_history *hist_ev; 142 struct hif_event_record *record; 143 int record_index; 144 145 if (!(scn->event_enable_mask & BIT(event->type))) 146 return; 147 148 if (qdf_unlikely(intr_grp_id >= HIF_NUM_INT_CONTEXTS)) { 149 hif_err("Invalid interrupt group id %d", intr_grp_id); 150 return; 151 } 152 153 hist_ev = scn->evt_hist[intr_grp_id]; 154 if (qdf_unlikely(!hist_ev)) 155 return; 156 157 if (hif_hist_skip_event_record(hist_ev, event)) 158 return; 159 160 record_index = hif_get_next_record_index( 161 &hist_ev->index, HIF_EVENT_HIST_MAX); 162 163 record = &hist_ev->event[record_index]; 164 165 if (event->type == HIF_EVENT_IRQ_TRIGGER) { 166 hist_ev->misc.last_irq_index = record_index; 167 hist_ev->misc.last_irq_ts = hif_get_log_timestamp(); 168 } 169 170 record->hal_ring_id = event->hal_ring_id; 171 record->hp = event->hp; 172 record->tp = event->tp; 173 record->cpu_id = qdf_get_cpu(); 174 record->timestamp = hif_get_log_timestamp(); 175 record->type = event->type; 176 } 177 178 void hif_event_history_init(struct hif_opaque_softc *hif_ctx, uint8_t id) 179 { 180 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 181 182 scn->evt_hist[id] = &hif_event_desc_history[id]; 183 qdf_atomic_set(&scn->evt_hist[id]->index, -1); 184 185 hif_info("SRNG events history initialized for group: %d", id); 186 } 187 188 void hif_event_history_deinit(struct hif_opaque_softc *hif_ctx, uint8_t id) 189 { 190 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 191 192 scn->evt_hist[id] = NULL; 193 hif_info("SRNG events history de-initialized for group: %d", id); 194 } 195 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 196 197 /** 198 * hif_print_napi_latency_stats() - print NAPI scheduling latency stats 199 * @hif_state: hif context 200 * 201 * return: void 202 */ 203 #ifdef HIF_LATENCY_PROFILE_ENABLE 204 static void hif_print_napi_latency_stats(struct HIF_CE_state *hif_state) 205 { 206 struct hif_exec_context *hif_ext_group; 207 int i, j; 208 int64_t cur_tstamp; 209 210 const char time_str[HIF_SCHED_LATENCY_BUCKETS][15] = { 211 "0-2 ms", 212 "3-10 ms", 213 "11-20 ms", 214 "21-50 ms", 215 "51-100 ms", 216 "101-250 ms", 217 "251-500 ms", 218 "> 500 ms" 219 }; 220 221 cur_tstamp = qdf_ktime_to_ms(qdf_ktime_get()); 222 223 QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_FATAL, 224 "Current timestamp: %lld", cur_tstamp); 225 226 for (i = 0; i < hif_state->hif_num_extgroup; i++) { 227 if (hif_state->hif_ext_group[i]) { 228 hif_ext_group = hif_state->hif_ext_group[i]; 229 230 QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_FATAL, 231 "Interrupts in the HIF Group"); 232 233 for (j = 0; j < hif_ext_group->numirq; j++) { 234 QDF_TRACE(QDF_MODULE_ID_HIF, 235 QDF_TRACE_LEVEL_FATAL, 236 " %s", 237 hif_ext_group->irq_name 238 (hif_ext_group->irq[j])); 239 } 240 241 QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_FATAL, 242 "Last serviced timestamp: %lld", 243 hif_ext_group->tstamp); 244 245 QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_FATAL, 246 "Latency Bucket | Time elapsed"); 247 248 for (j = 0; j < HIF_SCHED_LATENCY_BUCKETS; j++) { 249 QDF_TRACE(QDF_MODULE_ID_HIF, 250 QDF_TRACE_LEVEL_FATAL, 251 "%s | %lld", time_str[j], 252 hif_ext_group-> 253 sched_latency_stats[j]); 254 } 255 } 256 } 257 } 258 #else 259 static void hif_print_napi_latency_stats(struct HIF_CE_state *hif_state) 260 { 261 } 262 #endif 263 264 /** 265 * hif_clear_napi_stats() - reset NAPI stats 266 * @hif_ctx: hif context 267 * 268 * return: void 269 */ 270 void hif_clear_napi_stats(struct hif_opaque_softc *hif_ctx) 271 { 272 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 273 struct hif_exec_context *hif_ext_group; 274 size_t i; 275 276 for (i = 0; i < hif_state->hif_num_extgroup; i++) { 277 hif_ext_group = hif_state->hif_ext_group[i]; 278 279 if (!hif_ext_group) 280 return; 281 282 qdf_mem_set(hif_ext_group->sched_latency_stats, 283 sizeof(hif_ext_group->sched_latency_stats), 284 0x0); 285 } 286 } 287 288 qdf_export_symbol(hif_clear_napi_stats); 289 290 #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT 291 /** 292 * hif_get_poll_times_hist_str() - Get HIF poll times histogram string 293 * @stats: NAPI stats to get poll time buckets 294 * @buf: buffer to fill histogram string 295 * @buf_len: length of the buffer 296 * 297 * Return: void 298 */ 299 static void hif_get_poll_times_hist_str(struct qca_napi_stat *stats, char *buf, 300 uint8_t buf_len) 301 { 302 int i; 303 int str_index = 0; 304 305 for (i = 0; i < QCA_NAPI_NUM_BUCKETS; i++) 306 str_index += qdf_scnprintf(buf + str_index, buf_len - str_index, 307 "%u|", stats->poll_time_buckets[i]); 308 } 309 310 /** 311 * hif_exec_fill_poll_time_histogram() - fills poll time histogram for a NAPI 312 * @hif_ext_group: hif_ext_group of type NAPI 313 * 314 * The function is called at the end of a NAPI poll to calculate poll time 315 * buckets. 316 * 317 * Return: void 318 */ 319 static 320 void hif_exec_fill_poll_time_histogram(struct hif_exec_context *hif_ext_group) 321 { 322 struct qca_napi_stat *napi_stat; 323 unsigned long long poll_time_ns; 324 uint32_t poll_time_us; 325 uint32_t bucket_size_us = 500; 326 uint32_t bucket; 327 uint32_t cpu_id = qdf_get_cpu(); 328 329 poll_time_ns = qdf_time_sched_clock() - hif_ext_group->poll_start_time; 330 poll_time_us = qdf_do_div(poll_time_ns, 1000); 331 332 napi_stat = &hif_ext_group->stats[cpu_id]; 333 if (poll_time_ns > hif_ext_group->stats[cpu_id].napi_max_poll_time) 334 hif_ext_group->stats[cpu_id].napi_max_poll_time = poll_time_ns; 335 336 bucket = poll_time_us / bucket_size_us; 337 if (bucket >= QCA_NAPI_NUM_BUCKETS) 338 bucket = QCA_NAPI_NUM_BUCKETS - 1; 339 ++napi_stat->poll_time_buckets[bucket]; 340 } 341 342 /** 343 * hif_exec_poll_should_yield() - Local function deciding if NAPI should yield 344 * @hif_ext_group: hif_ext_group of type NAPI 345 * 346 * Return: true if NAPI needs to yield, else false 347 */ 348 static bool hif_exec_poll_should_yield(struct hif_exec_context *hif_ext_group) 349 { 350 bool time_limit_reached = false; 351 unsigned long long poll_time_ns; 352 int cpu_id = qdf_get_cpu(); 353 struct hif_softc *scn = HIF_GET_SOFTC(hif_ext_group->hif); 354 struct hif_config_info *cfg = &scn->hif_config; 355 356 poll_time_ns = qdf_time_sched_clock() - hif_ext_group->poll_start_time; 357 time_limit_reached = 358 poll_time_ns > cfg->rx_softirq_max_yield_duration_ns ? 1 : 0; 359 360 if (time_limit_reached) { 361 hif_ext_group->stats[cpu_id].time_limit_reached++; 362 hif_ext_group->force_break = true; 363 } 364 365 return time_limit_reached; 366 } 367 368 bool hif_exec_should_yield(struct hif_opaque_softc *hif_ctx, uint grp_id) 369 { 370 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 371 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 372 struct hif_exec_context *hif_ext_group; 373 bool ret_val = false; 374 375 if (!(grp_id < hif_state->hif_num_extgroup) || 376 !(grp_id < HIF_MAX_GROUP)) 377 return false; 378 379 hif_ext_group = hif_state->hif_ext_group[grp_id]; 380 381 if (hif_ext_group->type == HIF_EXEC_NAPI_TYPE) 382 ret_val = hif_exec_poll_should_yield(hif_ext_group); 383 384 return ret_val; 385 } 386 387 /** 388 * hif_exec_update_service_start_time() - Update NAPI poll start time 389 * @hif_ext_group: hif_ext_group of type NAPI 390 * 391 * The function is called at the beginning of a NAPI poll to record the poll 392 * start time. 393 * 394 * Return: None 395 */ 396 static inline 397 void hif_exec_update_service_start_time(struct hif_exec_context *hif_ext_group) 398 { 399 hif_ext_group->poll_start_time = qdf_time_sched_clock(); 400 } 401 402 void hif_print_napi_stats(struct hif_opaque_softc *hif_ctx) 403 { 404 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 405 struct hif_exec_context *hif_ext_group; 406 struct qca_napi_stat *napi_stats; 407 int i, j; 408 409 /* 410 * Max value of uint_32 (poll_time_bucket) = 4294967295 411 * Thus we need 10 chars + 1 space =11 chars for each bucket value. 412 * +1 space for '\0'. 413 */ 414 char hist_str[(QCA_NAPI_NUM_BUCKETS * 11) + 1] = {'\0'}; 415 416 QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_INFO_HIGH, 417 "NAPI[#]CPU[#] |scheds |polls |comps |dones |t-lim |max(us)|hist(500us buckets)"); 418 419 for (i = 0; 420 (i < hif_state->hif_num_extgroup && hif_state->hif_ext_group[i]); 421 i++) { 422 hif_ext_group = hif_state->hif_ext_group[i]; 423 for (j = 0; j < num_possible_cpus(); j++) { 424 napi_stats = &hif_ext_group->stats[j]; 425 if (!napi_stats->napi_schedules) 426 continue; 427 428 hif_get_poll_times_hist_str(napi_stats, 429 hist_str, 430 sizeof(hist_str)); 431 QDF_TRACE(QDF_MODULE_ID_HIF, 432 QDF_TRACE_LEVEL_INFO_HIGH, 433 "NAPI[%d]CPU[%d]: %7u %7u %7u %7u %7u %7llu %s", 434 i, j, 435 napi_stats->napi_schedules, 436 napi_stats->napi_polls, 437 napi_stats->napi_completes, 438 napi_stats->napi_workdone, 439 napi_stats->time_limit_reached, 440 qdf_do_div(napi_stats->napi_max_poll_time, 441 1000), 442 hist_str); 443 } 444 } 445 446 hif_print_napi_latency_stats(hif_state); 447 } 448 449 qdf_export_symbol(hif_print_napi_stats); 450 451 #else 452 453 static inline 454 void hif_get_poll_times_hist_str(struct qca_napi_stat *stats, char *buf, 455 uint8_t buf_len) 456 { 457 } 458 459 static inline 460 void hif_exec_update_service_start_time(struct hif_exec_context *hif_ext_group) 461 { 462 } 463 464 static inline 465 void hif_exec_fill_poll_time_histogram(struct hif_exec_context *hif_ext_group) 466 { 467 } 468 469 void hif_print_napi_stats(struct hif_opaque_softc *hif_ctx) 470 { 471 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 472 struct hif_exec_context *hif_ext_group; 473 struct qca_napi_stat *napi_stats; 474 int i, j; 475 476 QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_FATAL, 477 "NAPI[#ctx]CPU[#] |schedules |polls |completes |workdone"); 478 479 for (i = 0; i < hif_state->hif_num_extgroup; i++) { 480 if (hif_state->hif_ext_group[i]) { 481 hif_ext_group = hif_state->hif_ext_group[i]; 482 for (j = 0; j < num_possible_cpus(); j++) { 483 napi_stats = &(hif_ext_group->stats[j]); 484 if (napi_stats->napi_schedules != 0) 485 QDF_TRACE(QDF_MODULE_ID_HIF, 486 QDF_TRACE_LEVEL_FATAL, 487 "NAPI[%2d]CPU[%d]: " 488 "%7d %7d %7d %7d ", 489 i, j, 490 napi_stats->napi_schedules, 491 napi_stats->napi_polls, 492 napi_stats->napi_completes, 493 napi_stats->napi_workdone); 494 } 495 } 496 } 497 498 hif_print_napi_latency_stats(hif_state); 499 } 500 qdf_export_symbol(hif_print_napi_stats); 501 #endif /* WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT */ 502 503 static void hif_exec_tasklet_schedule(struct hif_exec_context *ctx) 504 { 505 struct hif_tasklet_exec_context *t_ctx = hif_exec_get_tasklet(ctx); 506 507 tasklet_schedule(&t_ctx->tasklet); 508 } 509 510 /** 511 * hif_exec_tasklet() - grp tasklet 512 * data: context 513 * 514 * return: void 515 */ 516 static void hif_exec_tasklet_fn(unsigned long data) 517 { 518 struct hif_exec_context *hif_ext_group = 519 (struct hif_exec_context *)data; 520 struct hif_softc *scn = HIF_GET_SOFTC(hif_ext_group->hif); 521 unsigned int work_done; 522 523 work_done = 524 hif_ext_group->handler(hif_ext_group->context, HIF_MAX_BUDGET); 525 526 if (hif_ext_group->work_complete(hif_ext_group, work_done)) { 527 qdf_atomic_dec(&(scn->active_grp_tasklet_cnt)); 528 hif_ext_group->irq_enable(hif_ext_group); 529 } else { 530 hif_exec_tasklet_schedule(hif_ext_group); 531 } 532 } 533 534 /** 535 * hif_latency_profile_measure() - calculate latency and update histogram 536 * hif_ext_group: hif exec context 537 * 538 * return: None 539 */ 540 #ifdef HIF_LATENCY_PROFILE_ENABLE 541 static void hif_latency_profile_measure(struct hif_exec_context *hif_ext_group) 542 { 543 int64_t cur_tstamp; 544 int64_t time_elapsed; 545 546 cur_tstamp = qdf_ktime_to_ms(qdf_ktime_get()); 547 548 if (cur_tstamp > hif_ext_group->tstamp) 549 time_elapsed = (cur_tstamp - hif_ext_group->tstamp); 550 else 551 time_elapsed = ~0x0 - (hif_ext_group->tstamp - cur_tstamp); 552 553 hif_ext_group->tstamp = cur_tstamp; 554 555 if (time_elapsed <= HIF_SCHED_LATENCY_BUCKET_0_2) 556 hif_ext_group->sched_latency_stats[0]++; 557 else if (time_elapsed <= HIF_SCHED_LATENCY_BUCKET_3_10) 558 hif_ext_group->sched_latency_stats[1]++; 559 else if (time_elapsed <= HIF_SCHED_LATENCY_BUCKET_11_20) 560 hif_ext_group->sched_latency_stats[2]++; 561 else if (time_elapsed <= HIF_SCHED_LATENCY_BUCKET_21_50) 562 hif_ext_group->sched_latency_stats[3]++; 563 else if (time_elapsed <= HIF_SCHED_LATENCY_BUCKET_51_100) 564 hif_ext_group->sched_latency_stats[4]++; 565 else if (time_elapsed <= HIF_SCHED_LATENCY_BUCKET_101_250) 566 hif_ext_group->sched_latency_stats[5]++; 567 else if (time_elapsed <= HIF_SCHED_LATENCY_BUCKET_251_500) 568 hif_ext_group->sched_latency_stats[6]++; 569 else 570 hif_ext_group->sched_latency_stats[7]++; 571 } 572 #else 573 static inline 574 void hif_latency_profile_measure(struct hif_exec_context *hif_ext_group) 575 { 576 } 577 #endif 578 579 /** 580 * hif_latency_profile_start() - Update the start timestamp for HIF ext group 581 * hif_ext_group: hif exec context 582 * 583 * return: None 584 */ 585 #ifdef HIF_LATENCY_PROFILE_ENABLE 586 static void hif_latency_profile_start(struct hif_exec_context *hif_ext_group) 587 { 588 hif_ext_group->tstamp = qdf_ktime_to_ms(qdf_ktime_get()); 589 } 590 #else 591 static inline 592 void hif_latency_profile_start(struct hif_exec_context *hif_ext_group) 593 { 594 } 595 #endif 596 597 #ifdef FEATURE_NAPI 598 #ifdef FEATURE_IRQ_AFFINITY 599 static inline int32_t 600 hif_is_force_napi_complete_required(struct hif_exec_context *hif_ext_group) 601 { 602 return qdf_atomic_inc_not_zero(&hif_ext_group->force_napi_complete); 603 } 604 #else 605 static inline int32_t 606 hif_is_force_napi_complete_required(struct hif_exec_context *hif_ext_group) 607 { 608 return 0; 609 } 610 #endif 611 612 /** 613 * hif_exec_poll() - napi poll 614 * napi: napi struct 615 * budget: budget for napi 616 * 617 * Return: mapping of internal budget to napi 618 */ 619 static int hif_exec_poll(struct napi_struct *napi, int budget) 620 { 621 struct hif_napi_exec_context *napi_exec_ctx = 622 qdf_container_of(napi, struct hif_napi_exec_context, napi); 623 struct hif_exec_context *hif_ext_group = &napi_exec_ctx->exec_ctx; 624 struct hif_softc *scn = HIF_GET_SOFTC(hif_ext_group->hif); 625 int work_done; 626 int normalized_budget = 0; 627 int actual_dones; 628 int shift = hif_ext_group->scale_bin_shift; 629 int cpu = smp_processor_id(); 630 631 hif_record_event(hif_ext_group->hif, hif_ext_group->grp_id, 632 0, 0, 0, HIF_EVENT_BH_SCHED); 633 634 hif_ext_group->force_break = false; 635 hif_exec_update_service_start_time(hif_ext_group); 636 637 if (budget) 638 normalized_budget = NAPI_BUDGET_TO_INTERNAL_BUDGET(budget, shift); 639 640 hif_latency_profile_measure(hif_ext_group); 641 642 work_done = hif_ext_group->handler(hif_ext_group->context, 643 normalized_budget); 644 645 actual_dones = work_done; 646 647 if (hif_is_force_napi_complete_required(hif_ext_group) || 648 (!hif_ext_group->force_break && work_done < normalized_budget)) { 649 hif_record_event(hif_ext_group->hif, hif_ext_group->grp_id, 650 0, 0, 0, HIF_EVENT_BH_COMPLETE); 651 napi_complete(napi); 652 qdf_atomic_dec(&scn->active_grp_tasklet_cnt); 653 hif_ext_group->irq_enable(hif_ext_group); 654 hif_ext_group->stats[cpu].napi_completes++; 655 } else { 656 /* if the ext_group supports time based yield, claim full work 657 * done anyways */ 658 hif_record_event(hif_ext_group->hif, hif_ext_group->grp_id, 659 0, 0, 0, HIF_EVENT_BH_FORCE_BREAK); 660 work_done = normalized_budget; 661 } 662 663 hif_ext_group->stats[cpu].napi_polls++; 664 hif_ext_group->stats[cpu].napi_workdone += actual_dones; 665 666 /* map internal budget to NAPI budget */ 667 if (work_done) 668 work_done = INTERNAL_BUDGET_TO_NAPI_BUDGET(work_done, shift); 669 670 hif_exec_fill_poll_time_histogram(hif_ext_group); 671 672 return work_done; 673 } 674 675 /** 676 * hif_exec_napi_schedule() - schedule the napi exec instance 677 * @ctx: a hif_exec_context known to be of napi type 678 */ 679 static void hif_exec_napi_schedule(struct hif_exec_context *ctx) 680 { 681 struct hif_napi_exec_context *n_ctx = hif_exec_get_napi(ctx); 682 ctx->stats[smp_processor_id()].napi_schedules++; 683 684 napi_schedule(&n_ctx->napi); 685 } 686 687 /** 688 * hif_exec_napi_kill() - stop a napi exec context from being rescheduled 689 * @ctx: a hif_exec_context known to be of napi type 690 */ 691 static void hif_exec_napi_kill(struct hif_exec_context *ctx) 692 { 693 struct hif_napi_exec_context *n_ctx = hif_exec_get_napi(ctx); 694 int irq_ind; 695 696 if (ctx->inited) { 697 napi_disable(&n_ctx->napi); 698 ctx->inited = 0; 699 } 700 701 for (irq_ind = 0; irq_ind < ctx->numirq; irq_ind++) 702 hif_irq_affinity_remove(ctx->os_irq[irq_ind]); 703 704 hif_core_ctl_set_boost(false); 705 netif_napi_del(&(n_ctx->napi)); 706 } 707 708 struct hif_execution_ops napi_sched_ops = { 709 .schedule = &hif_exec_napi_schedule, 710 .kill = &hif_exec_napi_kill, 711 }; 712 713 /** 714 * hif_exec_napi_create() - allocate and initialize a napi exec context 715 * @scale: a binary shift factor to map NAPI budget from\to internal 716 * budget 717 */ 718 static struct hif_exec_context *hif_exec_napi_create(uint32_t scale) 719 { 720 struct hif_napi_exec_context *ctx; 721 722 ctx = qdf_mem_malloc(sizeof(struct hif_napi_exec_context)); 723 if (!ctx) 724 return NULL; 725 726 ctx->exec_ctx.sched_ops = &napi_sched_ops; 727 ctx->exec_ctx.inited = true; 728 ctx->exec_ctx.scale_bin_shift = scale; 729 qdf_net_if_create_dummy_if((struct qdf_net_if *)&ctx->netdev); 730 netif_napi_add(&(ctx->netdev), &(ctx->napi), hif_exec_poll, 731 QCA_NAPI_BUDGET); 732 napi_enable(&ctx->napi); 733 734 return &ctx->exec_ctx; 735 } 736 #else 737 static struct hif_exec_context *hif_exec_napi_create(uint32_t scale) 738 { 739 hif_warn("FEATURE_NAPI not defined, making tasklet"); 740 return hif_exec_tasklet_create(); 741 } 742 #endif 743 744 745 /** 746 * hif_exec_tasklet_kill() - stop a tasklet exec context from being rescheduled 747 * @ctx: a hif_exec_context known to be of tasklet type 748 */ 749 static void hif_exec_tasklet_kill(struct hif_exec_context *ctx) 750 { 751 struct hif_tasklet_exec_context *t_ctx = hif_exec_get_tasklet(ctx); 752 int irq_ind; 753 754 if (ctx->inited) { 755 tasklet_disable(&t_ctx->tasklet); 756 tasklet_kill(&t_ctx->tasklet); 757 } 758 ctx->inited = false; 759 760 for (irq_ind = 0; irq_ind < ctx->numirq; irq_ind++) 761 hif_irq_affinity_remove(ctx->os_irq[irq_ind]); 762 } 763 764 struct hif_execution_ops tasklet_sched_ops = { 765 .schedule = &hif_exec_tasklet_schedule, 766 .kill = &hif_exec_tasklet_kill, 767 }; 768 769 /** 770 * hif_exec_tasklet_schedule() - allocate and initialize a tasklet exec context 771 */ 772 static struct hif_exec_context *hif_exec_tasklet_create(void) 773 { 774 struct hif_tasklet_exec_context *ctx; 775 776 ctx = qdf_mem_malloc(sizeof(struct hif_tasklet_exec_context)); 777 if (!ctx) 778 return NULL; 779 780 ctx->exec_ctx.sched_ops = &tasklet_sched_ops; 781 tasklet_init(&ctx->tasklet, hif_exec_tasklet_fn, 782 (unsigned long)ctx); 783 784 ctx->exec_ctx.inited = true; 785 786 return &ctx->exec_ctx; 787 } 788 789 /** 790 * hif_exec_get_ctx() - retrieve an exec context based on an id 791 * @softc: the hif context owning the exec context 792 * @id: the id of the exec context 793 * 794 * mostly added to make it easier to rename or move the context array 795 */ 796 struct hif_exec_context *hif_exec_get_ctx(struct hif_opaque_softc *softc, 797 uint8_t id) 798 { 799 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(softc); 800 801 if (id < hif_state->hif_num_extgroup) 802 return hif_state->hif_ext_group[id]; 803 804 return NULL; 805 } 806 807 int32_t hif_get_int_ctx_irq_num(struct hif_opaque_softc *softc, 808 uint8_t id) 809 { 810 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(softc); 811 812 if (id < hif_state->hif_num_extgroup) 813 return hif_state->hif_ext_group[id]->os_irq[0]; 814 return -EINVAL; 815 } 816 817 qdf_export_symbol(hif_get_int_ctx_irq_num); 818 819 #ifdef HIF_CPU_PERF_AFFINE_MASK 820 void hif_config_irq_set_perf_affinity_hint( 821 struct hif_opaque_softc *hif_ctx) 822 { 823 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 824 825 hif_config_irq_affinity(scn); 826 } 827 828 qdf_export_symbol(hif_config_irq_set_perf_affinity_hint); 829 #endif 830 831 QDF_STATUS hif_configure_ext_group_interrupts(struct hif_opaque_softc *hif_ctx) 832 { 833 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 834 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 835 struct hif_exec_context *hif_ext_group; 836 int i, status; 837 838 if (scn->ext_grp_irq_configured) { 839 hif_err("Called after ext grp irq configured"); 840 return QDF_STATUS_E_FAILURE; 841 } 842 843 for (i = 0; i < hif_state->hif_num_extgroup; i++) { 844 hif_ext_group = hif_state->hif_ext_group[i]; 845 status = 0; 846 qdf_spinlock_create(&hif_ext_group->irq_lock); 847 if (hif_ext_group->configured && 848 hif_ext_group->irq_requested == false) { 849 hif_ext_group->irq_enabled = true; 850 status = hif_grp_irq_configure(scn, hif_ext_group); 851 } 852 if (status != 0) { 853 hif_err("Failed for group %d", i); 854 hif_ext_group->irq_enabled = false; 855 } 856 } 857 858 scn->ext_grp_irq_configured = true; 859 860 return QDF_STATUS_SUCCESS; 861 } 862 863 qdf_export_symbol(hif_configure_ext_group_interrupts); 864 865 void hif_deconfigure_ext_group_interrupts(struct hif_opaque_softc *hif_ctx) 866 { 867 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 868 869 if (!scn || !scn->ext_grp_irq_configured) { 870 hif_err("scn(%pk) is NULL or grp irq not configured", scn); 871 return; 872 } 873 874 hif_grp_irq_deconfigure(scn); 875 scn->ext_grp_irq_configured = false; 876 } 877 878 qdf_export_symbol(hif_deconfigure_ext_group_interrupts); 879 880 #ifdef WLAN_SUSPEND_RESUME_TEST 881 /** 882 * hif_check_and_trigger_ut_resume() - check if unit-test command was used to 883 * to trigger fake-suspend command, if yes 884 * then issue resume procedure. 885 * @scn: opaque HIF software context 886 * 887 * This API checks if unit-test command was used to trigger fake-suspend command 888 * and if answer is yes then it would trigger resume procedure. 889 * 890 * Make this API inline to save API-switch overhead and do branch-prediction to 891 * optimize performance impact. 892 * 893 * Return: void 894 */ 895 static inline void hif_check_and_trigger_ut_resume(struct hif_softc *scn) 896 { 897 if (qdf_unlikely(hif_irq_trigger_ut_resume(scn))) 898 hif_ut_fw_resume(scn); 899 } 900 #else 901 static inline void hif_check_and_trigger_ut_resume(struct hif_softc *scn) 902 { 903 } 904 #endif 905 906 /** 907 * hif_check_and_trigger_sys_resume() - Check for bus suspend and 908 * trigger system resume 909 * @scn: hif context 910 * @irq: irq number 911 * 912 * Return: None 913 */ 914 static inline void 915 hif_check_and_trigger_sys_resume(struct hif_softc *scn, int irq) 916 { 917 if (scn->bus_suspended && scn->linkstate_vote) { 918 hif_info_rl("interrupt rcvd:%d trigger sys resume", irq); 919 qdf_pm_system_wakeup(); 920 } 921 } 922 923 /** 924 * hif_ext_group_interrupt_handler() - handler for related interrupts 925 * @irq: irq number of the interrupt 926 * @context: the associated hif_exec_group context 927 * 928 * This callback function takes care of dissabling the associated interrupts 929 * and scheduling the expected bottom half for the exec_context. 930 * This callback function also helps keep track of the count running contexts. 931 */ 932 irqreturn_t hif_ext_group_interrupt_handler(int irq, void *context) 933 { 934 struct hif_exec_context *hif_ext_group = context; 935 struct hif_softc *scn = HIF_GET_SOFTC(hif_ext_group->hif); 936 937 if (hif_ext_group->irq_requested) { 938 hif_latency_profile_start(hif_ext_group); 939 940 hif_record_event(hif_ext_group->hif, hif_ext_group->grp_id, 941 0, 0, 0, HIF_EVENT_IRQ_TRIGGER); 942 943 hif_ext_group->irq_disable(hif_ext_group); 944 /* 945 * if private ioctl has issued fake suspend command to put 946 * FW in D0-WOW state then here is our chance to bring FW out 947 * of WOW mode. 948 * 949 * The reason why you need to explicitly wake-up the FW is here: 950 * APSS should have been in fully awake through-out when 951 * fake APSS suspend command was issued (to put FW in WOW mode) 952 * hence organic way of waking-up the FW 953 * (as part-of APSS-host wake-up) won't happen because 954 * in reality APSS didn't really suspend. 955 */ 956 hif_check_and_trigger_ut_resume(scn); 957 958 hif_check_and_trigger_sys_resume(scn, irq); 959 960 qdf_atomic_inc(&scn->active_grp_tasklet_cnt); 961 962 hif_ext_group->sched_ops->schedule(hif_ext_group); 963 } 964 965 return IRQ_HANDLED; 966 } 967 968 /** 969 * hif_exec_kill() - grp tasklet kill 970 * scn: hif_softc 971 * 972 * return: void 973 */ 974 void hif_exec_kill(struct hif_opaque_softc *hif_ctx) 975 { 976 int i; 977 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 978 979 for (i = 0; i < hif_state->hif_num_extgroup; i++) 980 hif_state->hif_ext_group[i]->sched_ops->kill( 981 hif_state->hif_ext_group[i]); 982 983 qdf_atomic_set(&hif_state->ol_sc.active_grp_tasklet_cnt, 0); 984 } 985 986 #ifdef FEATURE_IRQ_AFFINITY 987 static inline void 988 hif_init_force_napi_complete(struct hif_exec_context *hif_ext_group) 989 { 990 qdf_atomic_init(&hif_ext_group->force_napi_complete); 991 } 992 #else 993 static inline void 994 hif_init_force_napi_complete(struct hif_exec_context *hif_ext_group) 995 { 996 } 997 #endif 998 999 /** 1000 * hif_register_ext_group() - API to register external group 1001 * interrupt handler. 1002 * @hif_ctx : HIF Context 1003 * @numirq: number of irq's in the group 1004 * @irq: array of irq values 1005 * @handler: callback interrupt handler function 1006 * @cb_ctx: context to passed in callback 1007 * @type: napi vs tasklet 1008 * 1009 * Return: QDF_STATUS 1010 */ 1011 QDF_STATUS hif_register_ext_group(struct hif_opaque_softc *hif_ctx, 1012 uint32_t numirq, uint32_t irq[], 1013 ext_intr_handler handler, 1014 void *cb_ctx, const char *context_name, 1015 enum hif_exec_type type, uint32_t scale) 1016 { 1017 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 1018 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1019 struct hif_exec_context *hif_ext_group; 1020 1021 if (scn->ext_grp_irq_configured) { 1022 hif_err("Called after ext grp irq configured"); 1023 return QDF_STATUS_E_FAILURE; 1024 } 1025 1026 if (hif_state->hif_num_extgroup >= HIF_MAX_GROUP) { 1027 hif_err("Max groups: %d reached", hif_state->hif_num_extgroup); 1028 return QDF_STATUS_E_FAILURE; 1029 } 1030 1031 if (numirq >= HIF_MAX_GRP_IRQ) { 1032 hif_err("Invalid numirq: %d", numirq); 1033 return QDF_STATUS_E_FAILURE; 1034 } 1035 1036 hif_ext_group = hif_exec_create(type, scale); 1037 if (!hif_ext_group) 1038 return QDF_STATUS_E_FAILURE; 1039 1040 hif_state->hif_ext_group[hif_state->hif_num_extgroup] = 1041 hif_ext_group; 1042 1043 hif_ext_group->numirq = numirq; 1044 qdf_mem_copy(&hif_ext_group->irq[0], irq, numirq * sizeof(irq[0])); 1045 hif_ext_group->context = cb_ctx; 1046 hif_ext_group->handler = handler; 1047 hif_ext_group->configured = true; 1048 hif_ext_group->grp_id = hif_state->hif_num_extgroup; 1049 hif_ext_group->hif = hif_ctx; 1050 hif_ext_group->context_name = context_name; 1051 hif_ext_group->type = type; 1052 hif_init_force_napi_complete(hif_ext_group); 1053 1054 hif_state->hif_num_extgroup++; 1055 return QDF_STATUS_SUCCESS; 1056 } 1057 qdf_export_symbol(hif_register_ext_group); 1058 1059 /** 1060 * hif_exec_create() - create an execution context 1061 * @type: the type of execution context to create 1062 */ 1063 struct hif_exec_context *hif_exec_create(enum hif_exec_type type, 1064 uint32_t scale) 1065 { 1066 hif_debug("%s: create exec_type %d budget %d\n", 1067 __func__, type, QCA_NAPI_BUDGET * scale); 1068 1069 switch (type) { 1070 case HIF_EXEC_NAPI_TYPE: 1071 return hif_exec_napi_create(scale); 1072 1073 case HIF_EXEC_TASKLET_TYPE: 1074 return hif_exec_tasklet_create(); 1075 default: 1076 return NULL; 1077 } 1078 } 1079 1080 /** 1081 * hif_exec_destroy() - free the hif_exec context 1082 * @ctx: context to free 1083 * 1084 * please kill the context before freeing it to avoid a use after free. 1085 */ 1086 void hif_exec_destroy(struct hif_exec_context *ctx) 1087 { 1088 struct hif_softc *scn = HIF_GET_SOFTC(ctx->hif); 1089 1090 if (scn->ext_grp_irq_configured) 1091 qdf_spinlock_destroy(&ctx->irq_lock); 1092 qdf_mem_free(ctx); 1093 } 1094 1095 /** 1096 * hif_deregister_exec_group() - API to free the exec contexts 1097 * @hif_ctx: HIF context 1098 * @context_name: name of the module whose contexts need to be deregistered 1099 * 1100 * This function deregisters the contexts of the requestor identified 1101 * based on the context_name & frees the memory. 1102 * 1103 * Return: void 1104 */ 1105 void hif_deregister_exec_group(struct hif_opaque_softc *hif_ctx, 1106 const char *context_name) 1107 { 1108 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 1109 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1110 struct hif_exec_context *hif_ext_group; 1111 int i; 1112 1113 for (i = 0; i < HIF_MAX_GROUP; i++) { 1114 hif_ext_group = hif_state->hif_ext_group[i]; 1115 1116 if (!hif_ext_group) 1117 continue; 1118 1119 hif_debug("%s: Deregistering grp id %d name %s\n", 1120 __func__, 1121 hif_ext_group->grp_id, 1122 hif_ext_group->context_name); 1123 1124 if (strcmp(hif_ext_group->context_name, context_name) == 0) { 1125 hif_ext_group->sched_ops->kill(hif_ext_group); 1126 hif_state->hif_ext_group[i] = NULL; 1127 hif_exec_destroy(hif_ext_group); 1128 hif_state->hif_num_extgroup--; 1129 } 1130 1131 } 1132 } 1133 qdf_export_symbol(hif_deregister_exec_group); 1134 1135 #ifdef DP_UMAC_HW_RESET_SUPPORT 1136 /** 1137 * hif_umac_reset_handler_tasklet() - Tasklet for UMAC HW reset interrupt 1138 * @data: UMAC HW reset HIF context 1139 * 1140 * return: void 1141 */ 1142 static void hif_umac_reset_handler_tasklet(unsigned long data) 1143 { 1144 struct hif_umac_reset_ctx *umac_reset_ctx = 1145 (struct hif_umac_reset_ctx *)data; 1146 1147 /* call the callback handler */ 1148 umac_reset_ctx->cb_handler(umac_reset_ctx->cb_ctx); 1149 } 1150 1151 /** 1152 * hif_umac_reset_irq_handler() - Interrupt service routine of UMAC HW reset 1153 * @irq: irq coming from kernel 1154 * @ctx: UMAC HW reset HIF context 1155 * 1156 * return: IRQ_HANDLED if success, else IRQ_NONE 1157 */ 1158 static irqreturn_t hif_umac_reset_irq_handler(int irq, void *ctx) 1159 { 1160 struct hif_umac_reset_ctx *umac_reset_ctx = ctx; 1161 1162 /* Schedule the tasklet and exit */ 1163 tasklet_hi_schedule(&umac_reset_ctx->intr_tq); 1164 1165 return IRQ_HANDLED; 1166 } 1167 1168 QDF_STATUS hif_register_umac_reset_handler(struct hif_opaque_softc *hif_scn, 1169 int (*handler)(void *cb_ctx), 1170 void *cb_ctx, int irq) 1171 { 1172 struct hif_softc *hif_sc = HIF_GET_SOFTC(hif_scn); 1173 struct hif_umac_reset_ctx *umac_reset_ctx; 1174 int ret; 1175 1176 if (!hif_sc) { 1177 hif_err("scn is null"); 1178 return QDF_STATUS_E_NULL_VALUE; 1179 } 1180 1181 umac_reset_ctx = &hif_sc->umac_reset_ctx; 1182 1183 umac_reset_ctx->cb_handler = handler; 1184 umac_reset_ctx->cb_ctx = cb_ctx; 1185 umac_reset_ctx->os_irq = irq; 1186 1187 /* Init the tasklet */ 1188 tasklet_init(&umac_reset_ctx->intr_tq, 1189 hif_umac_reset_handler_tasklet, 1190 (unsigned long)umac_reset_ctx); 1191 1192 /* Register the interrupt handler */ 1193 ret = pfrm_request_irq(hif_sc->qdf_dev->dev, irq, 1194 hif_umac_reset_irq_handler, 1195 IRQF_SHARED | IRQF_NO_SUSPEND, 1196 "umac_hw_reset_irq", 1197 umac_reset_ctx); 1198 if (ret) { 1199 hif_err("request_irq failed: %d", ret); 1200 return qdf_status_from_os_return(ret); 1201 } 1202 1203 umac_reset_ctx->irq_configured = true; 1204 1205 return QDF_STATUS_SUCCESS; 1206 } 1207 1208 qdf_export_symbol(hif_register_umac_reset_handler); 1209 1210 QDF_STATUS hif_unregister_umac_reset_handler(struct hif_opaque_softc *hif_scn) 1211 { 1212 struct hif_softc *hif_sc = HIF_GET_SOFTC(hif_scn); 1213 struct hif_umac_reset_ctx *umac_reset_ctx; 1214 int ret; 1215 1216 if (!hif_sc) { 1217 hif_err("scn is null"); 1218 return QDF_STATUS_E_NULL_VALUE; 1219 } 1220 1221 umac_reset_ctx = &hif_sc->umac_reset_ctx; 1222 if (!umac_reset_ctx->irq_configured) { 1223 hif_err("unregister called without a prior IRQ configuration"); 1224 return QDF_STATUS_E_FAILURE; 1225 } 1226 1227 ret = pfrm_free_irq(hif_sc->qdf_dev->dev, 1228 umac_reset_ctx->os_irq, 1229 umac_reset_ctx); 1230 if (ret) { 1231 hif_err("free_irq failed: %d", ret); 1232 return qdf_status_from_os_return(ret); 1233 } 1234 umac_reset_ctx->irq_configured = false; 1235 1236 tasklet_disable(&umac_reset_ctx->intr_tq); 1237 tasklet_kill(&umac_reset_ctx->intr_tq); 1238 1239 umac_reset_ctx->cb_handler = NULL; 1240 umac_reset_ctx->cb_ctx = NULL; 1241 1242 return QDF_STATUS_SUCCESS; 1243 } 1244 1245 qdf_export_symbol(hif_unregister_umac_reset_handler); 1246 #endif 1247